Semiconductor device

Abstract

The present disclosure provides semiconductor devices. A method of manufacturing a memory device includes sequentially forming a primary selector device layer, a primary intermediate electrode layer, and a primary variable resistance layer on a substrate and then etching the primary selector device layer, the primary intermediate electrode layer, and the primary variable resistance layer, thereby forming a selector device, an intermediate electrode, and a variable resistance layer. At least one of a side portion of the selector device and a side portion of the variable resistance layer is removed such that a first width of the intermediate electrode in a first direction parallel to a top of the substrate is greater than a second width of the variable resistance layer in the first direction or a third width of the selector device in the first direction. A cap layer is formed on at least one of a sidewall of the etched side portion of the selector device and a sidewall of the etched side portion of the variable resistance layer.

Description

[0001] This application is a divisional application of Samsung Electronics Co., Ltd.'s invention patent application filed on February 16, 2017, entitled "Storage Device and Method of Manufacturing Storage Device" with application number 201710083498.6. Technical Field

[0002] Exemplary embodiments of the present invention relate to storage devices, and more particularly, to methods of manufacturing storage devices. Background Technology

[0003] With the trend towards lighter, thinner, and smaller electronic products, the need for high integration of semiconductor devices is increasing. Memory devices with a three-dimensional (3D) intersection structure in which memory cells are located at the intersection between two electrodes have been proposed. When memory devices with an intersection structure are scaled down, the width and / or thickness of virtually all layers in each memory device are also reduced. Consequently, the electrical characteristics and reliability of the scaled-down memory devices decrease. Summary of the Invention

[0004] Exemplary embodiments of the present invention provide a memory device having a cross-point array type and a method for manufacturing the memory device, which can have excellent electrical characteristics and improved reliability.

[0005] According to an exemplary embodiment of the present invention, a method of manufacturing a memory device includes sequentially forming a primary select device layer, a primary intermediate electrode layer, and a primary variable resistor layer on a substrate. The primary select device layer, the primary intermediate electrode layer, and the primary variable resistor layer are etched, thereby forming a select device, an intermediate electrode, and a variable resistor layer sequentially stacked on the substrate. At least one of a side portion of the select device and a side portion of the variable resistor layer is removed such that a first width of the intermediate electrode in a first direction parallel to the top of the substrate is greater than a second width of the variable resistor layer in the first direction or a third width of the select device in the first direction. A capping layer is formed on at least one of the sidewalls of the etched side portions of the select device and the sidewalls of the etched side portions of the variable resistor layer.

[0006] According to an exemplary embodiment of the present invention, a method of manufacturing a memory device includes sequentially forming a primary select device layer, a primary intermediate electrode layer, and a primary variable resistor layer on a substrate. The primary select device layer, the primary intermediate electrode layer, and the primary variable resistor layer are etched, thereby forming a select device, an intermediate electrode, and a variable resistor layer sequentially stacked on the substrate. At least one of a side portion of the select device and a side portion of the variable resistor layer is removed, such that a first width of the intermediate electrode in a first direction parallel to the top of the substrate is greater than a second width of the variable resistor layer in the first direction or a third width of the select device in the first direction. A capping layer is formed on at least one of the sidewalls of the etched side portions of the select device and the sidewalls of the etched side portions of the variable resistor layer. An insulating pattern is formed on the sidewalls of the capping layer and the sidewalls of the intermediate electrode using a material having a dielectric constant smaller than that of the capping layer.

[0007] According to an exemplary embodiment of the present invention, a memory device includes a plurality of first word lines extending in a first direction parallel to the top of a substrate. A plurality of bit lines extend on the substrate in a second direction, different from the first direction. A plurality of memory cells are respectively disposed at the intersections between the plurality of bit lines and the plurality of first word lines, each of the plurality of memory cells including a select device, an intermediate electrode, and a variable resistance layer. A first capping layer is disposed on the sidewall of a recessed portion of each variable resistance layer, and a second capping layer is disposed on the sidewall of a recessed portion of each select device. The second capping layer is spaced apart from the first capping layer. Attached Figure Description

[0008] The above and other features of the present invention will become more apparent from the detailed description of exemplary embodiments of the invention with reference to the accompanying drawings, in which:

[0009] Figure 1 This is an equivalent circuit diagram of a storage device according to an exemplary embodiment of the present invention.

[0010] Figure 2 This is a perspective view illustrating an exemplary embodiment of a storage device according to a concept of the present invention;

[0011] Figure 3 It is along Figure 2 A cross-sectional view taken from lines X1-X1' and Y1-Y1';

[0012] Figure 4 It is along Figure 2 Cross-sectional views of lines X2-X2' and Y2-Y2';

[0013] Figure 5 It is a schematic diagram showing the voltage-current curve of an OTS device with bidirectional threshold switching (OTS) characteristics.

[0014] Figure 6 This is a cross-sectional view illustrating a storage device according to an exemplary embodiment of the concept of the present invention;

[0015] Figure 7 This is a cross-sectional view illustrating a storage device according to an exemplary embodiment of the concept of the present invention;

[0016] Figure 8 This is a cross-sectional view illustrating a storage device according to an exemplary embodiment of the concept of the present invention;

[0017] Figure 9 This is a cross-sectional view illustrating a storage device according to an exemplary embodiment of the concept of the present invention;

[0018] Figure 10 This is a perspective view illustrating an exemplary embodiment of a storage device according to a concept of the present invention;

[0019] Figure 11 It is along Figure 10 A cross-sectional view taken from lines X1-X1' and Y1-Y1';

[0020] Figure 12 This is an equivalent circuit diagram of a storage device according to an exemplary embodiment of the present invention.

[0021] Figure 13 This is a perspective view illustrating an exemplary embodiment of a storage device according to a concept of the present invention;

[0022] Figure 14 It is along Figure 13 A cross-sectional view taken by line X1-X1';

[0023] Figures 15A to 15O This is a cross-sectional view illustrating a method for manufacturing a storage device according to an exemplary embodiment of the concept of the present invention;

[0024] Figures 16A to 16G This is a cross-sectional view illustrating a method for manufacturing a storage device according to an exemplary embodiment of the concept of the present invention;

[0025] Figures 17A to 17D This is a cross-sectional view illustrating a method for manufacturing a storage device according to an exemplary embodiment of the concept of the present invention. Detailed Implementation

[0026] Figure 1 This is an equivalent circuit diagram of a storage device according to an exemplary embodiment of the present invention.

[0027] refer to Figure 1The memory device 100 may include a plurality of word lines WL1 to WL4 extending along a first direction and spaced apart from each other in a second direction perpendicular to the first direction. The memory device 100 may include a plurality of bit lines BL1 to BL4 extending along the second direction and spaced apart from each other in the first direction. The memory device 100 may include a memory cell MC located at each intersection between the word lines WL1 to WL4 and the bit lines BL1 to BL4.

[0028] A memory cell MC may include a variable resistor layer ME for storing information and a selection device SW for selecting the memory cell MC. In the memory cell MC located between word line WL1 and bit line BL1, the variable resistor layer ME may be electrically connected to word line WL1, the selection device SW may be electrically connected to bit line BL1, and the variable resistor layer ME and the selection device SW may be connected in series with each other. However, exemplary embodiments of the present invention are not limited thereto. For example, in one exemplary embodiment of the present invention, in the memory cell MC, the selection device SW may be directly connected to word line WL1, and the variable resistor layer ME may be directly connected to bit line BL1.

[0029] A voltage can be applied to the variable resistance layer ME of the memory cell MC via word lines WL1 to WL4 and bit lines BL1 to BL4, thus allowing current to flow within the variable resistance layer ME. The variable resistance layer ME may include a phase change material layer that reversibly changes between a first state and a second state. However, the variable resistance layer ME is not limited to this. For example, in an exemplary embodiment of the present invention, the variable resistance layer ME may include any variable resistor whose resistance value changes according to the voltage applied thereto. For example, the resistance of the variable resistance layer ME may reversibly change between a first state and a second state depending on the voltage applied to the variable resistance layer ME of the selected memory cell MC.

[0030] The storage cell MC can store digital information such as "0" or "1" according to the resistance changes of the variable resistance layer ME, and the digital information can be erased from the storage cell MC. For example, data can be written to the storage cell MC as a high resistance state "0" and a low resistance state "1". Writing from a high resistance state "0" to a low resistance state "1" can be called a set operation, and writing from a low resistance state "1" to a high resistance state "0" can be called a reset operation. However, the storage cell MC of the exemplary embodiment of the present invention is not limited to digital information corresponding only to the high resistance state "0" and the low resistance state "1", but can store various resistance states.

[0031] Any memory cell MC can be addressed by selecting word lines WL1 to WL4 and bit lines BL1 to BL4 and can be programmed by applying a certain signal between word lines WL1 to WL4 and bit lines BL1 to BL4. Information based on the resistance value of the variable resistor configured for any memory cell MC can be read by measuring the current value via bit lines BL1 to BL4.

[0032] In a storage device 100 according to an exemplary embodiment of the present invention, a plurality of cover layers 142 and 144 (see, for example) Figure 2 These can be formed on the sidewalls of the variable resistance layer ME and the selection device SW, respectively. For example, reference... Figure 2 Multiple capping layers 142 can be formed on the sidewalls of the variable resistor layer 132, and multiple capping layers 144 can be formed on the sidewalls of the selector 134. Multiple insulating patterns 150 and 160 (see, for example) include materials having a lower dielectric constant than those of the capping layers 142 and 144. Figure 2 These can be formed in the space between adjacent memory cells (MCs). For example, see reference... Figure 2 The plurality of insulating patterns 150 and 160 can be formed between adjacent memory cell pillars 130. Therefore, the RC delay caused by the reduction in the size of the memory device 100 can be reduced or eliminated, thus allowing the memory device 100 to operate at a relatively high speed.

[0033] Figure 2 This is a perspective view illustrating an exemplary embodiment of a storage device according to a concept of the present invention. Figure 3 It is along Figure 2 The cross-sectional view taken by lines X1-X1' and Y1-Y1'. Figure 4 It is along Figure 2 The cross-sectional view taken by lines X2-X2' and Y2-Y2'.

[0034] refer to Figures 2 to 4 The memory device 100 may include a plurality of word lines 110 extending in a first direction (e.g., the X direction) and a plurality of bit lines 120 extending in a second direction (e.g., the Y direction) perpendicular to the first direction on the substrate 102.

[0035] An insulating interlayer 105 may be disposed on the substrate 102. The insulating interlayer 105 may include an oxide such as silicon oxide, or a nitride such as silicon nitride. The insulating interlayer 105 may electrically decouple the plurality of word lines 110 from the substrate 102.

[0036] The plurality of word lines 110 and the plurality of bit lines 120 may each comprise a metal, a conductive metal nitride, a conductive metal oxide, or a combination thereof. In an exemplary embodiment of the present invention, the plurality of word lines 110 and the plurality of bit lines 120 may each comprise tungsten (W), tungsten nitride (WN), gold (Au), silver (Ag), copper (Cu), aluminum (Al), titanium aluminum nitride (TiAlN), iridium (Ir), platinum (Pt), palladium (Pd), ruthenium (Ru), zirconium (Zr), rhodium (Rh), nickel (Ni), cobalt (Co), chromium (Cr), tin (Sn), zinc (Zn), indium tin oxide (ITO), alloys thereof, or combinations thereof. In an exemplary embodiment of the present invention, the plurality of word lines 110 and the plurality of bit lines 120 may each comprise a metal layer and a conductive barrier layer covering at least a portion of the metal layer. The conductive barrier layer may include, for example, titanium (Ti), TiN, tantalum (Ta), TaN, or a combination thereof.

[0037] refer to Figures 2 to 4 According to an exemplary embodiment of the present invention, the plurality of word lines 110 may be disposed on the substrate 102 and the plurality of bit lines 120 may be disposed on the plurality of word lines 110, but the exemplary embodiment of the present invention is not limited thereto. According to an exemplary embodiment of the present invention, the plurality of bit lines 120 may extend on the substrate 102 in a first direction or a second direction, and the plurality of word lines 110 may extend on the plurality of bit lines 120 in the second direction or the first direction.

[0038] refer to Figure 2 Each word line 110 extending in a first direction (e.g., the X direction) may intersect each bit line 120 extending in a second direction (e.g., the Y direction). Multiple memory cells MC may be respectively disposed at multiple intersection points between the multiple word lines 110 and the multiple bit lines 120.

[0039] Each of the plurality of memory cells MC may include a memory cell pillar 130. Each memory cell pillar may include a top electrode TE, a variable resistance layer 132, a middle electrode ME, a selection device 134, and a bottom electrode BE.

[0040] In one exemplary embodiment of the present invention, the variable resistance layer 132 may include a phase change material that reversibly changes between a crystalline and an amorphous state depending on the duration of heating. For example, the variable resistance layer 132 may include a material whose phase changes reversibly due to Joule heating generated by a voltage applied across the two ends of the variable resistance layer 132. The resistance of this material can change with the phase transition. The phase change material can be in a high-resistivity state in the amorphous phase and in a low-resistivity state in the crystalline phase. The high-resistivity state can be defined as 0, and the low-resistivity state can be defined as 1, so that data can be stored in the variable resistance layer 132.

[0041] In one exemplary embodiment of the present invention, the variable resistance layer 132 may include one or more elements from Group VI of the periodic table (e.g., chalcogens), and may additionally include one or more chemical modifiers from Group III, IV, or V. For example, the variable resistance layer 132 may include Ge-Sb-Te. A chemical composition designation including a hyphen (-) may represent a compound or an element included in a compound, and may represent the full chemical formula of the represented element. For example, Ge-Sb-Te may be a material such as Ge2Sb2Te5, Ge2Sb2Te7, Ge1Sb2Te4, Ge1Sb4Te7, or the like.

[0042] In addition to Ge-Sb-Te, the variable resistance layer 132 may also include various phase change materials. For example, the variable resistance layer 132 may include Ge-Te, Sb-Te, In-Se, Ga-Sb, In-Sb, As-Te, Al-Te, Bi-Sb-Te (BST), In-Sb-Te (IST), Ge-Sb-Te, Te-Ge-As, Te-Sn-Se, Ge-Se-Ga, Bi-Se-Sb, Ga-Se-Te, Sn-Sb-Te, In-Sb-Ge, In-Ge-Te, Ge-Sn-Te, Ge-Bi-Te, Ge-Te-Se, As-Sb-Te, Sn-Sb-B i. Ge-Te-O, Te-Ge-Sb-S, Te-Ge-Sn-O, Te-Ge-Sn-Au, Pd-Te-Ge-Sn, In-Se-Ti-Co, Ge-Sb-Te-Pd, Ge-Sb-Te-Co, Sb-Te-Bi-Se, At least one of Ag-In-Sb-Te, Ge-Sb-Se-Te, Ge-Sn-Sb-Te, Ge-Te-Sn-Ni, Ge-Te-Sn-Pd, Ge-Te-Sn-Pt, In-Sn-Sb-Te or As-Ge-Sb-Te or a combination thereof.

[0043] Each element included in the variable resistivity layer 132 can have a different stoichiometric ratio. The crystallization temperature, melting temperature, phase transition rate based on crystallization energy, and data retention characteristics of the variable resistivity layer 132 can be adjusted based on the stoichiometric ratio of each element.

[0044] The variable resistance layer 132 may include at least one impurity such as carbon (C), nitrogen (N), silicon (Si), oxygen (O), bismuth (Bi), or tin (Sn). The drive current of the memory device 100 can be varied by said at least one impurity. The variable resistance layer 132 may include at least one metal. For example, the variable resistance layer 132 may include at least one of aluminum (Al), gallium (Ga), tin (Sn), titanium (Ti), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), molybdenum (Mo), ruthenium (Ru), palladium (Pd), hafnium (Hf), tantalum (Ta), iridium (Ir), platinum (Pt), zirconium (Zr), thallium (Tl), lead (Pb), titanium (Ti), and polonium (Po). This metal can improve the electrical and thermal conductivity of the variable resistance layer 132, and thus can increase the crystallization rate, thereby increasing the setup speed. This metal can improve the data retention characteristics of the variable resistance layer 132.

[0045] The variable resistance layer 132 can have a multilayer structure in which two or more layers with different physical properties are stacked. The number or thickness of the layers can be selected as required. Barrier layers can be formed between the layers. Barrier layers can prevent material from diffusing between the layers. For example, when forming subsequent layers among the layers, barrier layers can reduce diffusion from the preceding layer.

[0046] The variable resistance layer 132 may have a superlattice structure in which multiple layers comprising different materials are alternately stacked. For example, the variable resistance layer 132 may include a structure in which a first layer comprising Ge-Te and a second layer comprising Sb-Te are alternately stacked. However, exemplary embodiments of the inventive concept are not limited thereto, and the material of the first layer is not limited to Ge-Te, nor is the material of the second layer limited to Sb-Te. Both the first and second layers may comprise the various materials described above.

[0047] The variable resistance layer 132 has been described above as comprising a phase change material. However, exemplary embodiments of the present invention are not limited thereto. For example, in one exemplary embodiment of the present invention, the variable resistance layer 132 of the storage device 100 may comprise various materials having resistance-changing characteristics.

[0048] In some exemplary embodiments of the present invention, when the variable resistance layer 132 comprises a transition metal oxide, the storage device 100 may be a resistive random access memory (ReRAM). In the variable resistance layer 132 comprising a transition metal oxide, at least one electrical path may be formed or depleted in the variable resistance layer 132 via a programming operation. When an electrical path is formed, the variable resistance layer 132 may have a low resistance value, and when an electrical path is depleted, the variable resistance layer 132 may have a high resistance value. The storage device 100 may store data by utilizing the resistance difference of the variable resistance layer 132.

[0049] When the variable resistance layer 132 comprises a transition metal oxide, the transition metal oxide may include at least one metal such as Ta, Zr, Ti, Hf, Mn, Y, Ni, Co, Zn, Nb, Cu, Fe, or Cr. For example, the transition metal oxide may have a composition including Ta2O 5-x ZrO 2-x TiO 2-x HfO 2-x MnO 2-x Y2O 3-x NiO 1-y Nb2O 5-x CuO 1-y and Fe2O 3-x A single-layer or multi-layer structure of at least one material selected from the above. In the materials described above, x can be selected in the range of 0 ≤ x ≤ 1.5, and y can be selected in the range of 0 ≤ y ≤ 0.5. However, exemplary embodiments of the inventive concept are not limited thereto.

[0050] In an exemplary embodiment of the present invention, when the variable resistor layer 132 has a magnetic tunnel junction (MJT) structure comprising two electrodes containing magnetic material and a dielectric disposed between the two magnetic electrodes, the storage device 100 may be a magnetic random access memory (MRAM).

[0051] The two electrodes can be a magnetized fixed layer and a magnetized free layer, respectively, and the dielectric disposed therebetween can be a tunneling barrier layer. The magnetized fixed layer can have a magnetization direction fixed in one direction, and the magnetized free layer can have a magnetization direction that can be parallel or antiparallel to the magnetization direction of the magnetized fixed layer. The magnetization directions of the magnetized fixed layer and the magnetized free layer can be parallel to one surface of the tunneling barrier layer, but the exemplary embodiments of the present invention are not limited thereto. In an exemplary embodiment of the present invention, the magnetization directions of the magnetized fixed layer and the magnetized free layer can be perpendicular to the one surface of the tunneling barrier layer.

[0052] When the magnetization direction of the free magnetization layer is parallel to the magnetization direction of the fixed magnetization layer, the variable resistance layer 132 can have a first resistance value. When the magnetization direction of the free magnetization layer is antiparallel to the magnetization direction of the fixed magnetization layer, the variable resistance layer 132 can have a second resistance value. By using such a difference in resistance value, the storage device 100 can store data. The magnetization direction of the free magnetization layer can be changed by the spin torque of the electrons included in the programming current.

[0053] Both the magnetization fixed layer and the magnetization free layer may comprise magnetic materials. In this case, the magnetization fixed layer may further comprise an antiferromagnetic material fixed in the magnetization direction of the ferromagnetic material included in the magnetization fixed layer. The tunneling barrier layer may comprise at least one oxide such as Mg, Ti, Al, MgZn or MgB, but exemplary embodiments of the present invention are not limited thereto.

[0054] Selector 134 can be a current control element for controlling the flow of current. Selector 134 can be, for example, a current control element with bidirectional threshold switching (OTS) characteristics.

[0055] The selector 134 may include a material having a resistance that changes according to the level of the voltage applied across its terminals, and may include, for example, a material having an OTS characteristic. For example, when a voltage lower than the threshold voltage VT is applied to the selector 134, the selector 134 may be in a high-resistance state, and when a voltage higher than the threshold voltage VT is applied to the selector 134, the selector 134 may be in a low-resistance state and current may begin to flow. When the current flowing through the selector 134 becomes lower than the holding current, the selector 134 may return to a high-resistance state. The OTS characteristic of the selector 134 will be referenced... Figure 5 It is described in more detail below.

[0056] Selection device 134 may include a chalcogenide material as an OTS material layer. Representative examples of chalcogenide materials may include one or more elements from Group VI of the periodic table (e.g., chalcogen elements) and may additionally include one or more chemical modifiers from Group III, IV, or V. Exemplary chalcogen elements that can be included in selection device 134 may include sulfur (S), selenium (Se), or tellurium (Te). Chalcogen elements are characterized by including divalent bonds and lone pairs of electrons. The divalent bonds cause the formation of chain and ring structures by bonding the chalcogen elements used to form the chalcogenide material, and the lone pairs of electrons provide an electron source for forming conductive filaments. For example, trivalent and tetravalent modifiers such as Al, Ga, indium (In), germanium (Ge), Sn, Si, phosphorus (P), arsenic (As), or antimony (Sb) may be added to the chain and ring structures of the chalcogen elements to determine the structural stiffness of the chalcogenide material, and the chalcogenide material may be classified as a switching material or a phase change material based on its ability to perform crystallization or other structural rearrangements.

[0057] In some exemplary embodiments of the present invention, the selected device 134 may include Si, Te, As, Ge, In, or combinations thereof. For example, the selected device 134 may include approximately 14% Si, approximately 39% Te, approximately 37% As, approximately 9% Ge, and approximately 1% In. Percentages represent atomic percentages when the total atomic elements are 100%.

[0058] Selected device 134 may include Si, Te, As, Ge, S, Se, or combinations thereof. For example, selected device 134 may include approximately 5% Si, approximately 34% Te, approximately 28% As, approximately 11% Ge, approximately 21% S, and approximately 1% Se.

[0059] Selected device 134 may include Si, Te, As, Ge, S, Se, Sb or combinations thereof. For example, selected device 134 may include approximately 21% Te, approximately 10% As, approximately 15% Ge, approximately 2% S, approximately 50% Se and approximately 2% Sb.

[0060] In a storage device 100 according to an exemplary embodiment of the present invention, the selection device 134 is not limited to an OTS material layer. For example, the selection device 134 may include various material layers having the function of a selection device, and is not limited to an OTS material layer. For example, the selection device 134 may include a diode, a tunnel junction, a PNP diode, or a bipolar junction transistor (BJT), or may employ hybrid ion-electron conduction (MIEC).

[0061] The bottom electrode BE can be disposed between the multiple word lines 110 and the select device 134. The middle electrode ME can be disposed between the select device 134 and the variable resistor layer 132. The top electrode TE can be disposed between the variable resistor layer 132 and the multiple bit lines 120.

[0062] In an exemplary embodiment of the present invention, the bottom electrode BE, the intermediate electrode ME, and the top electrode TE may all comprise a metal, a conductive metal nitride, a conductive metal oxide, or a combination thereof. At least one of the bottom electrode BE, the intermediate electrode ME, and the top electrode TE may comprise a conductive layer comprising a metal or a conductive metal nitride, and at least one conductive barrier layer covering at least a portion of the conductive layer. The conductive barrier layer may comprise a metal oxide, a metal nitride, or a combination thereof, but the exemplary embodiment of the present invention is not limited thereto.

[0063] In an exemplary embodiment of the present invention, the top electrode TE or intermediate electrode ME contacting the variable resistance layer 132 may include a conductive material that generates heat sufficient to cause a phase transition in the variable resistance layer 132. For example, the top electrode TE or intermediate electrode ME may include refractory metals such as TiN, TiSiN, TiAlN, TaSiN, TaAlN, TaN, WSi, WN, TiW, MoN, NbN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoAlN, TiAl, TiON, TiAlON, WON, TaON, C, SiC, SiCN, CN, TiCN, TaCN or combinations thereof, their nitrides, or carbon-based conductive materials.

[0064] In an exemplary embodiment of the present invention, the heater electrode may be disposed between the variable resistivity layer 132 and the top electrode TE or between the variable resistivity layer 132 and the intermediate electrode ME. The heater electrode may include a conductive material that generates heat sufficient to cause a phase change in the variable resistivity layer 132. For example, the heater electrode may include refractory metals such as TiN, TiSiN, TiAlN, TaSiN, TaAlN, TaN, WSi, WN, TiW, MoN, NbN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoAlN, TiAl, TiON, TiAlON, WON, TaON, C, SiC, SiCN, CN, TiCN, TaCN or combinations thereof, their nitrides, or carbon-based conductive materials.

[0065] refer to Figures 2 to 4The variable resistance layer 132 may be disposed on the selector 134, with the intermediate electrode ME disposed between the selector 134 and the variable resistance layer 132; however, exemplary embodiments of the present invention are not limited thereto. In an exemplary embodiment of the present invention, the selector 134 may be disposed on the variable resistance layer 132, with the intermediate electrode ME disposed between the variable resistance layer 132 and the selector 134. The bottom electrode BE or the intermediate electrode ME contacting the variable resistance layer 132 may comprise a conductive material that generates heat sufficient to cause a phase change in the variable resistance layer 132. A heater electrode may be disposed between the variable resistance layer 132 and the bottom electrode BE or between the variable resistance layer 132 and the intermediate electrode ME.

[0066] Multiple capping layers 142 and 144 can be formed on the sidewalls of the multiple memory cell pillars 130, respectively. The first capping layer 142 can be disposed on the sidewall of the variable resistor layer 132, and the second capping layer 144 can be disposed on the sidewall of the select device 134.

[0067] In one exemplary embodiment of the present invention, the first capping layer 142 may surround the sidewall of the variable resistance layer 132 and may contact the bottom of the top electrode TE and the top of the intermediate electrode ME. (See reference...) Figure 2 The first capping layer 142 may surround substantially the entire portion of the sidewall of the variable resistance layer 132, but exemplary embodiments of the inventive concept are not limited thereto.

[0068] The first capping layer 142 may include a pair of first portions 142X disposed on the sidewall of the variable resistance layer 132 and spaced apart from each other in a second direction (e.g., the Y direction), and a pair of second portions 142Y disposed on the sidewall of the variable resistance layer 132 and spaced apart from each other in a first direction (e.g., the X direction). The pair of second portions 142Y may contact the ends of the pair of first portions 142X, and the pair of first portions 142X and the pair of second portions 142Y may surround the sidewall of the variable resistance layer 132.

[0069] refer to Figure 3The pair of first portions 142X included in the first capping layer 142 may each include an outer wall 142X-OS and an inner wall 142X-IS extending in a first direction (e.g., the X direction). The inner wall 142X-IS of the first capping layer 142 may contact the sidewall of the variable resistor layer 132. In an exemplary embodiment of the inventive concept, the inner wall 142X-IS of the first capping layer 142 may be substantially flat along a third direction (e.g., the Z direction). For example, the inner wall 142X-IS of the first capping layer 142 may be vertically flat. The outer wall 142X-OS of the first capping layer 142 may be aligned with the sidewall of the intermediate electrode ME. The extension surface of the outer wall 142X-OS of the first capping layer 142 may be disposed on a plane substantially the same as the extension surface of the sidewall of the intermediate electrode ME.

[0070] refer to Figure 3 The pair of second portions 142Y included in the first capping layer 142 may each comprise an outer wall 142Y-OS and an inner wall 142Y-IS extending in a second direction (e.g., the Y direction). The inner wall 142Y-IS of the first capping layer 142 that contacts the sidewall of the variable resistance layer 132 may be substantially flat along a third direction (e.g., the Z direction). For example, the inner wall 142Y-IS of the first capping layer 142 that contacts the sidewall of the variable resistance layer 132 may be vertically flat. The outer wall 142Y-OS of the first capping layer 142 may be aligned with the sidewall of the intermediate electrode ME.

[0071] In one exemplary embodiment of the present invention, the second cover layer 144 may surround the sidewall of the selection device 134 and may contact the bottom of the intermediate electrode ME and the top of the bottom electrode BE. (See reference...) Figure 2 The second cover layer 144 may surround substantially the entire portion of the sidewall of the selection device 134, but exemplary embodiments of the inventive concept are not limited thereto.

[0072] The second cover layer 144 may include at least two third portions 144X disposed on the sidewall of the selector 134 and spaced apart from each other along a second direction (e.g., the Y direction), and at least two fourth portions 144Y disposed on the sidewall of the selector 134 and spaced apart from each other along a first direction (e.g., the X direction). The fourth portions 144Y may contact the ends of the pair of third portions 144X. The third portions 144X and the fourth portions 144Y may surround the sidewall of the selector 134.

[0073] refer to Figure 3The pair of third portions 144X included in the second capping layer 144 may each include an outer wall 144X-OS and an inner wall 144X-IS extending in a first direction (e.g., the X direction). The inner wall 144X-IS of the second capping layer 144 may contact the sidewall of the selection device 134. In an exemplary embodiment of the inventive concept, the inner wall 144X-IS of the second capping layer 144 may be substantially flat along a third direction (e.g., the Z direction). For example, the inner wall 144X-IS of the second capping layer 144 may be vertically flat. The outer wall 144X-OS of the second capping layer 144 may be aligned with the sidewall of the intermediate electrode ME.

[0074] The fourth portion 144Y included in the second capping layer 144 may consist of an outer wall 144Y-OS and an inner wall 144Y-IS extending in a second direction (e.g., the Y direction). The inner wall 144Y-IS of the second capping layer 144, which is the sidewall of the contact selection device 134, may be substantially flat along a third direction (e.g., the Z direction). The outer wall 144Y-OS of the second capping layer 144 may be aligned with the sidewall of the intermediate electrode ME.

[0075] In an exemplary embodiment of the present invention, both the first capping layer 142 and the second capping layer 144 may comprise silicon nitride or silicon oxide nitride. However, the material of each of the first capping layer 142 and the second capping layer 144 is not limited thereto. The first capping layer 142 and the second capping layer 144 may respectively surround the sidewalls of the variable resistor layer 132 and the select device 134. The first capping layer 142 and the second capping layer 144 may each serve as a passivation layer to prevent the variable resistor layer 132 and the select device 134 from being oxidized or damaged due to exposure during the manufacturing process of the memory device 100 (such as during the etching of the underlying layer or the formation of the insulating layer).

[0076] Multiple first insulating patterns 150 may be respectively disposed between multiple memory cell posts 130 arranged in a row along a second direction (e.g., the Y direction). Multiple second insulating patterns 160 may be respectively disposed between multiple memory cell posts 130 arranged in a row along a first direction (e.g., the X direction).

[0077] refer to Figures 2 to 4The plurality of second insulating patterns 160 may be linear patterns spaced apart from each other in a first direction and extending along a second direction. The plurality of first insulating patterns 150 may be island-shaped patterns respectively disposed between two adjacent second insulating patterns 160 among the plurality of storage cell pillars 130. However, exemplary embodiments of the present invention are not limited thereto. In an exemplary embodiment of the present invention, the plurality of first insulating patterns 150 may be linear patterns extending along the second direction, and the plurality of second insulating patterns 160 may be island-shaped patterns spaced apart from each other along the first and second directions. In an exemplary embodiment of the present invention, the plurality of first insulating patterns 150 may be island-shaped patterns spaced apart from each other along the first and second directions, and the plurality of second insulating patterns 160 may be linear patterns extending along the first direction.

[0078] In one exemplary embodiment of the present invention, the plurality of first insulating patterns 150 and the plurality of second insulating patterns 160 may each comprise a material with a lower dielectric constant than capping layers 142 and 144. For example, each of the plurality of first insulating patterns 150 and the plurality of second insulating patterns 160 may comprise silicon oxide such as BPSG, PSG, USG, FSG, SOG, FOX, TEOS, PE-TEOS, HDP-CVD oxide, FSG, or SiOC.

[0079] refer to Figure 3 The intermediate electrode ME may have a first width W1 in a second direction (e.g., the Y direction). The second width W2 of the variable resistor layer 132 in the second direction may be smaller than the first width W1 of the intermediate electrode ME. The third width W3 of the selection device 134 in the second direction may be smaller than the first width W1 of the intermediate electrode ME. The first width W1 of the intermediate electrode ME may range from approximately 10 nm to approximately 200 nm, but exemplary embodiments of the present invention are not limited thereto. The second width W2 of the variable resistor layer 132 and the third width W3 of the selection device 134 may range from approximately 5 nm to approximately 180 nm, but exemplary embodiments of the present invention are not limited thereto. The first width W1 of the intermediate electrode ME, the second width W2 of the variable resistor layer 132 and the third width W3 of the selection device 134 and / or the thickness of the intermediate electrode ME, the variable resistor layer 132 and the selection device 134 may be selected based on the integration density of the memory device 100, the resolution limitations of the photolithography process and the threshold voltage of the selection device 134.

[0080] In one exemplary embodiment of the present invention, the first capping layer 142 may have a fourth width W4 in a second direction (e.g., the Y direction), and the second capping layer 144 may have a fifth width W5 in the second direction equal to the fourth width W4. For example, the fourth width W4 and the fifth width W5 may range from approximately 2 nm to approximately 50 nm. However, the exemplary embodiment of the present invention is not limited thereto. In one exemplary embodiment of the present invention, the fourth width W4 of the first capping layer 142 may be different from the fifth width W5 of the second capping layer 144.

[0081] Typically, in the processes of forming the plurality of memory cell pillars 130 (e.g., etching the plurality of memory cell pillars 130, etching word lines 110 or bit lines 120, or forming the plurality of insulating patterns 150 and 160), damage such as oxidation can occur in the variable resistance layer 132, which includes a phase material layer, and the select device 134, which includes a material having OTS characteristics, when exposed to the atmosphere (e.g., air). A passivation layer including silicon nitride can surround the sidewalls of each of the plurality of memory cell pillars 130, thus reducing or eliminating damage such as oxidation. However, in memory devices including cross-point structures, as the width of each memory cell pillar 130 decreases, the spacing between the memory cell pillars 130 can also decrease. In this case, the passivation layer can adequately fill the spacing between the memory cell pillars 130. However, due to the passivation layer typically having a high dielectric constant, a considerable RC delay can occur in the driven memory device.

[0082] However, in a memory device 100 according to an exemplary embodiment of the present invention, capping layers 142 and 144, having a relatively thin thickness, can be disposed on only the sidewalls of the variable resistor layer 132 and the select device 134, and the plurality of insulating patterns 150 and 160 can be disposed between the memory cell pillars 130. The plurality of insulating patterns 150 and 160 may comprise a material having a dielectric constant lower than that of each capping layer 142 and 144. Therefore, the RC delay occurring during driving the memory device 100 can be reduced or eliminated, thus enabling the memory device 100 to operate at high speed.

[0083] In a storage device 100 according to an exemplary embodiment of the present invention, because cover layers 142 and 144, having a relatively thin thickness, are disposed only on the sidewalls of the variable resistor layer 132 and the selector 134, damage to the variable resistor layer 132 and the selector 134 during the manufacturing process of the storage device 100 can be reduced or prevented. Therefore, the reliability of the storage device 100 can be improved.

[0084] In a memory device 100 according to an exemplary embodiment of the present invention, a selector 134 having OTS characteristics can be used. The OTS device may comprise a chalcogenide compound having an amorphous state in both an on and off state. For example, the OTS device can be repeatedly switched between an off state corresponding to relatively high resistance and an on state corresponding to relatively low resistance by applying a voltage or current without any phase change of the chalcogenide compound. Therefore, the OTS device can have relatively high durability (e.g., relatively high cycle characteristics and reliability). Even when the integration density of the memory device 100 is relatively high, such as when the size of the memory device 100 is reduced, the selector 134 in each memory cell pillar 130 can have a uniform threshold voltage distribution. Reference will be made below. Figure 5 The switching operation of the OTS device is described in more detail.

[0085] Figure 5 This is a schematic diagram showing the voltage-current curve 60 of an OTS device with OTS characteristics. Figure 5 The diagram schematically shows the current flowing in an OTS device based on the voltage applied across its two ends.

[0086] refer to Figure 5 The first curve 61 represents the voltage-current relationship in the state where no current flows in the OTS device. The OTS device can be used as a threshold voltage V at a first voltage level 63. T A switching device. When the voltage is gradually increased from a state where both voltage and current are 0, almost no current flows in the OTS device until the voltage reaches the threshold voltage V. T (For example, the first voltage level is 63). However, the voltage exceeds the threshold voltage V. T The current flowing in the OTS device will increase dramatically, and the voltage applied to the OTS device can be reduced to a second voltage level 64 (e.g., the saturation voltage V). S ).

[0087] The second curve 62 represents the voltage-current relationship when current flows through the OTS device. Because the current flowing through the OTS device has a higher level than the first current level 66, the voltage applied to the OTS device can be slightly increased further than the second voltage level 64. For example, when the current flowing through the OTS device increases from the first current level 66 to the second current level 67, the voltage applied to the OTS device can be slightly increased from the second voltage level 64. For example, once the current flows through the OTS device, the voltage applied to the OTS device can be maintained essentially at the saturation voltage V. S(For example, a second voltage level 64). For example, when the current decreases to less than the holding current level (for example, a first current level 66), the OTS device can become a resistive state and can effectively block the current until the voltage increases to the threshold voltage V. T .

[0088] Figure 6 This is a cross-sectional view illustrating a storage device according to an exemplary embodiment of the concept of the present invention. (Reference) Figure 6 The same reference number can represent a reference. Figures 1 to 5 The same parts are described, so repeated descriptions can be omitted.

[0089] Figure 6 Showing along Figure 2 The cross-sectional view corresponding to the cross-sectional view taken by line X1-X1'. Except for the shape of each of the first capping layer 142A and the second capping layer 144A, refer to... Figure 6 The described storage device 100A can be compared with the reference. Figures 2 to 4 The described storage device 100 is essentially the same.

[0090] refer to Figure 6 Each of the multiple memory cell pillars 130A may include a variable resistor layer 132A and a selection device 134A. The variable resistor layer 132A includes a recessed portion 132R disposed in the sidewall of the variable resistor layer 132A, and the selection device 134A includes a recessed portion 134R disposed in the sidewall of the selection device 134A.

[0091] The sidewalls of the variable resistor layer 132A may include recessed portions 132R that are recessed inwards. Therefore, the second width W2 of the variable resistor layer 132A may gradually decrease in the direction from the upper side to the center portion, and gradually increase in the direction from the center portion to the lower side. (Reference) Figure 6 The tail can extend outward and can be formed in the uppermost sidewall of the variable resistance layer 132A. The tail can also be formed in the lowermost sidewall of the variable resistance layer 132A.

[0092] The sidewall of the selector 134A may include a recessed portion 134R that is recessed inwards. Therefore, the third width W3 of the selector 134A may gradually decrease in the direction from the upper side to the center portion and gradually increase in the direction from the center portion to the lower side. (Reference) Figure 6The tail portion can extend outward and can be formed in the uppermost sidewall of the selector 134A. The tail portion can be formed in the lowermost sidewall of the selector 134A. The first capping layer 142A can surround the recessed portion 132R of the variable resistor layer 132A. The outer wall 142A-OS of the first capping layer 142A can be aligned with the sidewall of the intermediate electrode ME and can be substantially flat in the vertical direction (e.g., the Z direction). Alternatively, the outer wall 142A-OS of the first capping layer 142A can be inclined at an angle about the vertical direction. The inner wall 142A-IS of the first capping layer 142A can be a rounded sidewall that contacts the recessed portion 132R of the variable resistor layer 132A and protrudes in the direction toward the variable resistor layer 132A.

[0093] The second capping layer 144A may surround the recessed portion 134R of the selector 134A. The outer wall 144A-OS of the second capping layer 144A may be aligned with the sidewall of the intermediate electrode ME and may be substantially flat in the vertical direction (e.g., the Z direction). Alternatively, the outer wall 144A-OS of the second capping layer 144A may be inclined at an angle about the vertical direction. The inner wall 142A-IS of the second capping layer 144A may be a rounded sidewall that contacts the recessed portion 134R of the selector 134A and protrudes in the direction toward the selector 134A.

[0094] In an exemplary embodiment of the present invention, the recessed portion 132R of the variable resistor layer 132A and the recessed portion 134R of the selector 134A can be formed by an isotropic etching process for the variable resistor layer 132A and the selector 134A. The first capping layer 142A and the second capping layer 144A can fill a portion of the variable resistor layer 132A and a portion of the selector 134A removed by the isotropic etching process. Therefore, the first capping layer 142A and the second capping layer 144A can respectively fill the rounded inner wall 142A-IS and the rounded inner wall 144A-IS.

[0095] The exemplary contours of the recessed portion 132R of the variable resistor layer 132A and the contours of the recessed portion 134R of the selection device 134A are shown in the figure. Figure 6 As shown in the figure. However, exemplary embodiments of the inventive concept are not limited thereto. The outlines of the recessed portion 132R of the variable resistance layer 132A and the recessed portion 134R of the selector 134A can be varied based on the materials of the variable resistance layer 132A and the selector 134A, the heights of the variable resistance layer 132A and the selector 134A, and the etching formulation applied to the isotropic etching process for the variable resistance layer 132A and the selector 134A.

[0096] According to an exemplary embodiment of the present invention, when a first isotropic etching process for the variable resistance layer 132A and a second isotropic etching process for the selection device 134A are performed respectively, the outline of the recessed portion 132R of the variable resistance layer 132A may differ from the outline of the recessed portion 134R of the selection device 134A. For example, when the etching rate of the first isotropic etching process differs from the etching rate of the second isotropic etching process, for example, the sidewall of the variable resistance layer 132A may include a generally vertically flat recessed portion 132R, and the tilt angle of the recessed portion 134R of the selection device 134A may be greater than that of the second isotropic etching process. Figure 6 The large shown in the figure. According to an exemplary embodiment of the present invention, even when the isotropic etching process for the variable resistor layer 132A and the isotropic etching process for the selection device 134A are performed substantially simultaneously, the outline of the recessed portion 132R of the variable resistor layer 132A may differ from the outline of the recessed portion 134R of the selection device 134A based on the material and / or height difference between the variable resistor layer 132A and the selection device 134A.

[0097] Figure 7 This is a cross-sectional view illustrating a storage device according to an exemplary embodiment of the concept of the present invention. (Reference) Figure 7 The same reference number can represent a reference. Figures 1 to 6 The same parts are described, therefore, repeated descriptions can be omitted.

[0098] Figure 7 Showing along Figure 2 The cross-sectional view corresponding to the cross-sectional view taken by line X1-X1'. Except for the shape of each of the first capping layer 142B and the second capping layer 144B, refer to... Figure 7 The described storage device 100B can be compared with the reference. Figures 2 to 4 The described storage device 100 is essentially the same.

[0099] refer to Figure 7 Each of the plurality of memory cell pillars 130B may include a variable resistor layer 132B having a second width W2B in a second direction (e.g., the Y direction) and a selection device 134B having a third width W3B different from the second width W2B. A first capping layer 142B contacting the variable resistor layer 132B may have a fourth width W4B in the second direction (e.g., the Y direction) different from a second capping layer 144B contacting the selection device 134B having a fifth width W5B in the second direction.

[0100] For example, the second width W2B of the variable resistor layer 132B can be smaller than the third width W3B of the selection device 134B. When the second width W2B of the variable resistor layer 132B is smaller than the third width W3B of the selection device 134B, the heat collection effect can increase, and therefore, the reset current of the storage device 100B can be reduced (e.g., or the "reset" operation can be performed with a relatively low reset current). When the second width W2B of the variable resistor layer 132B is relatively small, thermal crosstalk (e.g., thermal interference) can be reduced or prevented, in which heat generated during a "write" operation for any variable resistor layer 132B and affecting adjacent variable resistor layers 132B.

[0101] However, exemplary embodiments of the present invention are not limited thereto, and the second width W2B of the variable resistor layer 132B may be greater than the third width W3B of the selection device 134B.

[0102] Figure 8 This is a cross-sectional view illustrating a storage device according to an exemplary embodiment of the concept of the present invention. Figure 8 Showing along Figure 2 The cross-sectional view corresponding to the cross-sectional view intercepted by line X1-X1'.

[0103] refer to Figure 8 In a memory device 100C according to an exemplary embodiment of the present invention, each of the plurality of memory cell pillars 130C may include an insulation liner 146 disposed between a variable resistance layer 132C and a first capping layer 142. The insulation liner 146 may extend to the bottom of the first capping layer 142 and the bottom of the top electrode TE, and may also extend to the top of the first capping layer 142 and the top of the intermediate electrode ME. The insulation liner 146 does not need to be disposed between the selection device 134C and the second capping layer 144.

[0104] In one exemplary embodiment of the present invention, the insulating liner 146 may comprise silicon oxide or silicon nitride and may have a sixth width W6C ranging from about 1 nm to about 20 nm. However, exemplary embodiments of the present invention are not limited thereto.

[0105] In the process of forming the plurality of memory cell pillars 130C according to an exemplary embodiment of the present invention, an insulating liner 146 having a predetermined thickness can first be formed on the sidewall of the variable resistance layer 132C. Then, the first and second capping layers 142 and 144 can be formed substantially simultaneously on the insulating liner 146 and the select device 134C. The fourth width W4C of the first capping layer 142 can be substantially the same as the fifth width W5C of the second capping layer 144. In this case, by adjusting the sixth width W6C of the insulating liner 146, the second width W2C of the variable resistance layer 132C can be formed to be smaller than the third width W3C of the select device 134C. Therefore, the heat collection effect in the plurality of memory cell pillars 130C can be increased, and thus, the reset current of the memory device 100C can be reduced.

[0106] However, the exemplary embodiments of the present invention are not limited thereto. In one exemplary embodiment of the present invention, a first cover layer 142 may be formed on the insulating liner 146 first, and then a second cover layer 144 may be formed on the selection device 134C.

[0107] In one exemplary embodiment of the present invention, the thermal insulation layer 146 may be formed on only the sidewalls of the variable resistance layer 132C. In another exemplary embodiment of the present invention, when the variable resistance layer 132C is disposed below the selection device 134C, the thermal insulation layer 146 may be formed on only the sidewalls of the selection device 134C. In another exemplary embodiment of the present invention, the variable resistance layer 132C may be disposed on the selection device 134C, and the thermal insulation layer 146 may be formed on only the sidewalls of the selection device 134C. The thermal insulation layer 146 may be formed on all sidewalls of both the variable resistance layer 132C and the selection device 134C.

[0108] Figure 9 This is a cross-sectional view illustrating a storage device according to an exemplary embodiment of the concept of the present invention. Figure 9 Showing along Figure 2 The cross-sectional view corresponding to the cross-sectional view intercepted by line X1-X1'.

[0109] refer to Figure 9 In a storage device 100D according to an exemplary embodiment of the present invention, air spacers AS can be formed in a plurality of first insulating patterns 150A. Air spacers AS can also be formed in a plurality of second insulating patterns 160 (see, for example, in...). Figure 2 The second insulating pattern 160 shown in the figure.

[0110] In one exemplary embodiment of the present invention, the plurality of first insulating patterns 150A may include an insulating material such as silicon oxide. For example, in the process of forming the plurality of first insulating patterns 150A, the insulating material may not adequately fill the space between the memory cell pillars 130, and thus air spacers AS may be formed in the insulating material.

[0111] In one exemplary embodiment of the present invention, the plurality of first insulating patterns 150A may have a relatively thin thickness and may conformally cover the sidewalls of each memory cell post 130. A sacrificial layer filling the space between the memory cell posts 130 may be formed on the plurality of first insulating patterns 150A, and then air spacers AS may be formed in the plurality of first insulating patterns 150A by selectively removing the sacrificial layer via an ashing process and / or a stripping process.

[0112] The air spacer AS can have a lower dielectric constant than the first and second capping layers 142 and 144. Therefore, the RC delay that may occur during the operation of the memory device 100D can be reduced, so the memory device 100D can operate at a relatively high speed.

[0113] Figure 10 This is a perspective view illustrating an exemplary embodiment of a storage device according to a concept of the present invention. Figure 11 It is along Figure 10 The cross-sectional view taken by lines X1-X1' and Y1-Y1'. Figure 12 This is an equivalent circuit diagram of a storage device according to an exemplary embodiment of the present invention.

[0114] refer to Figures 10 to 12 The storage device 200 may include bottom word lines 110 (e.g., word lines WL11 and WL12) that can extend along a first direction (e.g., the X direction) and along the first direction (e.g., the X direction). Figure 10 The memory device 200 may include a top word line 210 (e.g., word lines WL21 and WL22) that extends along a second direction (e.g., the Y direction) and is spaced apart from the bottom word line 110 in a third direction perpendicular to the first direction (e.g., the Z direction).

[0115] The first memory cell 130 (MC1) can be disposed between the common bit line 120 and the bottom word line 110. The second memory cell 230 (MC2) can be disposed between the common bit line 120 and the top word line 210. The select device SW and the variable resistor layer ME can be connected in series with each other in the first memory cell 130 (MC1) and the second memory cell 230 (MC2).

[0116] refer to Figure 11 Multiple insulating patterns 260 can be respectively disposed between the first storage unit 130 and the second storage unit 230.

[0117] The first storage cell 130 (MC1) and the second storage cell 230 (MC2) may have the same characteristics as the above reference. Figures 2 to 4 The characteristics of the described storage cell column 130 are similar.

[0118] The first memory cell 130 may include a first bottom electrode BE1, a first select device 134, a first intermediate electrode ME1, a first variable resistor layer 132, and a first top electrode TE1, sequentially disposed at the intersection between a common bit line 120 and a bottom word line 110. A first capping layer 142, including a first portion 142X and a second portion 142Y, may be formed on the sidewall of the first variable resistor layer 132, and a second capping layer 144, including a third portion 144X and a fourth portion 144Y, may be formed on the sidewall of the first select device 134. In an exemplary embodiment of the present invention, the positions of the first select device 134 and the first variable resistor layer 132 may be reversed in the first memory cell 130.

[0119] The second memory cell 230 may include a second bottom electrode BE2, a second select device 234, a second intermediate electrode ME2, a second variable resistor layer 232, and a second top electrode TE2, sequentially disposed at the intersection between the common bit line 120 and the top word line 210. A third capping layer 242, including capping layers 242X and 242Y, may be formed on the sidewall of the second variable resistor layer 232, and a fourth capping layer 244, including capping layers 244X and 244Y, may be formed on the sidewall of the second select device 234. In an exemplary embodiment of the present invention, the positions of the second select device 234 and the second variable resistor layer 232 may be reversed in the second memory cell 230.

[0120] refer to Figures 10 to 12According to an exemplary embodiment of the present invention, the storage device 200 may have a cross-point array structure in which the first storage cell 130 and the second storage cell 230 are respectively stacked below and above the common bit line 120. However, the exemplary embodiment of the present invention is not limited thereto. According to an exemplary embodiment of the present invention, the storage device 200 may have a structure in which the first storage cell 130 and the second storage cell 230 are respectively stacked below and above the common word line.

[0121] According to an exemplary embodiment of the present invention, an insulating layer may be formed on the top word line 210, and a stacked structure including a bottom word line 110, a common bit line 120, a top word line 210, a first memory cell 130, and a second memory cell 230 may be formed on the insulating layer. For example, two or more stacked structures may be disposed in a third direction (e.g., the Z direction), with the insulating layer disposed between the two or more stacked structures.

[0122] Figure 13 This is a perspective view illustrating an exemplary embodiment of a storage device according to a concept of the present invention. Figure 14 It is along Figure 13 The cross-sectional view taken by line X1-X1'.

[0123] refer to Figure 13 and 14 The storage device 300 may include a first horizontal driving circuit region 310 above the substrate 102 and a second horizontal storage cell array region MCA above the substrate 102.

[0124] The term "horizontal" refers to the height in the vertical direction (e.g., the Z direction) from the substrate 102. A first horizontal level above the substrate 102 may be closer to the substrate 102 than a second horizontal level above the substrate 102.

[0125] The drive circuit region 310 may include an area where peripheral circuitry or drive circuitry for driving memory cells in the memory cell array region MCA is disposed. For example, the peripheral circuitry disposed in the drive circuit region 310 may be circuitry for processing data input to / output to the memory cell array region MCA at a relatively high speed. For example, the peripheral circuitry may be a page buffer, latch circuitry, cache circuitry, column decoder, sense amplifier, data input / output circuitry, and / or row decoder.

[0126] An active region AC for the drive circuit can be defined in the substrate 102 by an isolation layer 104. A plurality of transistors TR configuring the drive circuit region 310 can be formed in the active region AC of the substrate 102. Each of the plurality of transistors TR may include a gate G, a gate insulating layer GD, and a source / drain region SD. The sidewalls of the gate G may be covered by an insulating spacer 106, and an etch stop 108 may be formed on the gate G and the insulating spacer 106. The etch stop 108 may comprise an insulating material such as silicon nitride or silicon oxide nitride.

[0127] Multiple insulating layers 312A, 312B, and 312C may be sequentially stacked on the etch stop 108. Each of the multiple insulating layers 312A, 312B, and 312C may comprise silicon oxide, silicon oxide nitride, and / or silicon nitride.

[0128] The driving circuit region 310 may include a multilayer wiring structure 314 electrically connected to the plurality of transistors TR. The multilayer wiring structure 314 may be insulated from the plurality of insulating layers 312A, 312B and 312C.

[0129] The multilayer wiring structure 314 may include a first contact 316A, a first wiring layer 318A, a second contact 316B, and a second wiring layer 318B sequentially stacked on the substrate 102 and electrically connected to each other. In an exemplary embodiment of the present invention, the first wiring layer 318A and the second wiring layer 318B may each include a metal, a conductive metal nitride, a metal silicide, or a combination thereof. For example, the first wiring layer 318A and the second wiring layer 318B may each include a conductive material such as tungsten (W), molybdenum (Mo), titanium (Ti), cobalt (Co), tantalum (Ta), nickel (Ni), tungsten silicide, titanium silicide, cobalt silicide, or nickel silicide.

[0130] refer to Figure 14 According to an exemplary embodiment of the present invention, the multilayer wiring structure 314 may have a two-layer wiring structure including a first wiring layer 318A and a second wiring layer 318B, but the exemplary embodiment of the present invention is not limited thereto. For example, based on the layout of the driving circuit region 310 and the type and arrangement of the gate G, the multilayer wiring structure may have a multilayer wiring structure including three or more layers.

[0131] A top insulating layer 320 may be formed on the plurality of insulating layers 312A to 312C. A memory cell array region (MCA) may be disposed on the top insulating layer 320. (See above reference) Figures 1 to 12 Storage devices 100, 100A, 100B, 100C, 100D, or 200, or combinations thereof, described in more detail, can be located in the memory cell array region MCA.

[0132] The wiring structure connecting the memory cell array region MCA and the drive circuit region 310 can pass through the top insulating interlayer 320.

[0133] In a storage device 300 according to an exemplary embodiment of the present invention, the integration density of the storage device 300 can be improved because the storage cell array region MCA can be disposed on the drive circuit region 310.

[0134] Figures 15A to 15O This is a cross-sectional view illustrating a method for manufacturing a storage device according to an exemplary embodiment of the concept of the present invention.

[0135] The following will refer to Figures 15A to 15O The method of manufacturing the storage device 100 is described in more detail below. The following description, along with reference to 15A to 15O, will be even more detailed. Figure 2 The cross-sectional view corresponding to the cross-section diagram intercepted by line X1-X1' and along the Figure 2 The cross-sectional view corresponding to the cross section intercepted by line Y1-Y1'. (Reference) Figures 15A to 15O The same reference number can represent a reference. Figures 1 to 14 The same parts are described, therefore, repeated descriptions can be omitted.

[0136] refer to Figure 15A An insulating interlayer 105 can be formed on a substrate 102, and a first conductive layer 110P can be formed on the insulating interlayer 105. In order to form a crosspoint array, a stacked structure CPS in which a primary bottom electrode layer PBE, a primary select device layer 134P, a primary intermediate electrode layer PME, a primary variable resistor layer 132P, and a primary top electrode layer PTE are sequentially stacked can be formed on the first conductive layer 110P.

[0137] The first mask pattern 410 can be formed on the stacked structure CPS.

[0138] The first mask pattern 410 may include a plurality of line patterns extending in a first direction (e.g., the X direction). The first mask pattern 410 may have a single layer or a multilayer structure in which multiple layers are stacked. For example, the first mask pattern 410 may include a photoresist pattern, a silicon oxide pattern, a silicon nitride pattern, a silicon oxide nitride pattern, a polysilicon pattern, or a combination thereof, but exemplary embodiments of the present invention are not limited thereto. In an exemplary embodiment of the present invention, the first mask pattern 410 may include different materials.

[0139] refer to Figure 15BBy using the first mask pattern 410 as an etching mask, the primary top electrode PTE and the primary variable resistor layer 132P can be sequentially anisotropically etched to separate the primary top electrode layer PTE into multiple top electrode lines TEL and the primary variable resistor layer 132P into multiple variable resistor layer lines 132L.

[0140] Therefore, the plurality of top electrode lines TEL and the plurality of variable resistance layer lines 132L extending in a first direction (e.g., the X direction) can be formed, and the plurality of first gaps GX1 extending in the first direction (e.g., the X direction) can be formed between the plurality of top electrode lines TEL and between the plurality of variable resistance layer lines 132L, respectively.

[0141] Because the plurality of first gaps GX1 are formed, a portion of the top of the primary intermediate electrode layer PME can be exposed to the bottom of each first gap GX1. (See reference...) Figure 15B The portion exposed on top of the primary intermediate electrode layer PME in each first gap GX1 may be recessed, but exemplary embodiments of the present invention are not limited thereto.

[0142] refer to Figure 15C The side portions of the plurality of variable resistance layer lines 132L can be removed by a predetermined width by performing an isotropic etching process on the sidewalls of the variable resistance layer lines 132L exposed by the plurality of first gaps GX1.

[0143] An isotropic etching process can be an etching process based on etching conditions in which the etching rate is high enough to form the plurality of variable resistance layer lines 132L. For example, the primary intermediate electrode layer PME and the plurality of top electrode lines TEL can be etched in relatively small amounts in an isotropic etching process, but can be etched at an etching rate much lower than that at which the plurality of variable resistance layer lines 132L are etched.

[0144] Because the multiple variable resistance layer lines 132L are etched to a predetermined width in the isotropic etching process while the primary intermediate electrode layer PME and the multiple top electrode lines TEL are not etched, the first undercut region 132XU can be formed in the portion adjacent to each sidewall of the multiple variable resistance layer lines 132L below the multiple top electrode lines TEL.

[0145] In one exemplary embodiment of the present invention, the isotropic etching process may include a wet etching process using at least one of HBr, Cl2, or F2 as an etchant and a dry etching process. For example, the isotropic etching process may be a reactive ion etching process or a reactive radical etching process using HBr gas as an etchant. For example, the isotropic etching process may be a wet etching process using LAL solution as an etchant.

[0146] The profile of the sidewalls of each variable resistance layer line 132L can be varied based on the etching rate of the isotropic etching process and / or the material of the variable resistance layer line 132L. For example, each of the plurality of variable resistance layer lines 132L may have a vertically flat sidewall profile, or it may have a rounded sidewall profile. For example, according to an exemplary embodiment of the present invention, a memory device 100A can be fabricated when the sidewalls of the plurality of variable resistance layer lines 132L have a rounded shape and are recessed toward the interior of the plurality of variable resistance layer lines 132L.

[0147] refer to Figure 15D The first primary capping layer 142L1 can be formed on the stacked structure CPS. In the stacked structure CPS, the first primary capping layer 142L1 can be conformally formed on the sidewalls of the top electrode line TEL and the variable resistance layer line 132L exposed by the plurality of first gaps GX1, as well as on top of the primary intermediate electrode layer PME.

[0148] In an exemplary embodiment of the present invention, the first primary capping layer 142L1 may comprise silicon nitride or silicon oxide nitride. For example, the first primary capping layer 142L1 may be formed by a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or a plasma-enhanced CVD (PECVD) process. The first primary capping layer 142L1 may be formed to a thickness from approximately 2 nm to approximately 50 nm.

[0149] In one exemplary embodiment of the present invention, the first primary capping layer 142L1 may fill the first undercut region 132XU. However, exemplary embodiments of the present invention are not limited thereto.

[0150] refer to Figure 15E Multiple first capping lines 142XP can be formed on the sidewalls of variable resistance layer lines 132L by etching back the first primary capping layer 142L1 in the multiple first gaps GX1 until the top of the primary intermediate electrode layer PME is exposed.

[0151] Only the portion of the first primary capping layer 142L1 filling the first undercut region 132XU can be retained, while the portion of the first primary capping layer 142L1 disposed in each first gap GX1 is removed in the etch-back process, thus forming the plurality of first capping lines 142XP. The sidewalls of the first capping lines 142XP can contact the sidewalls of the variable resistance layer lines 132L, and the top and bottom of the first capping lines 142XP can contact the bottom of the top electrode line TEL and the top of the plurality of intermediate electrode lines MEL.

[0152] The portion of the first primary capping layer 142L1 disposed on the first mask pattern 410 can be removed by an etch-back process, and the top of the first mask pattern 410 can be exposed. The plurality of first capping lines 142XP can extend along a first direction (e.g., the X direction) on the two sidewalls of each variable resistor layer line 132L.

[0153] refer to Figure 15F By using the first mask pattern 410 as an etching mask, the primary intermediate electrode layer PME and the primary select device layer 134P can be sequentially anisotropically etched to separate the primary intermediate electrode layer PME into multiple intermediate electrode lines MEL and the primary select device layer 134P into multiple select device layer lines 134L.

[0154] Therefore, the plurality of intermediate electrode lines MEL and the plurality of select device layer lines 134L extending in a first direction (e.g., the X direction) can be formed, and the bottom portion of each first gap GX1 can extend between the plurality of intermediate electrode lines MEL and between the plurality of select device layer lines 134L.

[0155] In the anisotropic etching process forming the plurality of intermediate electrode lines MEL and the plurality of selectable device layer lines 134L, the sidewalls of the variable resistance layer line 132L can be covered by the plurality of first cap lines 142XP, thus eliminating the need to expose the sidewalls. Because the sidewalls of the variable resistance layer line 132L are not exposed to the etching atmosphere, damage to the variable resistance layer line 132L during the etching process can be reduced or prevented.

[0156] The side portion of the selected device layer line 134L can be removed by a predetermined width by performing an isotropic etching process on the sidewall of the selected device layer line 134L exposed by the plurality of first gaps GX1.

[0157] The isotropic etching process can be an etching process based on etching conditions in which the etching rate for the plurality of selectable device layer lines 134L is sufficiently high. For example, the primary bottom electrode layer PBE, the plurality of top electrode lines TEL, and the plurality of intermediate electrode lines MEL can be etched in an isotropic etching process, but can be etched at an etching rate much lower than the etching rate at which the plurality of selectable device layer lines 134L are etched.

[0158] Because the multiple selectable device layer lines 134L are etched to a predetermined width in the isotropic etching process while the primary bottom electrode layer PBE and the multiple intermediate electrode lines MEL are not etched, the second undercut region 134XU can be formed in the portion adjacent to each sidewall of the selectable device layer lines 134L below the multiple intermediate electrode lines MEL.

[0159] In the isotropic etching process, the sidewalls of the variable resistance layer line 132L can be covered by the plurality of first cover lines 142XP, so the sidewalls do not need to be exposed to the plurality of first gaps GX1. Because the sidewalls of the variable resistance layer line 132L are not exposed to the etching atmosphere, damage to the variable resistance layer line 132L during the etching process can be reduced or prevented.

[0160] The isotropic etching process used for the variable resistor layer 132L can be similar to the above reference. Figure 15C A more detailed description of the isotropic etching process.

[0161] refer to Figure 15G The second primary capping layer 144L1 can be formed on the stacked structure CPS. In the stacked structure CPS, the second primary capping layer 144L1 can be conformally formed on the sidewalls of the top electrode line TEL, the first capping line 142XP, the intermediate electrode line MEL, and the select device layer line 134L exposed by the plurality of first gaps GX1, as well as on top of the primary bottom electrode layer PBE.

[0162] In one exemplary embodiment of the present invention, the second primary capping layer 144L1 may comprise silicon nitride or silicon oxide and may be formed by a CVD process, an ALD process, or a PECVD process. The second primary capping layer 144L1 may be formed to a thickness from approximately 2 nm to approximately 50 nm. However, the exemplary embodiment of the present invention is not limited thereto.

[0163] In one exemplary embodiment of the present invention, the second primary capping layer 144L1 may fill the second undercut region 134XU. However, exemplary embodiments of the present invention are not limited thereto.

[0164] refer to Figure 15HMultiple second capping lines 144XP can be formed on the sidewall of the select device layer line 134L by etching back the second primary capping layer 144L1 in the multiple first gaps GX1 until the top of the primary bottom electrode layer PBE is exposed again.

[0165] The portion of the second primary capping layer 144L1 that fills only the second undercut region 134XU can be retained, while the portion of the second primary capping layer 144L1 disposed in each first gap GX1 is removed in the etch-back process, thus forming the plurality of second capping lines 144XP.

[0166] The portion of the second primary capping layer 144L1 disposed on the first mask pattern 410 can be removed by an etch-back process, and the top of the first mask pattern 410 can be exposed. The plurality of second capping lines 144XP can extend along a first direction (e.g., the X direction) on the sidewall of each selected device layer line 134L.

[0167] refer to Figure 15I By using the first mask pattern 410 as an etching mask, the primary bottom electrode layer PBE and the first conductive layer 110P can be sequentially anisotropically etched to separate the primary bottom electrode layer PBE into multiple bottom electrode lines BEL and the first conductive layer 110P into multiple word lines 110.

[0168] The sidewalls of the variable resistor layer line 132L can be covered by the first capping line 142XP, and the sidewalls of the selectable device layer line 134L can be covered by the second capping line 144XP. Therefore, the variable resistor layer line 132L and the selectable device layer line 134L can be prevented from being exposed to the etching atmosphere, and damage to the variable resistor layer line 132L and the selectable device layer line 134L due to such exposure can be prevented.

[0169] In the anisotropic etching process that forms the plurality of bottom electrode lines BEL and the plurality of word lines 110, a plurality of stacked lines CPL that are spaced apart from each other by the plurality of first gaps GX1 and extend in a first direction (e.g., the X direction) can be formed on the substrate 102.

[0170] Subsequently, the first mask pattern 410 can be removed.

[0171] refer to Figure 15J A first insulating layer 150P can be formed to fill each first gap GX1. For example, the first insulating layer 150P can be formed on the plurality of laminate lines CPL and the insulating interlayer 105 by filling the plurality of first gaps GX1 with an insulating material and planarizing the top of the insulating material until the top of the laminate line CPL is exposed.

[0172] In one exemplary embodiment of the present invention, the first insulating layer 150P may comprise a material with a lower dielectric constant than the first and second cover lines 142L and 144L. For example, the first insulating layer 150P may comprise silicon oxide such as BPSG, PSG, USG, FSG, SOG, FOX, TEOS, PE-TEOS, HDP-CVD oxide, FSG, SiOC, or the like. The first insulating layer 150P may comprise one or more insulating layers. However, exemplary embodiments of the present invention are not limited thereto.

[0173] In one exemplary embodiment of the present invention, an air spacer AS can be formed in the first insulating layer 150P. Thus, the storage device 100D can be manufactured.

[0174] When air spacers AS are formed in the first insulating layer 150P, the first insulating layer 150P may comprise silicon oxide. In one exemplary embodiment of the invention, because the plurality of first gaps GX1 are not adequately filled during the process of forming the first insulating layer 150P, air spacers AS can be formed in the first insulating layer 150P. In another exemplary embodiment of the invention, a first insulating layer 150P having a relatively thin thickness and conformally covering the inner walls of the first gaps GX1 can be formed, and a sacrificial layer filling the interior of the first gaps GX1 on the first insulating layer 150P can be formed. Then, air spacers AS can be formed in the first insulating layer 150P by selectively removing the sacrificial layer via an ashing process and / or a stripping process.

[0175] The second conductive layer 120P can be formed on the first insulating layer 150P and the plurality of stacked lines CPL. The second conductive layer 120P can be similar to the first conductive layer 110P.

[0176] refer to Figure 15K The second mask pattern 420 can be formed on the second conductive layer 120P. The second mask pattern 420 can include a plurality of line patterns extending in a second direction (e.g., the Y direction). The second mask pattern 420 can have a single-layer structure or a multilayer structure in which multiple layers are stacked.

[0177] By using the second mask pattern 420 as an etching mask, the second conductive layer 120P, the plurality of top electrode lines TEL, and the plurality of variable resistance layer lines 132L can be sequentially anisotropically etched to separate the second conductive layer 120P into a plurality of bit lines 120, separate each top electrode line TEL into a plurality of top electrodes TE, and separate each variable resistance layer line 132L into a plurality of variable resistance layers 132.

[0178] Multiple second gaps GY1 extending along a second direction (e.g., the Y direction) can be formed by anisotropic processes. The multiple top electrodes TE and the multiple variable resistance layers 132 can be spaced apart from each other along the first and second directions. Each first cap line 142XP disposed on the sidewall of the variable resistance layer 132 can be separated into a first portion 142X of the first cap layer 142.

[0179] The side portions of the variable resistance layer 132 can be removed by a predetermined width by performing an isotropic etching process on the sidewalls of the variable resistance layer 132 exposed by the plurality of second gaps GY1. Therefore, the third undercut region 132YU can be formed in the portion adjacent to each sidewall of the variable resistance layer 132 below the plurality of top electrodes TE. In the isotropic etching process, it is not necessary to remove the first portion 142X of the first capping layer 142.

[0180] refer to Figure 15L The third primary capping layer can be conformally formed on the stack-up line CSL, and the third primary capping layer in each second gap GY1 is etched back until the top of the intermediate electrode line MEL is exposed, and the second portion 142Y of the first capping layer 142 can be formed on the sidewall of each variable resistor layer 132.

[0181] The second portion 142Y of the first capping layer 142 may cover the sidewalls of each variable resistance layer 132 exposed through the plurality of second gaps GY1. The second portion 142Y of the first capping layer 142, together with the first portion 142X, may surround the sidewalls of each variable resistance layer 132.

[0182] refer to Figure 15M By using the second mask pattern 420 as an etching mask, the plurality of intermediate electrode lines MEL and the plurality of select device layer lines 134L can be sequentially anisotropically etched to separate each intermediate electrode line MEL into a plurality of intermediate electrodes ME and each select device layer line 134L into a plurality of select devices 134.

[0183] The plurality of intermediate electrodes ME and the plurality of selection devices 134 may be spaced apart from each other along a first direction and a second direction. Each second cover line 144XP disposed on the sidewall of the selection device 134 may be separated into a third portion 144X of a plurality of second cover layers 144.

[0184] The sidewalls of the selector 134 can be removed by a predetermined width by performing an isotropic etching process on the sidewalls of the selector 134 exposed by the plurality of second gaps GY1. The fourth undercut region 134YU can be formed in the portion of the selector 134 adjacent to each sidewall below the plurality of intermediate electrodes ME.

[0185] refer to Figure 15N The fourth primary capping layer can be conformally formed on the stack-up line CSL, and the fourth portion 144Y of the second capping layer 144 can be formed on the sidewall of each select device 134 by etching back the fourth primary capping layer in each second gap GY1 until the top of the bottom electrode line BEL is exposed.

[0186] The fourth portion 144Y of the second cover layer 144 may cover the sidewalls of each selector 134 exposed through the plurality of second gaps GY1. The fourth portion 144Y of the second cover layer 144, together with the third portion 144X, may surround the sidewalls of each selector 134.

[0187] refer to Figure 15O By using the second mask pattern 420 as an etching mask, the plurality of bottom electrode lines BEL can be anisotropically etched to separate each bottom electrode line BEL into a plurality of bottom electrodes BE. Each stacked line CPL can be separated into a plurality of memory pillars 130 spaced apart from each other in a first direction and a second direction by an anisotropic etching process. The first insulating layer 150P can be separated into a plurality of first insulating patterns 150 spaced apart from each other in the first direction and the second direction between the plurality of memory cell pillars 130 by anisotropic etching process.

[0188] The plurality of second insulating patterns 160 filling the plurality of second gaps GY1 can be formed on the plurality of bit lines 120, the plurality of memory cell pillars 130, and the plurality of first insulating patterns 150 by filling the plurality of second gaps GY1 with insulating material and planarizing the top of the insulating material. The plurality of second insulating patterns 160 can extend along a second direction (e.g., the Y direction).

[0189] In one exemplary embodiment of the present invention, each of the plurality of second insulating patterns 160 may comprise a material with a lower dielectric constant than the first and second capping layers 142 and 144. For example, each of the plurality of second insulating patterns 160 may comprise silicon oxide such as BPSG, PSG, USG, FSG, SOG, FOX, TEOS, PE-TEOS, HDP-CVD oxide, FSG, or SiOC.

[0190] According to an exemplary embodiment of the present invention, in the process of forming the plurality of memory cell pillars 130 (e.g., etching the plurality of memory cell pillars 130, etching word lines 110 or bit lines 120, or forming the plurality of insulating patterns 150 and 160), for example, when the variable resistance layer 132, including a phase change material layer, and the select device 134, including a material having OTS characteristics, are exposed to the process atmosphere (e.g., air), the variable resistance layer 132 and the select device 134 may be damaged. A passivation layer including silicon nitride can surround the sidewalls of each of the plurality of memory cell pillars 130, thus reducing or preventing damage to the cell pillars 130. However, in memory devices including cross-point structures, as the width of each memory cell pillar 130 decreases, the spacing between the memory cell pillars 130 also decreases. Consequently, the passivation layer can substantially completely fill the spacing between the memory cell pillars 130, and due to the increased parasitic capacitance of the passivation layer, which typically has a high dielectric constant, a relatively large RC delay can be caused during driving the memory device.

[0191] In a method of manufacturing a memory device 100 according to an exemplary embodiment of the present invention, capping layers 142 and 144, having relatively thin thicknesses, are disposed on only the sidewalls of the variable resistor layer 132 and the select device 134 by an isotropic etching process, and the plurality of insulating patterns 150 and 160 can be disposed between the memory cell pillars 130. The plurality of insulating patterns 150 and 160 may comprise a material having a dielectric constant lower than that of each capping layer 142 and 144. Therefore, RC delays that may occur during driving the memory device 100 can be reduced or eliminated, thereby enabling the memory device 100 to operate at a relatively high speed.

[0192] In a method of manufacturing a memory device 100 according to an exemplary embodiment of the present invention, because the first and second cover layers 142 and 144 can be disposed on only the sidewalls of the variable resistance layer 132 and the selector 134, exposure or damage to the variable resistance layer 132 and the selector 134 can be prevented during the underlying process or the process of manufacturing multiple insulating patterns 150 and 160. Therefore, the memory device 100 manufactured by this method can have improved reliability.

[0193] Figures 16A to 16G This is a cross-sectional view illustrating a method for manufacturing a storage device according to an exemplary embodiment of the concept of the present invention. (Reference) Figures 16A to 16G The same reference number can represent a reference. Figures 15A to 15O The same parts are described, so repeated descriptions can be omitted.

[0194] refer to Figure 16AThe first mask pattern 410 can be formed on the stacked structure CPS. The stacked structure CPS can be anisotropically etched using the first mask pattern 410 as an etch mask, thereby separating the primary top electrode layer PTE, the primary variable resistor layer 132P, the primary intermediate electrode layer PME, and the primary select device layer 134P into multiple top electrode lines TEL, multiple variable resistor layer lines 132L, multiple intermediate electrode lines MEL, and multiple select device layer lines 134L, respectively.

[0195] Therefore, the plurality of first gaps GX1A extending in the first direction (e.g., the X direction) can be formed between the plurality of top electrode lines TEL, the plurality of variable resistor layer lines 132L, the plurality of intermediate electrode lines MEL, and the plurality of select device layer lines 134L extending in the first direction (e.g., the X direction).

[0196] refer to Figure 16B The side portions of the variable resistance layer line 132L and the side portions of the selectable device layer line 134L can be removed by a predetermined width by performing an isotropic etching process on the sidewalls of the variable resistance layer line 132L exposed through the plurality of first gaps GX1A and the sidewalls of the selectable device layer line 134L exposed through the plurality of first gaps GX1A.

[0197] In the isotropic etching process, the plurality of variable resistor layer lines 132L and the plurality of select device layer lines 134L can be etched to a predetermined width while the plurality of top electrode lines TEL and the plurality of intermediate electrode lines MEL are not etched. Therefore, a first undercut region 132XU can be formed in the portion adjacent to each sidewall of the variable resistor layer lines 132L below the plurality of top electrode lines TEL, and a second undercut region 134XU can be formed in the portion adjacent to each sidewall of the select device layer lines 134L below the plurality of intermediate electrode lines MEL.

[0198] Based on the isotropic etching process conditions and / or materials of each variable resistor layer line 132L and the selected device layer line 134L, the width of the first undercut region 132XU and the width of the second undercut region 134XU can be changed.

[0199] In an exemplary embodiment of the present invention, in an isotropic etching process, the etching rate at which the plurality of variable resistance layer lines 132L are etched can be similar to the etching rate at which the plurality of select device layer lines 134L are etched. For example, when both the plurality of variable resistance layer lines 132L and the plurality of select device layer lines 134L comprise chalcogenide materials, the plurality of variable resistance layer lines 132L and the plurality of select device layer lines 134L can be etched at similar etching rates in the isotropic etching process. In the isotropic etching process, the amount of side portions of the variable resistance layer lines 132L removed can be similar to the amount of side portions of the select device layer lines 134L removed, and the width of the first undercut region 132XU can be similar to the width of the second undercut region 134XU. Thus, the memory device 100 can be manufactured.

[0200] In an exemplary embodiment of the present invention, the isotropic etching process can use etching conditions where the etching rate of the plurality of variable resistor layer lines 132L being etched can differ from the etching rate of the plurality of select device layer lines 134L being etched. Therefore, the width of the first undercut region 132XU can differ from the width of the second undercut region 134XU. Consequently, the memory device 100B can be manufactured.

[0201] refer to Figure 16C The fifth primary capping layer 140L1 can be conformally formed on the plurality of top electrode lines TEL, the plurality of variable resistor layer lines 132L, the plurality of intermediate electrode lines MEL, the plurality of select device layer lines 134L, and the primary bottom electrode layer PBE. The fifth primary capping layer 140L1 can fill the first undercut region 132XU and the second undercut region 134XU.

[0202] refer to Figure 16D By etching back the fifth primary capping layer 140L1 in each first gap GX1A until the top of the primary bottom electrode layer PBE is exposed, multiple first capping lines 142XP can be formed on the sidewall of the variable resistance layer line 132L, and multiple second capping lines 144XP can be formed on the sidewall of the select device layer line 134L.

[0203] When the width of the first undercut region 132XU is substantially the same as the width of the second undercut region 134XU, the fourth width W4 of each first cover line 142XP can be substantially the same as the fifth width W5 of each second cover line 144XP. However, exemplary embodiments of the present invention are not limited thereto. In an exemplary embodiment of the present invention, the fourth width W4 of each first cover line 142XP can be different from the fifth width W5 of each second cover line 144XP.

[0204] Then, the above reference can be executed. Figure 15I and 15J The described process.

[0205] refer to Figure 16E A second mask pattern 420, including multiple line patterns extending parallel to a second direction (e.g., the Y direction), can be formed on the second conductive layer 120P.

[0206] Can be executed in accordance with the above references Figures 16A to 16D The process described is similar to that described above. Multiple second gaps GY1A can be formed by anisotropic etching of the stacked lines CSL, and an isotropic etching process can be performed to remove side portions of multiple variable resistor layers 132 and side portions of multiple select devices 134. Thus, multiple bit lines 120 can be formed.

[0207] refer to Figure 16F The sixth primary capping layer 140L2 can be conformally formed on the top and sidewalls of each of the multiple stacked lines CPL, and can fill the third undercut region 132YU and the fourth undercut region 134YU.

[0208] refer to Figure 16G The sixth primary capping layer 140L2 in the second gap GY1A can be etched back until the top of the bottom electrode layer BEL is exposed. A plurality of first capping layers 142 can be formed on the sidewalls of the variable resistor layer 132, and a plurality of second capping layers 144 can be formed on the sidewalls of the select device 134.

[0209] Then, the above reference can be executed. Figure 15O The described process.

[0210] In a method for manufacturing a memory device 100 according to an exemplary embodiment of the present invention, a significant amount of time can be reduced in performing the etching process and the process of forming capping layers 142 and 144. Therefore, the memory device 100 including capping layers 142 and 144 can be manufactured by a simpler process.

[0211] Figures 17A to 17D This is a cross-sectional view illustrating a method for manufacturing a storage device according to an exemplary embodiment of the concept of the present invention. (Reference) Figures 17A to 17D The same reference number can represent a reference. Figures 1 to 16G The same parts are described, so repeated descriptions can be omitted.

[0212] First, you can follow the above reference. Figures 15A to 15C The described process.

[0213] refer to Figure 17AThe thermal insulation liner 146 may be conformally formed on the inner wall of each of the plurality of first gaps GX1B. The thermal insulation liner 146 may be conformally formed on the bottom of each of the plurality of top electrode lines TEL and on the sidewall of each of the plurality of variable resistance layer lines 132L in the first undercut region 132XU. The thermal insulation liner 146 may comprise silicon oxide nitride or silicon nitride and may be formed via CVD, ALD or PECVD processes to have a thickness from approximately 2 nm to approximately 50 nm.

[0214] refer to Figure 17B The top of the primary bottom electrode layer (PBE) can be achieved by performing anisotropic etching and the above reference. Figure 15F The isotropic etching process described is exposed.

[0215] According to an exemplary embodiment of the present invention, in the etching process, the portion of the thermal insulation liner 146 disposed on the top of the first mask pattern 410 and the top of the primary intermediate electrode layer PME can be removed, while the portion of the thermal insulation liner 146 disposed on the sidewall of each top electrode line TEL and in the first undercut region 132XU can be retained. However, the exemplary embodiment of the present invention is not limited thereto.

[0216] The seventh primary capping layer 140L3 can be conformally formed on the inner wall of each first gap GX1B.

[0217] refer to Figure 17C By etching back the seventh primary capping layer 140L3 in each first gap GX1B until the top of the primary bottom electrode layer PBE is exposed again, multiple first capping lines 142XP can be formed on the sidewalls of the variable resistance layer line 132L, and multiple second capping lines 144XP can be formed on the sidewalls of the multiple select device layer lines 134L.

[0218] refer to Figure 17D A second mask pattern 420, including a plurality of line patterns extending along a second direction (e.g., the Y direction), can be formed on the stacked structure CPS. Subsequently, the plurality of second gaps GY1A can be formed by anisotropically etching the stacked structure CPS using the second mask pattern 420 as an etching mask.

[0219] Insulation liner 146 can be performed in accordance with the above reference. Figures 17A to 17C The described process is similar to the process described above and can be performed in accordance with the above references. Figures 16A to 16D The process described is similar to that described. Therefore, the storage device 100C can be manufactured.

[0220] While the inventive concept has been specifically shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the inventive concept.

[0221] This application claims priority to Korean Patent Application No. 10-2016-0020681, filed on February 22, 2016, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: substrate; The driving circuit area is disposed on the substrate and includes multiple peripheral circuits; Multiple word lines are disposed on the driving circuit area, including a first word line and a second word line; Multiple storage cell structures are disposed on the multiple word lines, including a first storage cell structure disposed on the first word line, a second storage cell structure disposed on the first word line, a third storage cell structure disposed on the second word line, and a fourth storage cell structure disposed on the second word line. Multiple bit lines are disposed on the multiple memory cell structures, including a first bit line disposed on the first memory cell structure and the third memory cell structure, and a second bit line disposed on the second memory cell structure and the fourth memory cell structure; as well as Multiple insulating patterns are disposed between two adjacent memory cell structures in the plurality of memory cell structures, including a first insulating pattern disposed between the first memory cell structure and the second memory cell structure, and a second insulating pattern disposed between the first memory cell structure and the third memory cell structure. The first memory cell structure includes a first electrode, a selection device disposed on the first electrode, a second electrode disposed on the selection device, a variable resistance layer disposed on the second electrode, and a third electrode disposed on the variable resistance layer. A gap is provided in at least one of the plurality of insulating patterns. The first memory cell structure includes a first capping layer disposed on the sidewall of the selection device and a second capping layer disposed on the sidewall of the variable resistor layer, wherein the first capping layer and the second capping layer are spaced apart on the same side of the first memory cell structure.

2. The semiconductor device of claim 1, wherein the width of the selection device is greater than the width of the variable resistor layer.

3. The semiconductor device according to claim 1, wherein the width of the first capping layer is smaller than the width of the second capping layer.

4. The semiconductor device of claim 1, wherein the first insulating pattern includes the voids.

5. The semiconductor device of claim 1, wherein the width of the selection device is smaller than the width of the first word line.

6. The semiconductor device of claim 1, wherein the variable resistance layer comprises a magnetic tunnel junction (MTJ) structure, the magnetic tunnel junction (MTJ) structure comprising two electrodes containing magnetic material and a dielectric disposed between the two electrodes.

7. A semiconductor device, comprising: substrate; Multiple word lines are disposed on the substrate, including a first word line and a second word line; Multiple storage cell structures are disposed on the multiple word lines, including a first storage cell structure disposed on the first word line, a second storage cell structure disposed on the first word line, a third storage cell structure disposed on the second word line, and a fourth storage cell structure disposed on the second word line. Multiple bit lines are disposed on the multiple memory cell structures, including a first bit line disposed on the first memory cell structure and the third memory cell structure, and a second bit line disposed on the second memory cell structure and the fourth memory cell structure; as well as Multiple insulating patterns are disposed between two adjacent memory cell structures in the plurality of memory cell structures, and include a first insulating pattern disposed between the first memory cell structure and the second memory cell structure. The first memory cell structure includes a first electrode, a selection device disposed on the first electrode, a second electrode disposed on the selection device, a variable resistance layer disposed on the second electrode, a third electrode disposed on the variable resistance layer, a first capping layer disposed on the sidewall of the selection device, and a second capping layer disposed on the sidewall of the variable resistance layer. The first capping layer is disposed only between the first electrode and the second electrode, and The width of the selection device is greater than the width of the variable resistor layer.

8. The semiconductor device according to claim 7 further includes a driving circuit region disposed between the substrate and the plurality of word lines and including a plurality of peripheral circuits.

9. The semiconductor device of claim 7, wherein the width of the first capping layer is smaller than the width of the second capping layer.

10. The semiconductor device of claim 7, wherein the selective device comprises at least one of Si, Te, As, Ge and In.

11. The semiconductor device of claim 7, wherein the semiconductor device is a magnetic random access memory (MRAM).

12. The semiconductor device of claim 7, wherein an air spacer is disposed in at least one of the plurality of insulating patterns.

13. The semiconductor device of claim 12, wherein the first insulating pattern includes the air spacer.

14. A semiconductor device, comprising: substrate; The driving circuit area is disposed on the substrate and includes multiple peripheral circuits; Multiple word lines are disposed on the driving circuit area, including a first word line and a second word line; Multiple storage cell structures are disposed on the multiple word lines, including a first storage cell structure disposed on the first word line, a second storage cell structure disposed on the first word line, a third storage cell structure disposed on the second word line, and a fourth storage cell structure disposed on the second word line. Multiple bit lines are disposed on the multiple memory cell structures, including a first bit line disposed on the first memory cell structure and the third memory cell structure, and a second bit line disposed on the second memory cell structure and the fourth memory cell structure; as well as Multiple insulating patterns are disposed between two adjacent memory cell structures in the plurality of memory cell structures, and include a first insulating pattern disposed between the first memory cell structure and the second memory cell structure. The first memory cell structure includes a first electrode, a selection device disposed on the first electrode, a second electrode disposed on the selection device, a variable resistance layer disposed on the second electrode, a third electrode disposed on the variable resistance layer, a first capping layer disposed on the sidewall of the selection device, and a second capping layer disposed on the sidewall of the variable resistance layer. The second capping layer is disposed only between the second electrode and the third electrode, and The width of the selection device is greater than the width of the variable resistor layer.

15. The semiconductor device of claim 14, wherein the width of the first capping layer is smaller than the width of the second capping layer.

16. The semiconductor device of claim 14, wherein the width of the first capping layer is the same as the width of the second capping layer.

17. The semiconductor device of claim 14, wherein the variable resistance layer comprises one or more elements from Group VI of the periodic table and one or more chemical modifiers from Group III, Group IV or Group V.

18. The semiconductor device of claim 14, wherein the plurality of word lines and the plurality of bit lines comprise at least one selected from tungsten (W), tungsten nitride (WN), copper (Cu), aluminum (Al), titanium aluminum nitride (TiAlN), iridium (Ir), platinum (Pt), palladium (Pd), ruthenium (Ru), zirconium (Zr), rhodium (Rh), nickel (Ni), cobalt (Co), chromium (Cr), tin (Sn), zinc (Zn), and indium tin oxide (ITO).

19. The semiconductor device of claim 14, wherein the first insulating pattern comprises air spacers.

20. A semiconductor device, comprising: substrate; The driving circuit area is disposed on the substrate; Multiple word lines extending in a first direction are disposed on the driving circuit region and include a first word line and a second word line spaced parallel to each other in a second direction perpendicular to the first direction. Multiple bit lines extending in the second direction are disposed on the word line and include a first bit line and a second bit line that are spaced apart from each other in parallel in the first direction. The memory cell array region includes a plurality of memory pillars respectively arranged at the intersections between the plurality of bit lines and the plurality of word lines, each of the plurality of memory pillars including a selection device and a variable resistor layer; Multiple insulating patterns are disposed between two adjacent storage columns among the multiple storage columns; A first capping layer is disposed on the inclined sidewall of each of the variable resistance layers; as well as A second cover layer is disposed on the inclined sidewall of each of the selected devices. In each of the plurality of storage columns, the first capping layer and the second capping layer are spaced apart on the same side, and The width of the variable resistor layer gradually decreases from the top to the middle and gradually increases from the middle to the bottom.

21. The semiconductor device according to claim 20, The maximum thickness of the first cover layer is greater than the maximum thickness of the second cover layer.

22. The semiconductor device according to claim 20, The width of the first cover layer increases from the top to the middle and gradually decreases from the middle to the bottom.

23. The semiconductor device of claim 20, further comprising: The top electrode is disposed on the variable resistance layer. The inclined sidewalls of the variable resistance layer are disposed below the top electrode.

24. The semiconductor device according to claim 20, The first capping layer surrounds the entire portion of the inclined sidewall of the variable resistance layer.

25. The semiconductor device of claim 20, further comprising: Multiple transistors on the substrate, The driving circuit region includes a multilayer wiring structure electrically connected to the plurality of transistors.

26. The semiconductor device of claim 20, further comprising: Multiple transistors on the substrate, The memory cell array region is connected to the plurality of transistors via a multi-layer wiring structure.

27. The semiconductor device of claim 20, further comprising: A top insulating interlayer is disposed on the drive circuit area; and The wiring structure passes through the top insulating interlayer and connects the memory cell array region and the drive circuit region.

28. The semiconductor device of claim 20, further comprising: Air spacers are provided in at least one of the plurality of insulating patterns.

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