Semiconductor device and method of manufacturing the same
Patent Information
- Application Number
- CN202610563955.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-04-27
- Publication Date
- 2026-09-01
AI Technical Summary
[0004]基于此，本申请提供一种半导体器件及其制备方法，用以解决金属硅化物区域的金属硅化物与多晶硅栅极距离过近引发的漏电流异常问题，以及解决非金属硅化物区域的多晶硅栅极顶部角落生长出金属硅化物的问题，提高产品性能
[0025]本申请提供的半导体器件的制备方法中，在预清洗工艺之前形成氧化硅保护层，通过氧化硅保护层保护第一侧墙结构以及自对准阻挡层，以减少第一侧墙结构在预清洗工艺和SiCoNi工艺中的消耗，以及减少自对准阻挡层在预清洗工艺和SiCoNi工艺中的消耗，从而避免金属硅化物与第一多晶硅栅极间距过小，进而避免由于间距过小导致的漏电流过高的情况，以及避免第二区的第一多晶硅栅极顶部拐角处长出金属硅化物，从而扩大工艺窗口，提升器件性能。
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Figure CN122679677A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and its fabrication method. Background Technology
[0002] In the semiconductor manufacturing process, metal and silicon are annealed at high temperatures to form metal silicides, which reduce the series resistance of the circuit. During the formation of metal silicides, a self-aligned block (SAB) layer is used to cover ESD devices (electrostatic discharge devices) and high impedance resistance areas.
[0003] However, during the formation of metal silicides, the gate sidewalls of the metal silicide region are damaged in subsequent pre-cleaning processes, which can lead to a smaller gap between the subsequently formed metal silicide and the gate polysilicon, resulting in excessive leakage current. On the other hand, the self-aligned barrier layer in the non-silicide region is also damaged during subsequent pre-cleaning processes, causing metal silicide to grow at the top corner of the polysilicon gate, resulting in abnormal leakage current. Summary of the Invention
[0004] Based on this, this application provides a semiconductor device and its fabrication method to solve the problem of abnormal leakage current caused by the close proximity of the metal silicide in the metal silicide region to the polysilicon gate, and to solve the problem of metal silicide growing at the top corner of the polysilicon gate in the non-metal silicide region, thereby improving product performance.
[0005] This application provides a method for fabricating a semiconductor device, including:
[0006] A semiconductor substrate is provided, the semiconductor substrate including a first region and a second region, a first gate structure is formed on the first region, and a second gate structure is formed on the second region, the first gate structure including a first polysilicon gate and a first sidewall structure, and the second gate structure including a second polysilicon gate and a second sidewall structure.
[0007] A self-aligned barrier layer is formed, which covers the semiconductor substrate of the second region and the top surface and sidewalls of the second gate structure;
[0008] A silicon oxide protective layer is formed, which covers the semiconductor substrate, the top surface and sidewalls of the first gate structure, and the self-aligned barrier layer is also covered by the silicon oxide protective layer;
[0009] A patternless etching process is performed, retaining the silicon oxide protective layer on the sidewall of the first gate structure and the silicon oxide protective layer on the sidewall of the second gate structure. The retained silicon oxide protective layer covers the self-aligned barrier layer on the sidewall of the first sidewall structure and the sidewall of the second sidewall structure.
[0010] A pre-cleaning process is performed, during which the silicon oxide protective layer is consumed;
[0011] A metal silicide is formed, which covers the first polysilicon gate and the semiconductor substrate on both sides of the first gate structure. The process of forming the metal silicide includes performing a SiCoNi process, during which the silicon oxide protective layer is consumed again.
[0012] Furthermore, in the semiconductor device fabrication method, the pre-cleaning process employs an acid washing process.
[0013] Furthermore, in the semiconductor device fabrication method, the etching liquid in the pickling process contains hydrofluoric acid, and the etching gas in the SiCoNi process contains NH3 and NF3.
[0014] Furthermore, in the method for fabricating a semiconductor device, the first sidewall structure includes, from the inside out, a first silicon oxide inner sidewall, a first silicon nitride inner sidewall, a first silicon oxide outer sidewall, and a first silicon nitride outer sidewall, and the second sidewall structure includes, from the inside out, a second silicon oxide inner sidewall, a second silicon nitride inner sidewall, a second silicon oxide outer sidewall, and a second silicon nitride outer sidewall.
[0015] Furthermore, in the method for fabricating a semiconductor device, the material of the self-aligned barrier layer is silicon nitride.
[0016] Furthermore, in the method for fabricating a semiconductor device, before forming the self-aligned barrier layer, an interface oxide layer is formed, wherein the interface oxide layer covers the semiconductor substrate of the second region and the top surface and sidewalls of the second gate structure, and the self-aligned barrier layer covers the interface oxide layer.
[0017] Furthermore, in the fabrication method of semiconductor devices, the process of forming a self-aligned barrier layer includes:
[0018] A self-aligned barrier layer material is formed, the self-aligned barrier layer material covering the first region and the second region;
[0019] Photolithography and etching processes are performed to remove the self-aligned barrier layer material in the first region.
[0020] Furthermore, in the fabrication method of semiconductor devices, an ALD-CVD process is used to form a silicon oxide protective layer.
[0021] Furthermore, in the method for fabricating a semiconductor device, the process of forming the metal silicide includes:
[0022] The metal material layer deposition process and the SiCoNi etching process are performed cyclically, wherein the metal material layer is a nickel-platinum alloy layer;
[0023] An annealing process is performed on the metal material layer to form the metal silicide.
[0024] This application also provides a semiconductor device, which is fabricated using any one of the semiconductor device fabrication methods described above.
[0025] In the semiconductor device fabrication method provided in this application, a silicon oxide protective layer is formed before the pre-cleaning process. The silicon oxide protective layer protects the first sidewall structure and the self-aligned barrier layer, thereby reducing the consumption of the first sidewall structure and the SiCoNi process, as well as the consumption of the self-aligned barrier layer. This avoids the metal silicide and the first polysilicon gate having an excessively small spacing, thus avoiding excessive leakage current due to the small spacing. It also prevents the growth of metal silicide at the top corner of the first polysilicon gate in the second region, thereby expanding the process window and improving device performance. Attached Figure Description
[0026] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this application or in the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0027] Figure 1 This is a schematic cross-sectional view of a semiconductor device after metal silicide formation in a related process.
[0028] Figure 2 This is a schematic diagram of the process for fabricating a semiconductor device according to an embodiment of this application;
[0029] Figure 3 A cross-sectional schematic diagram of step S11 in the method for fabricating a semiconductor device provided in the embodiments of this application;
[0030] Figures 4A to 4B A cross-sectional schematic diagram of step S12 in the method for fabricating a semiconductor device provided in the embodiments of this application;
[0031] Figure 5 A cross-sectional schematic diagram of step S13 in the method for fabricating a semiconductor device provided in the embodiments of this application;
[0032] Figure 6 A cross-sectional schematic diagram of step S14 in the method for fabricating a semiconductor device provided in the embodiments of this application;
[0033] Figure 7 This is a cross-sectional schematic diagram of step S16 in the method for fabricating a semiconductor device provided in the embodiments of this application.
[0034] Explanation of icon numbers:
[0035] exist Figure 1 In the middle, 10-semiconductor substrate, 10A-first region, 10B-second region, 11-first gate structure, 111-first polysilicon gate, 112-first sidewall, 12-second gate structure, 121-second polysilicon gate, 122-second sidewall, 13-self-aligned barrier layer, 14-metal silicide;
[0036] exist Figures 3 to 7 In the diagram, 100 is a semiconductor substrate, 101 is a first region, 102 is a second region, 210 is a first gate structure, 211 is a first polysilicon gate, 212 is a first sidewall structure, 213 is a first gate oxide layer, 220 is a second gate structure, 221 is a second polysilicon gate, 222 is a second sidewall structure, 223 is a second gate oxide layer, 300 is an interface oxide layer, 400 is a self-aligned barrier layer, 500 is a silicon oxide protective layer, and 600 is a metal silicide. Detailed Implementation
[0037] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.
[0038] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; and the term “at least two” is generally used to mean “two or more”. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature, unless otherwise expressly indicated.
[0039] Figure 1 This is a cross-sectional view of a semiconductor device after the formation of a metal silicide in the related art. The semiconductor device includes a semiconductor substrate 10, which includes a first region 10A and a second region 10B. A first gate structure 11 and a metal silicide 14 are formed on the semiconductor substrate 10 in the first region 10A. The first gate structure 11 includes a first polysilicon gate 111 and a first sidewall 112, with the first sidewall 112 located on both sides of the first polysilicon gate 111. The metal silicide 14 covers the semiconductor substrate 10 in the first region 11A and the top of the first polysilicon gate 111. A second gate structure 12 and a self-aligned barrier layer 13 are formed on the semiconductor substrate 10 in the second region 12B. The second gate structure 12 includes a second polysilicon gate 121 and a second sidewall 122. The self-aligned barrier layer 13 covers the semiconductor substrate 10 in the second region 10B and the top of the second polysilicon gate 121.
[0040] Before the formation of metal silicide 40, the semiconductor device needs to undergo a pre-cleaning process. During the pre-cleaning process, oxide residues on the surfaces of the first region 10A and the second region 10B are removed. At this time, the first sidewall 112 exposed on the first region 10A may have some losses, resulting in some depressions at the bottom corner of the first sidewall 110 (as shown by label A). The self-aligned barrier layer 13 on the second region 10B may also have some losses, resulting in the exposure of the underlying second polysilicon gate 121 (as shown by label B). As a result, during the formation of metal silicide 14, metal silicide 14 grows laterally along the surface of the semiconductor substrate 10 and stops at the position of the first sidewall. The first sidewall 112 is consumed in the pre-cleaning process, resulting in a smaller lateral spacing between the metal silicide and the first polysilicon gate 111 of 14. If the distance is too close, it can easily lead to excessive leakage current. In addition, the self-aligned barrier layer 13 will also be consumed in the pre-cleaning process, exposing the second polysilicon gate 121 at the corner of the second gate structure 12, which will then grow metal silicide 14, resulting in abnormal leakage current.
[0041] Based on this, this application provides a semiconductor device and a method for fabricating the same. The method includes forming a self-aligned barrier layer covering the semiconductor substrate of the second region and the top surface and sidewalls of the second gate structure; forming a silicon oxide protective layer covering the semiconductor substrate, the top surface and sidewalls of the first gate structure, and the silicon oxide protective layer also covering the self-aligned barrier layer; performing a patternless etching process to retain the silicon oxide protective layer on the sidewalls of the first gate structure and the second gate structure, wherein the retained silicon oxide protective layer covers the sidewalls of the first sidewall structure and the self-aligned barrier layer on the sidewalls of the second sidewall structure; performing a pre-cleaning process, wherein the silicon oxide protective layer is consumed during the pre-cleaning process; and forming a metal silicide covering the first polysilicon gate and the semiconductor substrate on both sides of the first gate structure. The process of forming the metal silicide includes performing a SiCoNi process, wherein the silicon oxide protective layer is consumed again during the SiCoNi process. In this way, a silicon oxide protective layer is formed before the pre-cleaning process. The silicon oxide protective layer protects the first sidewall structure and the self-aligned barrier layer, reducing the loss of the first sidewall structure and the SiCoNi process, as well as the loss of the self-aligned barrier layer. This avoids the metal silicide and the first polysilicon gate being too close together, thus avoiding excessive leakage current due to the small distance. It also prevents the growth of metal silicide at the top corner of the first polysilicon gate in the second region, thereby expanding the process window and improving device performance.
[0042] refer to Figure 2 , Figure 2 This is a schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application. The schematic flowchart of the method for fabricating a semiconductor device according to an embodiment of this application includes:
[0043] S11: A semiconductor substrate is provided, the semiconductor substrate includes a first region and a second region, a first gate structure is formed on the first region, a second gate structure is formed on the second region, the first gate structure includes a first polysilicon gate and a first sidewall structure, and the second gate structure includes a second polysilicon gate and a second sidewall structure.
[0044] S12: Form a self-aligned barrier layer, which covers the semiconductor substrate of the second region and the top surface and sidewalls of the second gate structure;
[0045] S13: Form a silicon oxide protective layer, which covers the semiconductor substrate, the top surface and sidewalls of the first gate structure, and also covers a self-aligned barrier layer.
[0046] S14: Perform a patternless etching process, retain the silicon oxide protective layer on the sidewall of the first gate structure and the silicon oxide protective layer on the sidewall of the second gate structure, and the retained silicon oxide protective layer covers the self-aligned barrier layer on the sidewall of the first sidewall structure and the sidewall of the second sidewall structure.
[0047] S15: Perform a pre-cleaning process, which consumes the silicon oxide protective layer.
[0048] S16: Forming a metal silicide, which covers the first polysilicon gate and the semiconductor substrate on both sides of the first gate structure. The process of forming the metal silicide includes performing a SiCoNi process, during which the silicon oxide protective layer is consumed again.
[0049] The embodiments of this application will be described in more detail below with reference to the accompanying drawings.
[0050] First, execute step S11: (e.g.) Figure 3 As shown, a semiconductor substrate 100 is provided, comprising a first region 101 and a second region 102. The first region 101 is a region for forming metal silicide. The second region 102 is a region where metal silicide formation is prohibited (non-silicide). The first region 101 and the second region 102 are separated by an STI isolation structure. The semiconductor substrate 100 can be made of any known type of substrate.
[0051] A first gate structure 210 is formed on the first region 101, and a second gate structure 220 is formed on the second region 102.
[0052] The first gate structure 210 includes a first polysilicon gate 211 and a first sidewall structure 212. As an example, the first sidewall structure 212 includes, from the inside out, a first silicon oxide inner sidewall, a first silicon nitride inner sidewall, a first silicon oxide outer sidewall, and a first silicon nitride outer sidewall. Exemplarily, the first silicon oxide inner sidewall extends to the bottom of the first silicon nitride inner sidewall between itself and the semiconductor substrate. Exemplarily, the first silicon oxide outer sidewall extends to the bottom of the first silicon nitride outer sidewall between itself and the semiconductor substrate.
[0053] The second gate structure 220 includes a second polysilicon gate 221 and a second sidewall structure 222. As an example, the second sidewall structure 220 includes, from the inside out, a second silicon oxide inner sidewall, a second silicon nitride inner sidewall, a second silicon oxide outer sidewall, and a second silicon nitride outer sidewall. Exemplarily, the second silicon oxide inner sidewall extends to the bottom of the second silicon nitride inner sidewall between itself and the semiconductor substrate. Exemplarily, the second silicon oxide outer sidewall extends to the bottom of the second silicon nitride outer sidewall between itself and the semiconductor substrate.
[0054] As an example, the process of forming the first and second silicon oxide inner sidewalls can involve first forming the silicon oxide inner sidewall material using a deposition process, and then etching the silicon oxide inner sidewall material using photolithography and etching processes to form the first and second silicon oxide inner sidewalls. The deposition process can be either PECVD (plasma-enhanced chemical vapor deposition) or LPCVD / TEOS (low-pressure chemical vapor deposition). The etching process can be a dry etching process performed using a fluorocarbon-based gas. Furthermore, the process for forming the first and second silicon oxide outer sidewalls is similar to the process for forming the first and second silicon oxide inner sidewalls.
[0055] As an example, the process of forming the first and second silicon nitride inner sidewalls can involve first forming the silicon nitride inner sidewall material using a deposition process, and then etching the silicon nitride inner sidewall material using photolithography and etching processes to form the first and second silicon nitride inner sidewalls. The deposition process can be LPCVD (low-pressure chemical vapor deposition). The etching process can be a dry etching process performed using fluorocarbon-based gases. Furthermore, the process of forming the first and second silicon nitride outer sidewalls is similar to that of forming the first and second silicon nitride inner sidewalls.
[0056] Furthermore, the first gate structure 210 also includes a first gate oxide layer 213, and a first polysilicon gate 211 covers the first gate oxide layer 213. The second gate structure 220 also includes a second gate oxide layer 223, and a second polysilicon gate 223 covers the second gate oxide layer 223. The materials of the first gate oxide layer 213 and the second gate oxide layer 223 are, for example, silicon oxide (SiO2).
[0057] Next, proceed to step S12, as follows: Figures 4A-4B As shown, a self-aligned barrier layer 400 is formed, which covers the semiconductor substrate 100 of the second region 102 and the top surface and sidewalls of the second gate structure 220.
[0058] like Figure 4A As shown, before forming the self-aligned barrier layer 400, an interface oxide layer 300 is formed. The interface oxide layer 300 covers the semiconductor substrate 100 of the second region 102 and the top surface and sidewalls of the second gate structure 220. The self-aligned barrier layer 400 covers the interface oxide layer 300. The material of the interface oxide layer 300 can be silicon oxide (SiO2). Typically, the interface oxide layer 300 can be formed first using a PECVD process, covering the surfaces of the first region 101 and the second region 102. Then, photolithography and etching processes are performed to remove the interface oxide layer 300 of the first region 101.
[0059] The material of the self-aligned barrier layer 400 can be at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon-rich oxide. Preferably, the material of the self-aligned barrier layer 400 is silicon nitride. The process of forming the self-aligned barrier layer 400 may include: forming a self-aligned barrier layer material covering the first region 101 and the second region 102; performing photolithography and etching processes to remove the self-aligned barrier layer material in the first region 101. Further, it also includes removing the interface oxide layer 300 on the first region 101. In this embodiment, the self-aligned barrier layer material can be formed using plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD). In this embodiment, the etching process for etching the self-aligned barrier layer 400 and the interface oxide layer 300 can be a dry etching process using a fluorocarbon-based gas (e.g., trifluoromethane) or a wet etching process using hydrofluoric acid.
[0060] Next, proceed to step S13, as follows: Figure 5 As shown, a silicon oxide protective layer 500 is formed, which covers the top surface and sidewalls of the semiconductor substrate 100 and the first gate structure 212. The silicon oxide protective layer 500 also covers a self-aligned barrier layer 400.
[0061] In this embodiment, a deposition process can be used to form the silicon oxide protective layer 500, such as ALD-CVD (chemical vapor deposition-atomic layer deposition) process.
[0062] The purpose of using the silicon oxide protective layer 500 in this embodiment is not only to protect the second sidewall structure 222, but also to facilitate its complete removal later. That is, if it is not completely consumed during the protection stage, it can be completely removed with hydrofluoric acid.
[0063] Next, proceed to step S14, as follows: Figure 6 As shown, a patternless etching process is performed, retaining the silicon oxide protective layer 500 on the sidewall of the first gate structure 210 and the silicon oxide protective layer 500 on the sidewall of the second gate structure 220. The retained silicon oxide protective layer 500 covers the self-aligned barrier layer 400 on the sidewall of the first sidewall structure 210 and the sidewall of the second sidewall structure 220.
[0064] Furthermore, during the patternless etching process of the silicon oxide protective layer 500, an anisotropic dry etching process is selected to etch the silicon oxide protective layer 500.
[0065] Next, step S15 is executed to perform a pre-cleaning process, during which 500g of silicon oxide protective layer will be consumed.
[0066] While cleaning the device surface through the pre-cleaning process, the silicon oxide protective layer 500 on the surface of the semiconductor substrate 100 is consumed, thereby reducing the consumption of the first sidewall structure 212 of the first region 101 and the self-aligned barrier layer 500 of the second region 102 during the pre-cleaning process.
[0067] As an example, the pre-cleaning process employs an acid pickling process. Further, the etching liquid in the acid pickling process contains hydrofluoric acid. For example, diluted hydrofluoric acid (DHF) or a cleaning solution containing hydrofluoric acid is used to wet-clean the surface of the semiconductor substrate 100 to remove etching residues from previous processes (e.g., SAB process residues) and to consume the silicon oxide protective layer 500.
[0068] Next, proceed to step S16, as follows: Figure 7 As shown, a metal silicide 600 is formed, which covers the semiconductor substrate 100 on both sides of the first polysilicon gate 211 and the first gate structure 210. The process of forming the metal silicide 600 includes performing a SiCoNi process, during which the silicon oxide protective layer is consumed again.
[0069] The SiCoNi process is a remote plasma-assisted dry etching process that involves simultaneously exposing the semiconductor substrate to plasma byproducts of hydrogen, nitrogen trifluoride, and ammonia. The remote plasma excitation of hydrogen and fluorine species allows for plasma-free semiconductor substrate processing. SiCoNi etching is largely conformal and selective for silicon oxide layers, but it does not readily etch silicon regardless of whether it is amorphous, crystalline, or polycrystalline. Solid-state byproducts generated during the removal of the semiconductor substrate material grow on the substrate surface. These byproducts are subsequently removed by sublimation when the substrate temperature is increased.
[0070] Furthermore, the etching gas in the SiCoNi process includes NH3 and NF3. For example, a fluorine- and ammonia-containing plasma is used to treat the surface of the semiconductor substrate 100 at a low temperature (e.g., 35°C). The residual silicon oxide protective layer 500 reacts to form a solid ammonium salt intermediate (e.g., ammonium hexafluorosilicate), which is then removed by sublimation (e.g., 180°C). Thus, during the implementation of the SiCoNi process, the silicon oxide protective layer 500 is consumed again, thereby reducing the consumption of the first sidewall structure 210 and the self-aligned barrier layer 400.
[0071] To further explain, a first source / drain region (not shown in the attached figure) is also formed in the semiconductor substrate on both sides of the first gate structure 210, and a metal silicide 600 is formed on top of the first source / drain region of the semiconductor substrate 100.
[0072] As an example, the process of forming metal silicide 600 includes: forming a metal material layer, the metal material layer being a nickel-platinum alloy layer; and performing an annealing process on the metal material layer to form metal silicide 600.
[0073] After forming the metal silicide 600, the process also includes removing the self-aligned barrier layer 400 and the interface oxide layer 300 on the second region 102.
[0074] This application also provides a semiconductor device, which is fabricated using the above-described semiconductor device fabrication method. The semiconductor device includes a semiconductor substrate 100, which includes a first region 101 and a second region 102. A first gate structure 210 is formed on the first region 101, and a second gate structure 220 is formed on the second region 102. The first gate structure 210 includes a first polysilicon gate 211, and metal silicides 600 are formed on the semiconductor substrate 100 on both sides of the first polysilicon gate 211 and the first gate structure 210.
[0075] In the semiconductor device and its fabrication method provided in this embodiment, a silicon oxide protective layer is formed before the pre-cleaning process. The silicon oxide protective layer protects the first sidewall structure and the self-aligned barrier layer, thereby reducing the consumption of the first sidewall structure and the SiCoNi process, and reducing the consumption of the self-aligned barrier layer in the pre-cleaning process and the SiCoNi process. This avoids the metal silicide and the first polysilicon gate having too small a spacing, thus avoiding the situation where the leakage current is too high due to the small spacing, and also avoids the growth of metal silicide at the top corner of the first polysilicon gate in the second region, thereby expanding the process window and improving device performance.
[0076] Those skilled in the art will understand that the above embodiments are specific examples of implementing this application, and in practical applications, various changes in form and detail can be made without departing from the spirit and scope of this application. Any person skilled in the art can make various alterations and modifications without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.
Claims
1. A method for fabricating a semiconductor device, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate including a first region and a second region, a first gate structure is formed on the first region, and a second gate structure is formed on the second region, the first gate structure including a first polysilicon gate and a first sidewall structure, and the second gate structure including a second polysilicon gate and a second sidewall structure. A self-aligned barrier layer is formed, which covers the semiconductor substrate of the second region and the top surface and sidewalls of the second gate structure; A silicon oxide protective layer is formed, which covers the semiconductor substrate, the top surface and sidewalls of the first gate structure, and the self-aligned barrier layer is also covered by the silicon oxide protective layer; A patternless etching process is performed, retaining the silicon oxide protective layer on the sidewall of the first gate structure and the silicon oxide protective layer on the sidewall of the second gate structure. The retained silicon oxide protective layer covers the self-aligned barrier layer on the sidewall of the first sidewall structure and the sidewall of the second sidewall structure. A pre-cleaning process is performed, during which the silicon oxide protective layer is consumed; A metal silicide is formed, which covers the first polysilicon gate and the semiconductor substrate on both sides of the first gate structure. The process of forming the metal silicide includes performing a SiCoNi process, during which the silicon oxide protective layer is consumed again.
2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The pre-cleaning process employs an acid washing process.
3. The method for fabricating a semiconductor device according to claim 2, characterized in that, The etching liquid used in the pickling process contains hydrofluoric acid.
4. The method for fabricating a semiconductor device according to claim 1, characterized in that, The first sidewall structure includes, from the inside out, a first silicon oxide inner sidewall, a first silicon nitride inner sidewall, a first silicon oxide outer sidewall, and a first silicon nitride outer sidewall. The second sidewall structure includes, from the inside out, a second silicon oxide inner sidewall, a second silicon nitride inner sidewall, a second silicon oxide outer sidewall, and a second silicon nitride outer sidewall.
5. The method for fabricating a semiconductor device according to claim 1, characterized in that, The material of the self-aligned barrier layer is silicon nitride.
6. The method for fabricating a semiconductor device according to claim 1, characterized in that, Before forming the self-aligned barrier layer, an interface oxide layer is formed, which covers the semiconductor substrate of the second region and the top surface and sidewalls of the second gate structure, and the self-aligned barrier layer covers the interface oxide layer.
7. The method for fabricating a semiconductor device according to claim 1, characterized in that, The process of forming a self-aligned barrier layer includes: A self-aligned barrier layer material is formed, the self-aligned barrier layer material covering the first region and the second region; Photolithography and etching processes are performed to remove the self-aligned barrier layer material in the first region.
8. The method for fabricating a semiconductor device according to claim 1, characterized in that, A silicon oxide protective layer is formed using the ALD-CVD process.
9. The method for fabricating a semiconductor device according to claim 1, characterized in that, The process of forming the metal silicide includes: The metal material layer deposition process and the SiCoNi etching process are performed cyclically, wherein the metal material layer is a nickel-platinum alloy layer; An annealing process is performed on the metal material layer to form the metal silicide.
10. A semiconductor device, characterized in that, It is prepared by the method of any one of claims 1 to 9.