An LDMOS device and a manufacturing method thereof

Abstract

The application discloses an LDMOS device and a manufacturing method thereof. The method comprises the following steps: providing a semiconductor substrate, forming a hard mask layer on the semiconductor substrate, etching the hard mask layer to form an opening exposing the semiconductor substrate, the sidewall of the opening having a slope morphology, performing a thermal oxidation process to grow a field oxide layer in the opening, the intersection of the field oxide layer and the hard mask layer forming a beak structure, reserving part of the hard mask layer above the beak structure, and removing the remaining hard mask layer. The application can make the silicon morphology at the intersection of the field oxide layer and the beak structure smoother, avoid double curvature morphology, and thus optimize the breakdown voltage and on-resistance of the LDMOS device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to an LDMOS device and a method for manufacturing the same. Background Technology

[0002] Lateral double-diffused metal-oxide-semiconductor (LDMOS) devices are widely used in power integrated circuits, RF power amplifiers, and automotive electronics due to their high breakdown voltage and excellent power handling capabilities. In the fabrication of LDMOS devices, a local oxidation of silicon (LOCOS) process is typically used to form a field oxide layer to achieve electrical isolation between the active regions.

[0003] In the conventional LOCOS process, a silicon nitride hard mask layer is first formed on a semiconductor substrate. Windows are then created in the hard mask layer using photolithography and etching processes to expose the areas to be field-oxidized. A thermal oxidation process is then performed to grow a field oxide layer in the exposed substrate area. During thermal oxidation, the oxidant diffuses downwards towards the edge of the hard mask layer, forming a so-called "bird's beak" structure.

[0004] Conventional LDMOS devices suffer from the following technical problems: First, at the junction of the field oxide layer and the bird's beak region, stress in the hard mask layer causes a hyperbolic morphology to form in the active region at the boundary between the open area of ​​the hard mask layer and the bird's beak region. This hyperbolic morphology reduces the breakdown voltage and increases the on-resistance of the LDMOS device, severely affecting its electrical performance. Second, the electric field accumulation effect in the bird's beak region leads to hot carrier injection reliability issues, affecting the device's lifespan and quality. Summary of the Invention

[0005] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0006] To address the existing problems, this application provides a method for manufacturing an LDMOS device, the method comprising: A semiconductor substrate is provided, and a hard mask layer is formed on the semiconductor substrate; The hard mask layer is etched to form an opening that exposes the semiconductor substrate, the opening having sidewalls that slope toward the center of the opening; A thermal oxidation process is performed to grow a field oxide layer inside the opening, and a bird's beak structure is formed at the junction of the field oxide layer and the hard mask layer. Retain a portion of the hard mask layer located above the beak structure, and remove the remaining hard mask layer.

[0007] In one embodiment, the etching includes dry etching, wherein etching the hard mask layer to form an opening exposing the semiconductor substrate includes: By adjusting the bias voltage and gas composition of the dry etching process, the lateral etching rate is made greater than the longitudinal etching rate to form the inclined sidewall.

[0008] In one embodiment, etching the hard mask layer to form an opening exposing the semiconductor substrate includes: A patterned photoresist layer is formed on the hard mask layer, and the hard mask layer is etched using the patterned photoresist layer as a mask. The patterned photoresist layer has inclined sidewalls.

[0009] In one embodiment, the thickness of the hard mask layer is 300 Å to 1000 Å.

[0010] In one embodiment, the material of the hard mask layer is silicon nitride or silicon oxynitride.

[0011] In one embodiment, the oblique angle of the sidewall relative to the surface of the semiconductor substrate is 20°-60°.

[0012] In one embodiment, the inclined sidewall extends from the top of the opening to the bottom of the opening, or the inclined sidewall extends from the top of the opening to the middle of the opening.

[0013] In one embodiment, the thermal oxidation process is a thermal dry oxidation process.

[0014] In one embodiment, a portion of the hard mask layer is located inside the drift region of the LDMOS device and does not extend into the channel region.

[0015] Another embodiment of this application provides an LDMOS device manufactured using the above-described manufacturing method.

[0016] According to the LDMOS device manufacturing method of this application embodiment, by forming inclined opening sidewalls in the hard mask layer, the lateral diffusion of the oxidant during thermal oxidation is more uniform, the stress distribution is improved, and the silicon morphology at the junction of the grown field oxide layer and the bird's beak is smoother, avoiding a double curvature morphology, thereby optimizing the breakdown voltage and on-resistance of the LDMOS device. By selectively retaining part of the hard mask layer at the bird's beak, the electric field distribution of the active region at the bird's beak is optimized, the electric field accumulation effect is alleviated, the breakdown risk is reduced, and the hot carrier injection reliability is improved. Furthermore, the manufacturing method of this application embodiment does not require reducing the thickness of the hard mask layer, avoiding the problems of increased bird's beak length and increased device size, which is beneficial for improving integration and reducing manufacturing costs. Attached Figure Description

[0017] The following drawings, which are incorporated herein by reference and are used to understand this application, illustrate embodiments of the invention and their descriptions to explain the principles of the invention.

[0018] In the attached image: Figures 1A-1C A cross-sectional view of an LDMOS device obtained by sequentially performing the steps of a manufacturing method in the related art is shown. Figure 1D It shows Figure 1C SEM image of the middle beak structure; Figure 1E The image shows a SEM image of the gate structure formed according to the manufacturing method of LDMOS devices in the related art. Figure 1F It shows Figure 1E SEM image of the middle beak structure; Figure 2 A schematic flowchart illustrating a method for manufacturing an LDMOS device according to an embodiment of this application is shown; Figures 3A-3F A cross-sectional view of an LDMOS device obtained by sequentially performing the steps of a method for manufacturing an LDMOS device according to an embodiment of this application is shown. Figure 4 It shows Figure 3D SEM image of the middle beak structure; Figure 5 A comparison diagram showing the TCAD simulation results of the embodiments of this application and the prior art is provided. Detailed Implementation

[0019] The following description provides numerous specific details to offer a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described to avoid confusion with this application.

[0020] It should be understood that this application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of this application to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0021] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0022] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0023] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0024] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0025] In related technologies, firstly, such as Figure 1A As shown, Figure 1A As shown, a semiconductor substrate 100 is provided, and a pad oxide layer 101 and a hard mask layer 102 are sequentially formed on the semiconductor substrate 100. Next, as... Figure 1B As shown, openings are formed in the hard mask layer 102 and the pad oxide layer 101 through photolithography and etching processes to expose the areas that need to be field-oxidized.

[0026] Next, as Figure 1C As shown, a thermal oxidation process is performed to grow a field oxide layer 103 within the opening. During the thermal oxidation process, the oxidant diffuses laterally below the hard mask layer 102, forming a bird's beak structure 104, and as shown... Figure 1D As shown, a double slope appears at the boundary between the opening region and the beak region (the location indicated by the elliptical dashed line in the figure).

[0027] Figure 1E This is a SEM image of the area after the gate structure has been formed. Figure 1F for Figure 1E A magnified SEM image of the bird's beak structure (shown by the dashed ellipse in the image) further demonstrates that the hyperbolic morphology persists throughout subsequent processes. This hyperbolic morphology reduces the breakdown voltage and increases the on-resistance of the LDMOS device, severely impacting its electrical performance. Furthermore, the electric field accumulation effect in the bird's beak region leads to hot carrier injection reliability issues, affecting the device's long-term lifespan and quality.

[0028] To address the aforementioned issues, existing technologies propose reducing stress concentration at the junction by decreasing the thickness of the hard mask layer. However, reducing the hard mask layer thickness leads to an increase in the beak length, resulting in a larger device size, reduced integration density, and increased manufacturing costs.

[0029] To address the aforementioned problems, this application provides an LDMOS device and a method for manufacturing the same. The following refers to... Figure 2 The manufacturing method of the LDMOS device according to embodiments of this application will be described in detail. For example... Figure 2 As shown, the manufacturing method mainly includes the following steps: In step S201, a semiconductor substrate is provided, and a hard mask layer is formed on the semiconductor substrate; In step S202, the hard mask layer is etched to form an opening that exposes the semiconductor substrate, the opening having sidewalls that slope toward the center of the opening; In step S203, a thermal oxidation process is performed to grow a field oxide layer inside the opening, and a bird's beak structure is formed at the junction of the field oxide layer and the hard mask layer. In step S204, the portion of the hard mask layer above the bird's beak structure is retained, and the remaining hard mask layer is removed.

[0030] The following reference Figures 3A-3F A method for manufacturing an LDMOS device according to one embodiment of this application will be described in detail. In this embodiment, a shallow trench isolation structure (STI) is formed based on the above method.

[0031] First, such as Figure 3A As shown, a semiconductor substrate 300 is provided. The material of the semiconductor substrate 300 includes, but is not limited to, at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other group III / V compound semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). As an example, in this embodiment, the semiconductor substrate 300 is made of single-crystal silicon material.

[0032] Next, a hard mask layer 302 is formed on the surface of the semiconductor substrate 300. The hard mask layer 302 serves as an oxide barrier layer in the subsequent LOCOS process. The material of the hard mask layer 302 is silicon nitride (SiN) or silicon oxynitride (SiON). Silicon nitride and silicon oxynitride are high-density materials with excellent oxygen diffusion barrier capabilities. In the LOCOS thermal oxidation process, oxygen has difficulty penetrating the silicon nitride or silicon oxynitride layer; therefore, oxygen can only enter through the openings in the hard mask layer 302 and react with the exposed semiconductor substrate to form silicon oxide. Simultaneously, oxygen diffuses laterally below the edge of the hard mask layer 302, forming a bird's beak structure.

[0033] The hard mask layer 302 can be formed by methods such as low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD). The thickness of the hard mask layer 302 is 300 Å-1000 Å, for example, 500 Å, 600 Å, 700 Å, or 800 Å. If the thickness of the hard mask layer 302 is too thin (less than 300 Å), the oxide blocking effect is insufficient, and the beak length increases; if the thickness of the hard mask layer 302 is too thick (greater than 1000 Å), the stress is too high, which can easily lead to substrate defects.

[0034] Optionally, a pad oxide layer 301 can be formed on the semiconductor substrate 300 before forming the hard mask layer 302. The pad oxide layer 301 can be formed by a thermal oxidation process to relieve stress between the hard mask layer 302 and the semiconductor substrate 300 and protect the surface of the semiconductor substrate 300.

[0035] Next, as Figure 3B As shown, the hard mask layer 302 is dry etched to form an opening that exposes the semiconductor substrate 300. The opening has sidewalls that slope towards the center of the opening, meaning that the width of the opening is wider at the top and narrower at the bottom.

[0036] Specifically, photoresist is coated over the hard mask layer 302, and a patterned photoresist layer is formed through exposure and development processes. The openings in the photoresist layer define the areas where LOCOS oxidation needs to be performed, i.e., the areas where the field oxide layer is to be formed.

[0037] Next, using the photoresist layer as a mask, the hard mask layer 302 is etched to form an opening that exposes the semiconductor substrate 300. In this embodiment, through process adjustments, the sidewalls of the etched opening are made into a sloping shape, with the width of the opening being wider at the top and narrower at the bottom.

[0038] In one embodiment, the etching process is a dry etching process. The sloping sidewalls can be formed by adjusting the process parameters of the dry etching process. Specifically, the bias voltage of the etching equipment and the composition of the etching gas are adjusted to make the lateral etching rate greater than the longitudinal etching rate. For example, adding an appropriate amount of polymerizing gas (such as CHF3, CH2F2, etc.) to the etching gas allows a polymer protective layer to form on the sidewalls during the etching process. Simultaneously, by adjusting the bias voltage to control the ion bombardment direction, anisotropic etching is achieved, resulting in a sloping morphology at the edge of the etched hard mask layer 302.

[0039] In another embodiment, the sloping sidewalls can be formed by adjusting the morphology of the photoresist. Specifically, in the photolithography process, the openings of the photoresist layer are made to have sloping sidewalls by adjusting the exposure dose and development conditions. During the subsequent etching process, the photoresist layer is gradually consumed, while its sloping profile is transferred to the hard mask layer 302, thereby forming an opening with sloping sidewalls in the hard mask layer 302.

[0040] For example, the angle between the sidewall and the surface of the semiconductor substrate 300 is 20°-60°, such as 30°, 40°, or 50°. Figure 3B As shown, the sloping sidewalls can extend directly from the top to the bottom of the opening; or, as... Figure 3C As shown, the inclined sidewalls can also extend from the top of the opening to the middle, with vertical sidewalls at the bottom. By forming an opening with inclined sidewalls, the diffusion path and stress distribution of the oxidant during subsequent thermal oxidation can be altered, resulting in a continuous and uniform stress distribution, and thus a smoother morphology of the active region at the junction of the field oxide layer and the beak structure.

[0041] Next, as Figure 3D As shown, a thermal oxidation process is performed to grow a field oxide layer 303 inside the opening, and a bird's beak structure is formed at the junction of the field oxide layer 303 and the hard mask layer 302.

[0042] Specifically, after removing the photoresist layer, a thermal oxidation process is performed. This thermal oxidation process is a hot dry oxygen oxidation process, which involves high-temperature oxidation in an oxygen-containing atmosphere. For example, the semiconductor substrate 300 is placed in an oxidation furnace tube, oxygen is introduced, the oxidation temperature is 900℃-1100℃, and the oxidation time is 30-120 minutes.

[0043] During the thermal oxidation process, the exposed surface of the semiconductor substrate 300 reacts with oxygen to generate silicon oxide, forming a field oxide layer 303. The thickness of the field oxide layer 303 is determined according to the device design requirements, for example, 2000Å-5000Å.

[0044] Because the hard mask layer 302 blocks oxygen diffusion, oxygen diffuses laterally below the edge of the hard mask layer 302, forming an oxide layer in the semiconductor substrate 300 below the edge of the hard mask layer 302, thus forming a bird's beak structure. The bird's beak structure is an unavoidable phenomenon in the LOCOS process, and its length and morphology are affected by factors such as the thickness of the hard mask layer 302, oxidation temperature, and time.

[0045] In this embodiment, because the opening of the hard mask layer 302 has inclined sidewalls, the diffusion of the oxidant below the edge of the hard mask layer 302 is more uniform, and the stress distribution is improved. Therefore, as Figure 4 As shown, the silicon morphology (substrate / active region morphology) at the interface between the grown field oxide layer 303 and the bird's beak structure is smoother, avoiding the hyperbolic morphology that occurs in conventional processes. Figure 5 As shown, TCAD (Technology Computer-Aided Design) simulation results indicate that the slope hard mask layer makes the silicon morphology at the junction of the grown field oxide layer and the bird's beak smoother.

[0046] Next, as Figure 3E As shown, a portion of the hard mask layer 302 is retained at the bird's beak structure, and the remaining hard mask layer 302 is removed.

[0047] Specifically, photoresist is coated on the wafer surface, and a patterned photoresist layer 304 is formed by exposure and development. This patterned photoresist layer 304 covers the area where the bird's beak structure is located and the hard mask layer 302 in the vicinity, while exposing the hard mask layer 302 in other areas. Then, using the patterned photoresist layer 304 as a mask, the exposed hard mask layer 302 is selectively removed by dry etching or wet etching.

[0048] The selectively retained portion of the hard mask layer 302 needs to be located inside the drift region and cannot extend into the channel region. Specifically, the retained hard mask layer 302 is located above the drift region of the LDMOS device to modulate the electric field distribution on the surface of the drift region and alleviate the electric field accumulation effect at the bird's beak. The retained hard mask layer 302 does not extend into the channel region to avoid adversely affecting the doping distribution and threshold voltage of the channel region.

[0049] By retaining the inclined hard mask layer 302 at the beak, the sharp steps or rough edges formed between the field oxide layer and the silicon interface caused by conventional processes can be avoided, making the interface smoother. The smooth transition interface eliminates sharp geometric abrupt changes, thereby effectively avoiding excessive concentration of electric field at sharp points, optimizing the electric field distribution in the active region at the beak, alleviating the electric field accumulation effect, reducing the risk of breakdown, and improving the hot carrier injection (HCI) reliability of LDMOS devices.

[0050] For example, when the hard mask layer 302 is a silicon nitride layer, wet etching is performed using a hot phosphoric acid solution to remove the hard mask layer 302 not covered by the photoresist layer 304. The temperature of the hot phosphoric acid is, for example, 150°C-180°C, and the etching time is adjusted according to the thickness of the hard mask layer, typically 30-90 minutes. The etching rate of hot phosphoric acid on silicon nitride is much higher than that on silicon oxide, therefore it will not damage the field oxide layer 303 and the pad oxide layer 301.

[0051] After removing the remaining hard mask layer 302, the underlying pad oxide layer 301 and the active region of the semiconductor substrate 300 are exposed. Next, as... Figure 3F As shown, a gate structure 305 is formed above the remaining hard mask layer 302. The gate structure 305 extends from the surface of the active region to the middle of the field oxide layer 303, covering the entire beak structure and the remaining hard mask layer 302.

[0052] This concludes the description of the manufacturing method of the LDMOS device according to the embodiments of this application. Subsequent conventional processes such as source / drain implantation and contact hole etching can then be performed, which will not be described in detail here.

[0053] According to the LDMOS device manufacturing method of this application embodiment, by forming an opening sidewall with a sloped morphology in the hard mask layer, the lateral diffusion of the oxidant during thermal oxidation is more uniform, the stress distribution is improved, and the silicon morphology at the junction of the grown field oxide layer and the bird's beak is smoother, avoiding a double curvature morphology, thereby optimizing the breakdown voltage and on-resistance of the LDMOS device. By selectively retaining part of the hard mask layer at the bird's beak, the electric field distribution of the active region at the bird's beak is optimized, the electric field accumulation effect is alleviated, and the hot carrier injection reliability is improved. Furthermore, the manufacturing method of this application embodiment does not require reducing the thickness of the hard mask layer, avoiding the problems of increased bird's beak length and increased device size, which is beneficial for improving integration and reducing manufacturing costs.

[0054] This application also provides an LDMOS device, which can be manufactured using the above-described process. For example... Figure 3F As shown, the LDMOS device in this application embodiment includes: a semiconductor substrate 300; a field oxide layer 303 formed in the semiconductor substrate 300, with bird beak structures on both sides of the field oxide layer 303, and an active region at the junction of the bird beak structure and the field oxide layer 303 having a smooth morphology; and a residual hard mask layer 302 located inside the drift region and above the bird beak structure.

[0055] Optionally, the residual hard mask layer 302 is made of silicon nitride or silicon oxynitride. Optionally, the residual hard mask layer 302 does not extend into the channel region. A gate structure 305 is formed above the hard mask layer 302, extending from the active region to above the field oxide layer 303.

[0056] In the LDMOS device of this application embodiment, the active region at the junction of the field oxide layer and the bird's beak structure has a smooth morphology, avoiding the electric field concentration and carrier scattering problems caused by the hyperbolic morphology. Therefore, it has a higher breakdown voltage, lower on-resistance, and better hot carrier injection reliability. At the same time, the residual hard mask layer located inside the drift region and above the bird's beak structure further optimizes the electric field distribution on the surface of the drift region, improving the overall performance of the device.

[0057] In another embodiment of this application, an electronic device is also provided, including the aforementioned LDMOS device, which is prepared according to the aforementioned method.

[0058] The electronic device in this embodiment can be any electronic product or device such as a mobile phone, tablet computer, laptop computer, netbook, television, VCD player, DVD player, navigator, digital photo frame, camera, camcorder, voice recorder, MP3 player, MP4 player, PSP, etc., or any intermediate product including circuitry. The electronic device in this embodiment has better performance because it uses the aforementioned LDMOS device.

[0059] This application has been described through the above embodiments. However, it should be understood that the above embodiments are for illustrative purposes only and are not intended to limit this application to the scope of the described embodiments. Furthermore, those skilled in the art will understand that this application is not limited to the above embodiments, and many more variations and modifications can be made based on the teachings of this application, all of which fall within the scope of protection claimed in this application. The scope of protection of this application is defined by the appended claims and their equivalents.

Claims

1. A method for manufacturing an LDMOS device, characterized in that, The method includes: A semiconductor substrate is provided, and a hard mask layer is formed on the semiconductor substrate; The hard mask layer is etched to form an opening that exposes the semiconductor substrate, the opening having sidewalls that slope toward the center of the opening and the sloped sidewalls extending downward from the top of the opening; A thermal oxidation process is performed to grow a field oxide layer inside the opening, and a bird's beak structure is formed at the junction of the field oxide layer and the hard mask layer. The portion of the hard mask layer located above the beak structure is retained, and the remaining hard mask layer is removed. The retained portion of the hard mask layer is located inside the drift region of the LDMOS device and does not extend into the channel region. A gate structure is formed over the reserved portion of the hard mask layer, the gate structure covering the reserved portion of the hard mask layer.

2. The manufacturing method according to claim 1, characterized in that, The etching includes dry etching, wherein etching the hard mask layer to form an opening exposing the semiconductor substrate includes: By adjusting the bias voltage and gas composition of the dry etching process, the lateral etching rate is made greater than the longitudinal etching rate to form the inclined sidewall.

3. The manufacturing method according to claim 1, characterized in that, The etching of the hard mask layer to form an opening exposing the semiconductor substrate includes: A patterned photoresist layer is formed on the hard mask layer, and the hard mask layer is etched using the patterned photoresist layer as a mask. The patterned photoresist layer has inclined sidewalls.

4. The manufacturing method according to claim 1, characterized in that, The thickness of the hard mask layer is 300 Å-1000 Å.

5. The manufacturing method according to claim 1, characterized in that, The material of the hard mask layer is silicon nitride or silicon oxynitride.

6. The manufacturing method according to claim 1, characterized in that, The angle between the sidewall and the surface of the semiconductor substrate is 20°-60°.

7. The manufacturing method according to claim 1, characterized in that, The inclined sidewall extends from the top of the opening to the bottom of the opening, or the inclined sidewall extends from the top of the opening to the middle of the opening.

8. The manufacturing method according to claim 1, characterized in that, The thermal oxidation process is a hot dry oxygen oxidation process.

9. An LDMOS device, characterized in that, It is manufactured using the manufacturing method described in any one of claims 1 to 8.

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