Semiconductor structure and its formation and testing methods

Abstract

A semiconductor structure and its formation and testing methods are disclosed. The formation method includes: providing a substrate, the substrate including a plurality of test regions and a connection region located between adjacent test regions, the substrate including a first surface and a second surface opposite to each other; forming interconnect vias through the substrate in the test regions; filling the interconnect vias with conductive material to form metal plugs; performing a first ion implantation process along the first surface into the connection regions to form a first doped region; forming a first pad, the first pad being electrically connected to a metal plug on one side of the first doped region; and forming a second pad, the second pad being electrically connected to the first doped region. By forming a first pad on the metal plug and a second pad on the first doped region, the presence of leakage current between the metal plug and the substrate can be tested by connecting the first pad and the second pad. Furthermore, the metal plug can be optimized based on the test results to improve its reliability, thereby improving the performance of the semiconductor.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and more particularly to a semiconductor structure and its formation and testing methods. Background Technology

[0002] Through Silicon Via (TSV) is a vertical interconnect that penetrates a silicon wafer or chip. As manufacturing processes continue to shrink, Moore's Law is approaching its limits. Application demands are shifting towards lower power consumption, higher efficiency, and faster speeds. Moore's Law is no longer applicable to the manufacturing of modern high-end electronic devices. Therefore, starting from packaging structures, there is a shift from traditional planar structures to 2.5D / 3D or even heterogeneous integration modes.

[0003] However, there are still some potential problems with through-silicon vias in current semiconductor devices, but existing technologies cannot test these problems and therefore cannot optimize the through-silicon vias in semiconductor devices to improve their performance. Summary of the Invention

[0004] The technical problem solved by this invention is how to improve the performance of semiconductor devices.

[0005] To address the aforementioned technical problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a plurality of test regions and a connection region located between adjacent test regions, the substrate including a first surface and a second surface opposite to each other; forming a first photoresist layer on the first surface, the first photoresist layer in the test regions having a metal plug pattern; using the first photoresist layer with the metal plug pattern as a mask, etching the substrate to form interconnect vias penetrating the substrate in the test regions; filling the interconnect vias with a conductive material to form metal plugs, the metal plugs including a conductive layer and an insulating oxide layer located on the sidewall surface of the conductive layer; performing a first ion implantation process along the first surface toward the connection regions to form a first doped region; forming a first pad, the first pad being electrically connected to the metal plug on one side of the first doped region; and forming a second pad, the second pad being electrically connected to the first doped region.

[0006] Optionally, the step of forming the first pad includes: forming a first metal layer on the metal plug on one side of the first doped region on the first surface and on a portion of the substrate; forming a first interlayer dielectric layer on the first surface; etching the first interlayer dielectric layer to expose the surface of the first metal layer to form a plug opening; filling the plug opening with a conductive material to form a first conductive plug, the first conductive plug being electrically connected to the first metal layer; and forming a first pad on the first conductive plug, the first pad being electrically connected to the first conductive plug.

[0007] Optionally, the step of forming the second pad includes: forming a second metal layer on a first doped region on the first surface and on a portion of the substrate; forming a first interlayer dielectric layer on the first surface; etching the first interlayer dielectric layer to expose the surface of the second metal layer, forming a plug opening; filling the plug opening with a conductive material to form a first conductive plug, the first conductive plug being electrically connected to the second metal layer; and forming a second pad on the first conductive plug, the second pad being electrically connected to the first conductive plug.

[0008] Optionally, the process for forming the first doped region is: a first ion implantation process, wherein the process parameters of the first ion implantation process are: the dopant ions are P-type or N-type, and the doping energy ranges from 100 keV to 3000 keV.

[0009] Optionally, the method of forming the semiconductor structure further includes: forming a third pad, the third pad being electrically connected to the metal plug on the other side of the first doped region.

[0010] Optionally, the step of forming the third pad includes: forming a third metal layer on the metal plug on the other side of the first doped region on the first surface and on a portion of the substrate; forming a first interlayer dielectric layer on the substrate; etching the first interlayer dielectric layer to expose the surface of the third metal layer to form a plug opening; filling the plug opening with a conductive material to form a first conductive plug, the first conductive plug being electrically connected to the third metal layer; and forming a third pad on the first conductive plug, the third pad being electrically connected to the first conductive plug.

[0011] Optionally, the electrode polarity of the first pad is opposite to that of the second pad, and the electrode polarity of the first pad is opposite to that of the third pad.

[0012] Optionally, prior to the step of forming the metal plug, the method further includes: performing a second ion implantation process along the second surface into the connection region to form a second doped region; forming a second interlayer dielectric layer on the second surface of the substrate; and forming a conductive ring within the second interlayer dielectric layer.

[0013] Optionally, the process for forming the second doped region is a second ion implantation process, wherein the process parameters of the second ion implantation process are: the dopant ions are P-type or N-type, and the doping energy ranges from 100 keV to 3000 keV.

[0014] Optionally, after forming the conductive ring, the method further includes: forming a fourth metal layer on the metal plug on the second surface, the fourth metal layer being electrically connected to the metal plug on one side of the conductive ring; and forming a fifth metal layer on the metal plug and the conductive ring on the second surface, the fifth metal layer being electrically connected to the metal plug located on the other side of the conductive ring and the conductive ring.

[0015] Optionally, the substrate further includes a device region; the semiconductor structure further includes a device structure located within the device region; the method of forming the device structure includes: prior to the step of forming the second interlayer dielectric layer: performing a first implantation process on the substrate within the device region of the second surface to form a well region; performing an implantation process within the well region to form a source / drain region; and forming a gate structure between adjacent source / drain regions.

[0016] Optionally, the step of forming the source / drain region is performed simultaneously with the step of forming the second doped region.

[0017] Accordingly, the present invention also provides a semiconductor structure, comprising: a substrate, the substrate including a plurality of test regions and a connection region located between adjacent test regions, the substrate including opposing first and second surfaces; a metal plug located within the test regions and penetrating the substrate, the metal plug including a conductive layer and an insulating oxide layer located on the sidewall surface of the conductive layer; a first doped region located within the connection region and located on a first surface of the substrate; a first pad located on the metal plug on one side of the first doped region and electrically connected to the metal plug on the first doped region; and a second pad located on the first doped region and electrically connected to the first doped region.

[0018] Optionally, the semiconductor structure further includes a third pad located on the metal plug on the other side of the first doped region, the third pad being electrically connected to the metal plug on the other side of the first doped region.

[0019] Optionally, the electrode polarity of the first pad is opposite to that of the second pad, and the electrode polarity of the first pad is opposite to that of the third pad.

[0020] Optionally, the semiconductor structure further includes: a first metal layer located on a metal plug on the first surface and on a portion of the substrate; a second metal layer located on a first doped region on the first surface and on a portion of the substrate; a third metal layer located on a metal plug on the first surface and on a portion of the substrate; a first interlayer dielectric layer located on the first surface; and a first conductive plug located within the first interlayer dielectric layer and electrically connected to the first metal layer, the second metal layer, and the third metal layer.

[0021] Optionally, the semiconductor structure further includes: a second doped region located within the connection region, and the second doped region being located on a second surface of the substrate; a second interlayer dielectric layer located on the second surface of the substrate; and a conductive ring located within the second interlayer dielectric layer.

[0022] Optionally, the semiconductor structure further includes: a fourth metal layer, a metal plug located on the second surface, the fourth metal layer being electrically connected to the metal plug on one side of the conductive ring; and a fifth metal layer, located on the metal plug and the conductive ring on the second surface, the fifth metal layer being electrically connected to the metal plug located on the other side of the conductive ring and the conductive ring.

[0023] Optionally, the substrate further includes a device region; the semiconductor structure further includes: a device structure located within the device region, the device structure including: a well region located within the substrate of the device region on the second surface; a source / drain region located within the well region; and a gate structure located between adjacent source / drain regions.

[0024] Optionally, the device structure is a combination of one or more of transistors, memory cells, resistors, capacitors, and inductors.

[0025] Accordingly, the present invention also provides a method for testing a semiconductor structure, comprising: electrically connecting a first pad and a second pad to obtain a first test current; comparing the test current with a preset threshold to obtain a first test result, wherein the first test result includes: when the first test current is greater than or equal to the preset threshold, a leakage path exists in the semiconductor structure and the leakage location is located on the sidewall of a metal plug in the substrate; when the first test current is less than the preset threshold, no leakage path exists in the semiconductor structure.

[0026] Optionally, the testing method further includes: electrically connecting the first pad and the third pad to obtain a second test current; comparing the second test current with a preset threshold to obtain a comparison result, wherein the comparison result includes: when the second test current is greater than or equal to the preset threshold, there is a leakage path in the semiconductor structure; when the first test current is less than the preset threshold, there is no leakage path in the semiconductor structure; and obtaining a second test result based on the comparison result and the first test result.

[0027] Optionally, the method for obtaining the second test result based on the comparison result and the first test result includes: when the second test current is greater than or equal to the preset threshold and the first test current is less than the preset threshold, the leakage location is located on the metal plug sidewall in the second interlayer dielectric layer; when the second test current is greater than or equal to the preset threshold, the second test current is greater than the first test current, and the first test current is greater than or equal to the preset threshold, the leakage location is located on the metal plug sidewall in the second interlayer dielectric layer and the metal plug sidewall in the substrate.

[0028] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0029] In the semiconductor structure of the present invention, the first pad is located on the metal plug and the second pad is located on the first doped region. Subsequently, by connecting the first pad and the second pad, it is possible to test whether there is leakage between the metal plug and the substrate, and the metal plug can be optimized based on the test results to improve the reliability of the metal plug, ensure the longitudinal transmission of signals, and thus improve the performance of the semiconductor.

[0030] Furthermore, the third pad and the first pad are respectively located on adjacent metal plugs. Subsequently, by connecting the first pad and the third pad, it is possible to test whether there is leakage between the metal plug and the second interlayer dielectric layer. Based on the test results, the metal plug can be optimized to improve its reliability, ensure the longitudinal transmission of signals, and thus improve the performance of the semiconductor.

[0031] The semiconductor structure formation method in the technical solution of the present invention forms a first pad on the metal plug and a second pad on the first doped region. Subsequently, by connecting the first pad and the second pad, it is possible to test whether there is leakage between the metal plug and the substrate, and the metal plug can be optimized according to the test results to improve the reliability of the metal plug, ensure the longitudinal transmission of signals, and thus improve the performance of the semiconductor.

[0032] Furthermore, the third pad and the first pad are formed on adjacent metal plugs respectively. Subsequently, by connecting the first pad and the third pad, it is possible to test whether there is leakage between the metal plug and the interlayer dielectric layer. Based on the test results, the metal plug can be optimized to improve its reliability, ensure the longitudinal transmission of signals, and thus improve the performance of the semiconductor.

[0033] Furthermore, the step of forming the source / drain region is performed simultaneously with the step of forming the second doped region, eliminating the need for additional process steps to separately dope the second doped region, thus simplifying the process and reducing manufacturing costs.

[0034] The semiconductor structure testing method in the technical solution of the present invention tests whether there is leakage between the metal plug and the substrate by connecting the first pad and the second pad, and can optimize the metal plug according to the test results to improve the reliability of the metal plug, ensure the longitudinal transmission of signals, and thus improve the performance of the semiconductor.

[0035] Furthermore, by connecting the first pad and the third pad, it is possible to test whether there is leakage between the metal plug and the second interlayer dielectric layer. The metal plug can be optimized based on the test results to improve its reliability, ensure longitudinal signal transmission, and thus improve the performance of the semiconductor. Attached Figure Description

[0036] Figures 1 to 2 This is a schematic diagram of the formation process of a semiconductor structure;

[0037] Figures 3 to 12 This is a schematic diagram of the formation process of a semiconductor structure in one embodiment of the present invention. Detailed Implementation

[0038] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0039] Please refer to the current process for forming through-silicon vias (TSVs). Figure 1 The method includes: providing a substrate 100, the substrate 100 including opposing first and second surfaces; forming an interlayer dielectric layer 101 on the second surface of the substrate 100; forming a metal layer 102 on the interlayer dielectric layer 101; forming a photoresist layer with a metal plug pattern on the first surface; using the photoresist layer with the metal plug pattern as a mask, etching the substrate 100 and the interlayer dielectric layer 101 until the surface of the metal layer 102 is exposed, forming an interconnect via 103 penetrating the substrate 100 and the interlayer dielectric layer 101.

[0040] Please refer to Figure 2 An insulating oxide layer 104 is deposited on the sidewall surface of the interconnecting via 103.

[0041] In the above scheme, during the etching process to form the interconnect via 103, TaN / Ta from the surface of the metal layer 102 is sputtered onto the sidewall of the via, forming a sputtered layer 1021. This results in uneven thickness of the sidewall of the interconnect via 103. Figure 2The area 105 within the dashed box is prone to charge accumulation, resulting in increased potential and concentrated electric field, which can lead to tip discharge and easy breakdown of the insulating oxide layer, causing leakage problems. Furthermore, the presence of a sputtered layer 1021 on the sidewall of the interconnect via 103 degrades the quality of the subsequently deposited insulating oxide layer 104, further increasing the risk of leakage in the silicon via and affecting electrical parameters such as dielectric breakdown voltage and capacitance.

[0042] However, there is currently a lack of effective methods to monitor leakage current issues in through-silicon vias (TSVs), and it is impossible to optimize TSVs in semiconductor devices to address these issues, thus reducing the performance of semiconductor devices.

[0043] To address the aforementioned issues, the present invention provides a semiconductor structure and its formation and testing methods. By forming a first pad on the metal plug and a second pad on the first doped region, the present invention can subsequently test whether there is leakage between the metal plug and the substrate by connecting the first pad and the second pad. Furthermore, the metal plug can be optimized based on the test results to improve its reliability, ensure longitudinal signal transmission, and thereby improve the performance of the semiconductor.

[0044] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0045] Please refer to Figure 3 A substrate 200 is provided, the substrate 200 including a plurality of test areas I and a connection area II located between adjacent test areas I, the substrate 200 including a first surface b and a second surface opposite to each other.

[0046] In some embodiments of the present invention, a second ion implantation process is performed along the second surface a toward the connection region II to form a second doped region 203.

[0047] In some embodiments of the present invention, the process for forming the second doped region 203 is a second ion implantation process, wherein the process parameters of the second ion implantation process are: the dopant ions are P-type or N-type, and the doping energy ranges from 100 keV to 3000 keV.

[0048] In this embodiment, the ion type in the second doped region 203 is P-type.

[0049] In some embodiments of the present invention, the substrate 200 further includes a device region III; the semiconductor structure further includes a device structure located within the device region III.

[0050] In some embodiments of the present invention, the method of forming the device structure includes: implanting a substrate 200 in the device region III of the second surface a to form a well region 201; and implanting a source / drain region 202 in the well region 201.

[0051] In this embodiment, the doping type of the ions in the well region 201 is opposite to the doping type of the ions in the source / drain region 202.

[0052] In this invention, the steps of forming the source / drain region 202 and forming the second doped region 203 are performed simultaneously. That is, in this invention, there is no need to add a process step to separately dope the second doped region 203, which simplifies the process steps and reduces the manufacturing cost.

[0053] In this embodiment, the device structure is a combination of one or more of transistors, memory cells, resistors, capacitors, and inductors.

[0054] In this embodiment, the substrate 200 is made of silicon.

[0055] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0056] Please refer to Figure 4 A gate structure 204 is formed between adjacent source / drain regions 202; a first sublayer dielectric layer 2081 is formed on the second surface a; the first sublayer dielectric layer 2081 is etched to expose the surface of the second doped region 203 and the surface of the gate structure 204 to form a plug opening; and a plug 205 is formed in the plug opening.

[0057] In this invention, the plug 205 on the surface of the second doped region 203 and the plug 205 on the surface of the gate structure 204 are formed simultaneously. That is, in this invention, there is no need to add a process step to form the plug 205 separately on the surface of the second doped region 203, which simplifies the process steps and reduces the manufacturing cost.

[0058] Please refer to Figure 5A second interlayer dielectric layer 2082 is formed on the first interlayer dielectric layer 2081; the second interlayer dielectric layer is etched to form a conductive ring 206; an initial metal layer (not shown in the figure) is formed on the second interlayer dielectric layer 2082; the initial metal layer is etched to expose the surface of the second interlayer dielectric layer 2082, forming a fourth metal layer 2091 on the test area I on one side of the conductive ring 206 and a fifth metal layer 2092 on the test area I on the other side of the conductive ring 206.

[0059] In some embodiments of the present invention, the second interlayer dielectric layer includes the first sublayer dielectric layer 2081 and the second sublayer dielectric layer 2082.

[0060] In some embodiments of the present invention, the material of the second interlayer dielectric layer includes silicon oxide, nitrogen-doped silicon oxide, or silicon oxynitride.

[0061] In some embodiments of the present invention, the material of the fourth metal layer 2091 is TaN or Ta; the material of the fifth metal layer 2092 is TaN or Ta.

[0062] In some embodiments of the present invention, the fourth metal layer 2091 is used for electrical connection with the metal plug 210 on one side of the subsequently formed conductive ring 206; the fifth metal layer 2092 is used for electrical connection with the metal plug 210 on the other side of the subsequently formed conductive ring 206 and the conductive ring 206.

[0063] In this embodiment, the conductive ring 206 includes a first sub-metal layer, a first sub-plug located on the first sub-metal layer, a second sub-metal layer located on the first sub-plug, a second sub-plug located on the second sub-metal layer, a third sub-metal layer located on the second sub-plug, and a third sub-plug located on the third sub-metal layer.

[0064] In some embodiments of the present invention, the conductive ring 206 is used to electrically connect the second interlayer dielectric layer and the subsequently formed metal plug 210.

[0065] In other embodiments, the conductive ring is also used to isolate noise in the circuit, prevent noise from interfering with other circuit parts, and reduce parasitic effects, thereby improving the stability and reliability of the circuit.

[0066] In some embodiments of the present invention, the method further includes etching the second sub-layer interlayer dielectric layer to form a metal interconnect layer 207, the metal interconnect layer 207 being used to connect the device structure in the device region, for example, to the gate structure.

[0067] In the above scheme, the metal connection layer 207 and the conductive ring 206 are formed simultaneously. That is, in this invention, there is no need to add a process step to form the conductive ring 206 separately, which simplifies the process steps and reduces the manufacturing cost.

[0068] Please refer to Figure 6 A first photoresist layer is formed on the first surface b, and a metal plug 210 pattern is formed on the first photoresist layer in the test area I. Using the first photoresist layer with the metal plug 210 pattern as a mask, the substrate 200 and the second interlayer dielectric layer are etched until the surface of the fourth metal layer 2091 and the surface of the fifth metal layer 2092 are exposed, and an interconnect via 2101 penetrating the substrate 200 is formed in the test area I.

[0069] In some embodiments of the present invention, the method for etching to form interconnect vias 2101 is a dry etching process, wherein the process parameters of the dry etching process are: chamber pressure of 5 mT to 15 mT, source power of 350 W to 1200 W, bias voltage of 150 V to 600 V, gas flow rate of 20 sccm to 200 sccm, and etching time of 8 s to 60 s.

[0070] In other embodiments not illustrated, during the etching of the substrate and the second interlayer dielectric layer, TaN or Ta material on the surface of the fourth metal layer and the fifth metal layer is sputtered onto the sidewalls of the interconnect vias. The sidewalls are uneven in thickness, which easily accumulates charge, leading to increased potential and concentrated electric field, which in turn causes tip discharge. The insulating oxide layer is prone to breakdown and leakage problems.

[0071] Please refer to Figure 7 An insulating oxide layer 2102 is formed on the surface of the interconnecting via 2101.

[0072] In this embodiment, the process for forming the insulating oxide layer 2102 is chemical vapor deposition.

[0073] In this embodiment, the process parameters for forming the insulating oxide layer 2102 are: the deposition rate of the insulating oxide layer 2102 is 400 angstroms per minute to 600 angstroms per minute, and the deposition time of the insulating oxide layer 2102 is one minute to two minutes.

[0074] In some embodiments of the present invention, the insulating oxide layer 2102 is made of silicon oxide or silicon nitride, and the insulating oxide layer 2102 is used to electrically isolate the substrate 200 and the subsequently formed metal plug 210.

[0075] In other embodiments, the presence of TaN or Ta on the sidewalls of the interconnect vias leads to a deterioration in the deposition quality of the insulating oxide layer, resulting in uneven thickness of the insulating oxide layer deposited on the sidewalls of the interconnect vias. This, in turn, causes leakage risk in the subsequently formed metal plugs, thereby affecting the breakdown voltage and capacitance electrical parameters of the dielectric layer.

[0076] Please refer to Figure 8 The insulating oxide layer 2102 on the bottom surface of the interconnect via 2101 is etched until the surface of the fourth metal layer 2091 and the surface of the fifth metal layer 2092 are exposed.

[0077] In some embodiments of the present invention, the insulating oxide layer 2102 on the bottom surface of the interconnect via 2101 is etched to expose the surfaces of the fourth metal layer 2091 and the fifth metal layer 2092, thereby enabling the subsequently formed metal plug 210 to be electrically connected to the surface of the fourth metal layer 2091 and to the surface of the fifth metal layer 2092.

[0078] Please refer to Figure 9 Conductive material is filled into the interconnecting via 2101 to form a conductive layer 2103.

[0079] In some embodiments of the present invention, the metal plug 210 includes a conductive layer 2103 and an insulating oxide layer 2102 located on the sidewall surface of the conductive layer 2103.

[0080] In some embodiments of the present invention, the conductive layer 2103 is made of copper.

[0081] Please refer to Figure 10 A first ion implantation process is performed along the first surface b toward the connection region II to form a first doped region 217.

[0082] In some embodiments of the present invention, the process for forming the first doped region 217 is: a first ion implantation process, wherein the process parameters of the first ion implantation process are: the dopant ions are P-type or N-type, and the doping energy ranges from 100 keV to 3000 keV.

[0083] In this embodiment, the ion type in the first doped region 217 is P-type.

[0084] In some embodiments of the present invention, the first doped region 217 is used to lead out the leakage path between the metal plug 210 and the substrate 200 when the metal plug 210 leaks current.

[0085] Please refer to Figure 11An initial metal layer (not shown in the figure) is formed on the first surface b; the initial metal layer is etched to expose the surface of the substrate 200, forming a first metal layer 211 on the metal plug 210 on one side of the first doped region 217 and on a portion of the substrate 200, a second metal layer 212 on the first doped region 217 and on a portion of the substrate 200, and a third metal layer 213 on the metal plug 210 on the other side of the first doped region 217 and on a portion of the substrate 200.

[0086] In some embodiments of the present invention, the first metal layer 211 is used to electrically connect with the metal plug 210 on one side of the first doped region 217; the second metal layer 212 is used to electrically connect with the first doped region 217; and the third metal layer 213 is used to electrically connect with the metal plug 210 on the other side of the first doped region 217.

[0087] Please refer to Figure 12 A first interlayer dielectric layer 218 is formed on the first surface b; the first interlayer dielectric layer 218 is etched to expose the surfaces of the first metal layer 211, the second metal layer 212, and the third metal layer 213, forming a plug opening (not shown in the figure); a conductive material is filled into the plug opening to form a first conductive plug 2181; a first pad 214, a second pad 215, and a third pad 216 are formed on the first conductive plug.

[0088] In some embodiments of the present invention, the material of the first interlayer dielectric layer 218 includes silicon oxide, nitrogen-doped silicon oxide, or silicon oxynitride.

[0089] In some embodiments of the present invention, the first conductive plug is electrically connected to the first metal layer 211; the first conductive plug is electrically connected to the second metal layer 212; and the first conductive plug is electrically connected to the third metal layer 213.

[0090] In some embodiments of the present invention, the first pad 214, the second pad 215 and the third pad 216 are all electrically connected to the first conductive plug 2181.

[0091] In some embodiments of the present invention, the first pad 214 is electrically connected to the metal plug 210 on one side of the first doped region 217 via the first conductive plug 2181; the second pad 215 is electrically connected to the first doped region 217 via the first conductive plug 2181; and the third pad 216 is electrically connected to the metal plug 210 on the other side of the first doped region 217 via the first conductive plug 2181.

[0092] In some embodiments of the present invention, the electrode polarity of the first pad 214 is opposite to that of the second pad 215, and the electrode polarity of the first pad 214 is opposite to that of the third pad 216.

[0093] In this embodiment, the first pad 214 is the positive electrode, the second pad 215 is the negative electrode, and the third pad 216 is the negative electrode.

[0094] In the above scheme, by forming the first pad 214 on the metal plug 210 and the second pad 215 on the first doped region 217, the first pad 214 and the second pad 215 can be connected to test whether there is leakage between the metal plug 210 and the substrate 200. The metal plug 210 can be optimized based on the test results to improve its reliability, ensure the longitudinal transmission of signals, and thus improve the performance of the semiconductor.

[0095] Furthermore, the third pad 216 and the first pad 214 are formed on adjacent metal plugs 210 respectively. Subsequently, by connecting the first pad 214 and the third pad 216, it is possible to test whether there is leakage between the metal plug 210 and the interlayer dielectric layer. Based on the test results, the metal plug 210 can be optimized to improve its reliability, ensure the longitudinal transmission of signals, and thus improve the performance of the semiconductor.

[0096] Accordingly, please continue to refer to Figure 12 The present invention also provides a semiconductor structure, comprising: a substrate 200, the substrate 200 including a plurality of test regions I and a connection region II located between adjacent test regions I, the substrate 200 including a first surface b and a second surface a opposite to each other; a metal plug 210 located within the test regions I and penetrating the substrate 200, the metal plug 210 including a conductive layer 2103 and an insulating oxide layer 2102 located on the sidewall surface of the conductive layer 2103; a first doped region 217 located within the connection region II and located on the first surface b of the substrate 200; a first pad 214 located on the metal plug 210 on one side of the first doped region 217 and electrically connected to the metal plug 210 on one side of the first doped region 217; and a second pad 215 located on the first doped region 217 and electrically connected to the first doped region 217.

[0097] In some embodiments of the present invention, the semiconductor structure further includes a third pad 216 located on the metal plug 210 on the other side of the first doped region 217, the third pad 216 being electrically connected to the metal plug 210 on the other side of the first doped region 217.

[0098] In some embodiments of the present invention, the electrode polarity of the first pad 214 is opposite to that of the second pad 215, and the electrode polarity of the first pad 214 is opposite to that of the third pad 216.

[0099] In some embodiments of the present invention, the semiconductor structure further includes: a first metal layer 211 located on a metal plug 210 on the first surface b and on a portion of the substrate 200; a second metal layer 212 located on a first doped region 217 on the first surface b and on a portion of the substrate 200; a third metal layer 213 located on the metal plug 210 on the first surface b and on a portion of the substrate 200; a first interlayer dielectric layer 218 located on the first surface b; and a first conductive plug 2181 located within the first interlayer dielectric layer 218 and electrically connected to the first metal layer 211, the second metal layer 212, and the third metal layer 213.

[0100] In some embodiments of the present invention, the semiconductor structure further includes: a second doped region 203 located within the connection region II, and the second doped region 203 located on the second surface a of the substrate 200; a second interlayer dielectric layer located on the second surface a of the substrate 200; and a conductive ring 206 located within the second interlayer dielectric layer.

[0101] In some embodiments of the present invention, the semiconductor structure further includes: a fourth metal layer 2091, a metal plug 210 located on the second surface a, the fourth metal layer 2091 being electrically connected to the metal plug 210 on one side of the conductive ring 206; and a fifth metal layer 2092 located on the metal plug 210 and the conductive ring 206 on the second surface a, the fifth metal layer 2092 being electrically connected to the metal plug 210 located on the other side of the conductive ring 206 and the conductive ring 206.

[0102] In some embodiments of the present invention, the substrate 200 further includes a device region III; the semiconductor structure further includes a device structure located within the device region III, the device structure including: a well region 201 located within the substrate 200 of the device region III on the second surface a; a source / drain region 202 located within the well region 201; and a gate structure 204 located between adjacent source / drain regions 202.

[0103] In some embodiments of the present invention, the device structure is a combination of one or more of transistors, memory cells, resistors, capacitors, and inductors.

[0104] In the above scheme, the first pad 214 is located on the metal plug 210, and the second pad 215 is located on the first doped region 217. Subsequently, by connecting the first pad 214 and the second pad 215, it is possible to test whether there is leakage between the metal plug 210 and the substrate 200, and the metal plug 210 can be optimized based on the test results to improve the reliability of the metal plug 210, ensure the longitudinal transmission of signals, and thus improve the performance of the semiconductor.

[0105] Furthermore, the first pad 214 is located on the metal plug 210, and the second pad 215 is located on the first doped region 217. Subsequently, by connecting the first pad 214 and the second pad 215, it is possible to test whether there is leakage between the metal plug 210 and the substrate 200, and the metal plug 210 can be optimized based on the test results to improve the reliability of the metal plug 210, ensure the longitudinal transmission of signals, and thus improve the performance of the semiconductor.

[0106] Accordingly, please continue to refer to Figure 12 The present invention also provides a method for testing a semiconductor structure, comprising: electrically connecting a first pad 214 and a second pad 215 to obtain a first test current; comparing the test current with a preset threshold to obtain a first test result, wherein the first test result includes: when the first test current is greater than or equal to the preset threshold, a leakage path exists in the semiconductor structure and the leakage location is located on the sidewall of the metal plug 210 in the substrate 200; when the first test current is less than the preset threshold, no leakage path exists in the semiconductor structure.

[0107] In this embodiment, the preset threshold ranges from 0mA to 1mA.

[0108] In this embodiment, the first pad 214 is the positive electrode, and the second pad 215 is the negative electrode.

[0109] In some embodiments of the present invention, the testing method further includes: electrically connecting the first pad 214 and the third pad 216 to obtain a second test current; comparing the second test current with a preset threshold to obtain a comparison result, wherein the comparison result includes: when the second test current is greater than or equal to the preset threshold, a leakage path exists in the semiconductor structure; when the first test current is less than the preset threshold, no leakage path exists in the semiconductor structure; and obtaining a second test result based on the comparison result and the first test result.

[0110] In some embodiments of the present invention, the method for obtaining a second test result based on the comparison result and the first test result includes: when the second test current is greater than or equal to the preset threshold and the first test current is less than the preset threshold, the leakage location is located on the sidewall of the metal plug 210 in the second interlayer dielectric layer; when the second test current is greater than or equal to the preset threshold, the second test current is greater than the first test current, and the first test current is greater than or equal to the preset threshold, the leakage location is located on the sidewall of the metal plug 210 in the second interlayer dielectric layer and the sidewall of the metal plug 210 in the substrate 200.

[0111] In this embodiment, the test method can also test whether the thickness of the insulating oxide layer 2102 is within a preset thickness range. Specifically, when a leakage path exists in the semiconductor structure, it indicates that the thickness of the insulating oxide layer 2102 is too thin, reducing its insulation performance and causing a leakage path between the metal plug 210 and the substrate 200, thus indicating that the thickness of the insulating oxide layer 2102 is less than the preset thickness range. When no leakage path exists in the semiconductor structure, it indicates that the thickness of the insulating oxide layer 2102 is sufficient to ensure electrical isolation between the metal plug 210 and the substrate 200, and between the metal plug 210 and the second interlayer dielectric layer, thus indicating that the thickness of the insulating oxide layer 2102 is within the preset thickness range.

[0112] In this embodiment, the preset thickness range is 0 angstroms to 1200 angstroms.

[0113] In other embodiments, the test method is also used to test the breakdown voltage of the metal plug. Specifically, a voltage is applied to the first pad and the second pad; the voltage is continuously increased; and the breakdown state between the metal plug and the substrate is obtained based on the voltage.

[0114] In one embodiment, when a breakdown occurs between the metal plug 210 and the substrate 200, the voltage corresponding to the first pad 214 and the second pad 215 is the breakdown voltage.

[0115] In a specific embodiment, when the customer requires a preset breakdown voltage of 80V, a voltage increasing from 0V to 200V is applied to the first pad 214 and the second pad 215 to monitor the leakage current (i.e., the first test current) between the metal plug 210 and the substrate 200. If the leakage current reaches a preset threshold, it is confirmed that a breakdown has occurred between the metal plug 210 and the substrate 200, and the breakdown voltage is greater than 80V. At this time, the thickness of the insulating oxide layer 2102 meets the customer's requirements. If the leakage current is less than 80V, the thickness of the insulating oxide layer 2102 does not meet the customer's requirements, and the thickness of the insulating oxide layer 2102 needs to be increased to optimize the metal plug 210.

[0116] In other embodiments, the test method is also used to test the capacitance of the metal plug. Specifically, an alternating current is applied to the first pad and the second pad; and the voltage of the first pad and the second pad is measured. Based on the current value of the alternating current and the voltage values ​​of the first pad and the second pad, the capacitance between the metal plug and the substrate is calculated.

[0117] Of course, the testing method in this embodiment of the invention is not limited to testing the performance parameters described above. The testing method is also used to test other performance parameters within the semiconductor structure, thus achieving test diversity of the test structure.

[0118] In the above scheme, by connecting the first pad 214 and the second pad 215, it is possible to test whether there is leakage between the metal plug 210 and the substrate 200, and the metal plug 210 can be optimized according to the test results to improve the reliability of the metal plug 210, ensure the longitudinal transmission of signals, and thus improve the performance of the semiconductor.

[0119] Furthermore, by connecting the first pad 214 and the third pad 216, it is possible to test whether there is leakage between the metal plug 210 and the second interlayer dielectric layer. Based on the test results, the metal plug 210 can be optimized to improve its reliability, ensure the longitudinal transmission of signals, and thus improve the performance of the semiconductor.

[0120] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a plurality of test areas and a connection area located between adjacent test areas, the substrate including opposing first and second surfaces; A first photoresist layer is formed on the first surface, and a metal plug pattern is present on the first photoresist layer in the test area. Using a first photoresist layer with a metal plug pattern as a mask, the substrate is etched to form interconnect vias penetrating the substrate in the test area; A conductive material is filled into the interconnect via to form a metal plug, the metal plug comprising a conductive layer and an insulating oxide layer located on the sidewall surface of the conductive layer; A first ion implantation process is performed along the first surface into the connection region to form a first doped region; A first pad is formed, and the first pad is electrically connected to the metal plug on one side of the first doped region; A second pad is formed, and the second pad is electrically connected to the first doped region.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The steps to form the first pad include: A first metal layer is formed on the metal plug on the first doped region side of the first surface and on a portion of the substrate; A first interlayer dielectric layer is formed on the first surface; The first interlayer dielectric layer is etched until the surface of the first metal layer is exposed, forming a plug opening; A conductive material is filled into the plug opening to form a first conductive plug, and the first conductive plug is electrically connected to the first metal layer. A first pad is formed on the first conductive plug, and the first pad is electrically connected to the first conductive plug.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The steps for forming the second pad include: A second metal layer is formed on a first doped region on the first surface and on a portion of the substrate; A first interlayer dielectric layer is formed on the first surface; The first interlayer dielectric layer is etched until the surface of the second metal layer is exposed, forming a plug opening; A conductive material is filled into the plug opening to form a first conductive plug, and the first conductive plug is electrically connected to the second metal layer; A second pad is formed on the first conductive plug, and the second pad is electrically connected to the first conductive plug.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process for forming the first doped region is: a first ion implantation process. The process parameters of the first ion implantation process are: the dopant ions are P-type or N-type, and the doping energy ranges from 100 keV to 3000 keV.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, Also includes: A third pad is formed, which is electrically connected to the metal plug on the other side of the first doped region.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, The steps to form the third pad include: A third metal layer is formed on the metal plug on the other side of the first doped region on the first surface and on a portion of the substrate; A first interlayer dielectric layer is formed on the substrate; The first interlayer dielectric layer is etched until the surface of the third metal layer is exposed, forming a plug opening; A conductive material is filled into the plug opening to form a first conductive plug, and the first conductive plug is electrically connected to the third metal layer. A third pad is formed on the first conductive plug, and the third pad is electrically connected to the first conductive plug.

7. The method for forming a semiconductor structure as described in claim 5, characterized in that, The electrode polarity of the first pad is opposite to that of the second pad, and the electrode polarity of the first pad is opposite to that of the third pad.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, Prior to the step of forming the metal plug, the following steps are also included: A second ion implantation process is performed along the second surface into the connection region to form a second doped region; A second interlayer dielectric layer is formed on the second surface of the substrate; A conductive ring is formed within the second interlayer dielectric layer.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The process for forming the second doped region is a second ion implantation process. The process parameters for the second ion implantation process are: the dopant ions are P-type or N-type, and the doping energy ranges from 100 keV to 3000 keV.

10. The method for forming a semiconductor structure as described in claim 8, characterized in that, After the step of forming the conductive ring, the method further includes: A fourth metal layer is formed on the metal plug on the second surface, and the fourth metal layer is electrically connected to the metal plug on one side of the conductive ring. A fifth metal layer is formed on the metal plug and conductive ring on the second surface, the fifth metal layer being electrically connected to the metal plug and the conductive ring located on the other side of the conductive ring.

11. The method for forming a semiconductor structure as described in claim 8, characterized in that, The substrate further includes a device region; the semiconductor structure further includes a device structure located within the device region; the method of forming the device structure includes: Before the step of forming the second interlayer dielectric layer: A first implantation process is performed on the substrate within the device region of the second surface to form a well region; Injection is performed into the well region to form a source / drain region; A gate structure is formed between adjacent source / drain regions.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The step of forming the source / drain region is performed simultaneously with the step of forming the second doped region.

13. A semiconductor structure, characterized in that, include: A substrate, the substrate including a plurality of test areas and a connection area located between adjacent test areas, the substrate including opposing first and second surfaces; A metal plug is located within the test area and extends through the substrate. The metal plug includes a conductive layer and an insulating oxide layer located on the sidewall surface of the conductive layer. A first doped region is located within the connection region, and the first doped region is located on a first surface of the substrate; The first pad is located on the metal plug on one side of the first doped region, and the first pad is electrically connected to the metal plug on one side of the first doped region. The second pad is located on the first doped region and is electrically connected to the first doped region.

14. The semiconductor structure as described in claim 13, characterized in that, Also includes: The third pad is located on the metal plug on the other side of the first doped region, and the third pad is electrically connected to the metal plug on the other side of the first doped region.

15. The semiconductor structure as described in claim 14, characterized in that, The electrode polarity of the first pad is opposite to that of the second pad, and the electrode polarity of the first pad is opposite to that of the third pad.

16. The semiconductor structure as claimed in claim 14, characterized in that, Also includes: The first metal layer is located on the metal plug on the first surface and on a portion of the substrate; A second metal layer is located on the first doped region on the first surface and on a portion of the substrate; The third metal layer is located on the metal plug on the first surface and on a portion of the substrate; A first interlayer dielectric layer is located on the first surface; a first conductive plug is located within the first interlayer dielectric layer and is electrically connected to the first metal layer, the second metal layer and the third metal layer.

17. The semiconductor structure as claimed in claim 13, characterized in that, Also includes: The second doped region is located within the connection region and is located on the second surface of the substrate; The second interlayer dielectric layer is located on the second surface of the substrate; A conductive ring is located within the second interlayer dielectric layer.

18. The semiconductor structure as claimed in claim 17, characterized in that, Also includes: A fourth metal layer, a metal plug located on the second surface, the fourth metal layer being electrically connected to the metal plug on one side of the conductive ring; A fifth metal layer is located on the metal plug and conductive ring on the second surface, and the fifth metal layer is electrically connected to the metal plug and the conductive ring located on the other side of the conductive ring.

19. The semiconductor structure as claimed in claim 13, characterized in that, The substrate further includes a device region; the semiconductor structure further includes: a device structure located within the device region, the device structure including: a well region located within the substrate of the device region on the second surface; a source / drain region located within the well region; and a gate structure located between adjacent source / drain regions.

20. The semiconductor structure as claimed in claim 19, characterized in that, The device structure is a combination of one or more of transistors, memory cells, resistors, capacitors, and inductors.

21. A method for testing semiconductor structures, characterized in that, include: Electrically connect the first pad and the second pad to obtain a first test current; The test current is compared with a preset threshold to obtain a first test result. The first test result includes: when the first test current is greater than or equal to the preset threshold, there is a leakage path in the semiconductor structure and the leakage location is located on the metal plug sidewall in the substrate. When the first test current is less than the preset threshold, there is no leakage path within the semiconductor structure.

22. The test method as described in claim 21, characterized in that, Also includes: Electrically connect the first pad and the third pad to obtain the second test current; The second test current is compared with a preset threshold to obtain a comparison result. The comparison result includes: when the second test current is greater than or equal to the preset threshold, there is a leakage path in the semiconductor structure; when the first test current is less than the preset threshold, there is no leakage path in the semiconductor structure. Based on the comparison results and the first test results, a second test result is obtained.

23. The test method as described in claim 22, characterized in that, The method for obtaining the second test result based on the comparison result and the first test result includes: When the second test current is greater than or equal to the preset threshold and the first test current is less than the preset threshold, the leakage location is located on the metal plug sidewall within the second interlayer dielectric layer. When the second test current is greater than or equal to the preset threshold, the second test current is greater than the first test current, and the first test current is greater than or equal to the preset threshold, the leakage location is located on the metal plug sidewall in the second interlayer dielectric layer and the metal plug sidewall in the substrate.

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