A dual linear symmetric scanning high-voltage ramp signal generation circuit and method

Abstract

The application discloses a kind of double linear symmetry scanning high-voltage ramp signal generation circuit and method, solve existing double symmetry ramp signal generation method circuit structure complex, cannot be applied in high-precision under wide time window etc. The power supply module in the circuit is connected with the input end of drive chip;Drive chip one of output ends is used to generate falling edge pulse signal and access high-voltage positive slope generator;Another output end is used to generate rising edge pulse signal and access high-voltage reverse slope generator;Linear symmetry of falling edge pulse signal and rising edge pulse signal and polarity is opposite;High-voltage power supply chip provides positive high voltage and negative high voltage for high-voltage positive slope generator and high-voltage reverse slope generator respectively;High-voltage positive slope generator and high-voltage reverse slope generator are used to generate double linear symmetry scanning high-voltage ramp signal.The circuit structure is simple, both improve the integration of circuit, and widen the adjustment range of scanning time.

Description

Technical Field

[0001] This invention relates to a method for generating high-voltage ramp deflection signals in a stripe camera scanning circuit, and more particularly to a MOSFET-based bilinear symmetrical scanning high-voltage ramp signal generation circuit and method. Background Technology

[0002] A streak camera is an ultrafast diagnostic instrument based on a streak tube and possessing high spatiotemporal resolution. It mainly consists of a streak tube, a relay lens, a camera, and a scanning control module. The core of the scanning control module is the scanning circuit, whose primary function is to apply a high-voltage ramp deflection signal to the scanning plate to achieve electrical signal scanning and spatiotemporal conversion. The scanning circuit can be divided into single-scan and synchronous repetitive-scan modes according to its operating mode. Single-scan uses a single ramp voltage signal, and the commonly used circuits for microsecond-range dynamic imaging are generally single-scan circuits; while synchronous repetitive-scan uses a high-frequency sinusoidal signal.

[0003] Currently, there are many methods for generating single-slope voltage signals. Among them, the invention patent with publication number CN118282359A discloses a linear high-voltage slope signal generation circuit and signal generation method. The proposed switching constant current method high-voltage slope signal generation circuit has the advantages of simple circuit structure, easy debugging, high generated voltage, and better linearity. However, when applied to dynamic scanning imaging with a long slit stripe camera, it easily leads to a decrease in image quality at the imaging edge. The reason for this is that when using a single-slope signal, one deflector plate is connected to the ground, and the other deflector plate is connected to the slope generator. Although the electric field in the vertical direction does not change compared to the dual-slope generator, the potential between the two deflector plates (the sum of the potentials of the two scanning plates) has changed. When using a single-slope signal, the potential is not constant, which causes a focusing problem, making the stripes on the fluorescent screen (positions with non-zero potential) blurry, thus affecting the imaging quality at the edge.

[0004] Compared to a single-path ramp, a dual-symmetric ramp provides a completely symmetrical ramp scanning signal, maintains a constant potential between the parallel deflector plates, and reduces the need for high voltage, thus simplifying the design. This is because a single-path ramp scanning voltage applied to one deflector plate while the other is grounded requires a ramp scanning voltage that linearly varies from -2V0 to 2V0, necessitating a high voltage of 2V0. However, with a dual-symmetric ramp, the voltage varies between the two deflector plates, one varying from -V0 to V0 and the other from V0 to -V0. The voltage difference between the two plates remains between -2V0 and 2V0, but the required high voltage is reduced to V0. Therefore, in circuit design, only one dual-linear symmetric ramp circuit needs to be generated, varying from -V0 to V0 and from V0 to -V0, to achieve the desired result. Thus, with a dual-symmetric ramp, the potential remains constant (maintaining 0 potential) at any given time. This method not only improves imaging edge resolution but also reduces the voltage and design complexity of a single-path scanning circuit.

[0005] Existing dual-symmetric ramp signal generation schemes are mainly divided into two categories: direct high-voltage generation and high-voltage symmetric ramp signal generation. Direct high-voltage generation utilizes circuits to directly generate two high-voltage symmetric ramp signals. Typical structures include avalanche transistor cascaded discharge structures, RLC high-voltage control structures, and high-voltage MOSFET switching constant current source structures. The avalanche transistor cascaded discharge structure generates high-voltage pulses through the rapid discharge of multiple stages of avalanche transistors, offering advantages such as short rise time and large output swing, making it suitable for high-speed scanning. However, its discharge process exhibits significant nonlinearity, resulting in poor ramp linearity, and the multi-stage cascading leads to circuit complexity, large jitter, and poor repeatability. The RLC high-voltage control structure uses an RLC resonant network to achieve voltage shaping, offering high linearity and good stability. However, it requires precise calculation of component parameters using external simulation software, making debugging difficult and reducing flexibility. The high-voltage MOSFET switching constant current source structure utilizes a constant current source to linearly charge and discharge a capacitor, combined with high-voltage MOSFET switching control, offering advantages such as high linearity, good repeatability, and circuit simplicity. The second method involves low-voltage generation followed by high-voltage amplification. A dedicated chip first generates a low-voltage symmetrical ramp signal, which is then boosted to the desired level by a high-voltage amplifier. This method offers high flexibility, but is limited by the bandwidth of the high-voltage amplifier, resulting in a rise time typically greater than 10 ns. As early as 1994, RJ ​​Bakert and BP Johnson published a research paper titled "Sweep circuit design for a picosecond streak camera" in Measurement Science and Technology (IOPScience), proposing the use of a multi-capacitor voltage divider network and a MOSFET pair structure to generate a symmetrical ramp signal, achieving a 2kV swing bipolar scanning voltage. This method effectively extended the scanning time, providing a preliminary solution to the deflection de-aggregation problem. However, its circuit structure is complex, with a large number of components, and the generated signal exhibits significant nonlinearity: nonlinearity is <2% at a scanning time of 4 ns, but deteriorates to 10% when the scanning time is extended to 300 ns, thus limiting its high-precision application over a wide time window.

[0006] Therefore, there is an urgent need for a simple and highly linear bilinear symmetrical scanning high-voltage ramp signal generation circuit to solve the above problems. Summary of the Invention

[0007] The purpose of this invention is to solve the technical problems of blurry imaging edges in existing single-scan ramp circuits and complex circuit structures in dual-symmetric ramp signal generation methods, which cannot be applied with high precision over a wide time window. The invention provides a dual-linear symmetric scanning high-voltage ramp signal generation circuit and method.

[0008] To achieve the above objectives, the technical solution provided by this invention is as follows:

[0009] A bilinear symmetrical scanning high-voltage ramp signal generation circuit, characterized by the following features:

[0010] Includes driver chip, high voltage forward ramp generator, high voltage reverse ramp generator, power supply module and high voltage power chip;

[0011] The power supply module is connected to the input terminal of the driver chip to provide it with input voltage;

[0012] The driver chip has two output terminals. One output terminal is connected to a high-voltage forward ramp generator to generate a falling edge pulse signal and input it to the high-voltage forward ramp generator. The other output terminal is connected to a high-voltage reverse ramp generator to generate a rising edge pulse signal and input it to the high-voltage reverse ramp generator. The falling edge pulse signal and the rising edge pulse signal are linearly symmetrical and have opposite polarities.

[0013] The high-voltage power chip is connected to the input terminals of the high-voltage forward ramp generator and the high-voltage reverse ramp generator respectively, providing them with positive high voltage and negative high voltage respectively, and the positive high voltage and negative high voltage are equal in value and opposite in direction;

[0014] The output terminals of the high-voltage forward ramp generator and the high-voltage reverse ramp generator are respectively used to connect to the upper and lower plates of the striped tube deflection plate to generate a bilinear symmetrical scanning high-voltage ramp signal.

[0015] Furthermore, the high-voltage forward ramp generator includes an NMOS transistor Q1, a first isolation resistor R1, a first energy storage capacitor C1, a first linear regulator Rp1, a first equivalent capacitor C2, and a first adjustable constant current source.

[0016] The gate of the NMOS transistor Q1 is connected to one of the output terminals of the driver chip A to receive the falling edge pulse signal; the drain of the NMOS transistor Q1 is connected to one end of the first energy storage capacitor C1, the other end of the first energy storage capacitor C1 is connected to one end of the first linear regulator Rp1, the other end of the first linear regulator Rp1 is connected to one end of the first equivalent capacitor C2, and this connection point is connected to the upper plate of the stripe tube deflection plate as an output terminal; the other end of the first equivalent capacitor C2 is grounded.

[0017] The drain of the NMOS transistor Q1 is connected to the high-voltage power supply chip through the first isolation resistor R1 to receive the positive high voltage.

[0018] The first adjustable constant current source serves as a scan time regulator, with one end connected to the source of the NMOS transistor Q1 and the other end grounded.

[0019] Furthermore, the high-voltage reverse ramp generator B- includes a PMOS transistor Q2, a second isolation resistor R2, a second energy storage capacitor C3, a second linear regulator Rp2, a second equivalent capacitor C4, and a second adjustable constant current source;

[0020] The gate of the PMOS transistor Q2 is connected to another output terminal of the driver chip A to receive the rising edge pulse signal; the source of the PMOS transistor Q2 is connected to one end of the second energy storage capacitor C3, the other end of the second energy storage capacitor C3 is connected to one end of the second linear regulator Rp2, the other end of the second linear regulator Rp2 is connected to one end of the second equivalent capacitor C4, and this connection point is connected to the lower plate of the stripe tube deflection plate as an output terminal, and the other end of the second equivalent capacitor C4 is grounded;

[0021] The source of the PMOS transistor Q2 is connected to the high-voltage power supply chip through the second isolation resistor R2 to receive negative high voltage.

[0022] The second adjustable constant current source serves as a scan time regulator, with one end connected to the drain of the PMOS transistor Q2 and the other end grounded.

[0023] Furthermore, both the first linear regulator Rp1 and the second linear regulator Rp2 are adjustable resistors with the same structure, used to achieve linear adjustment of the ramp signal.

[0024] Furthermore, the NMOS transistor Q1 and PMOS transistor Q2 are a pair;

[0025] The first isolation resistor R1 and the second isolation resistor R2 have the same resistance value;

[0026] The first energy storage capacitor C1 and the second energy storage capacitor C3 have the same capacitance value.

[0027] The first equivalent capacitor C2 and the second equivalent capacitor C4 have the same capacitance value.

[0028] This invention also provides a method for generating a bilinear symmetric scanning high-voltage ramp signal, comprising the following steps:

[0029] Step 1: Construct the above-mentioned bilinear symmetrical scanning high-voltage ramp signal generation circuit;

[0030] Step 2: The power supply module provides an input voltage Vin to the driver chip, which in turn generates falling edge pulse signals and rising edge pulse signals, which are then connected to a high-voltage forward ramp generator and a high-voltage reverse ramp generator, respectively. The falling edge pulse signals and rising edge pulse signals are linearly symmetrical and have opposite polarities.

[0031] Meanwhile, the high-voltage power chip provides positive and negative high voltage to the high-voltage positive ramp generator and the high-voltage reverse ramp generator, respectively; the positive and negative high voltage values ​​are equal and opposite in direction;

[0032] Step 3: The high-voltage forward ramp generator generates a descending high-voltage ramp signal on the upper plate of the striped tube deflection plate, while the high-voltage reverse ramp generator generates an ascending high-voltage ramp signal on the lower plate of the striped tube deflection plate, ultimately forming a bilinear symmetrical scanning high-voltage ramp signal.

[0033] Furthermore, step 3 specifically involves:

[0034] After receiving a positive high voltage, the high-voltage forward ramp generator charges the first energy storage capacitor C1; after receiving a falling edge pulse signal, the NMOS transistor Q1 turns on and forms a charging and discharging circuit with the first energy storage capacitor C1, the first linear regulator Rp1, the first equivalent capacitor C2 and the first adjustable constant current source, thereby discharging the first energy storage capacitor C1 and charging the first equivalent capacitor C2 to form a falling high-voltage ramp signal Vout1.

[0035] Simultaneously, after receiving the negative high voltage -HV, the high-voltage reverse ramp generator B- charges the second energy storage capacitor C3; after receiving the rising edge pulse signal, the PMOS transistor Q2 turns on and forms a charging and discharging circuit with the second energy storage capacitor C3, the second linear regulator Rp2, the second equivalent capacitor C4 and the second adjustable constant current source, thereby discharging the second energy storage capacitor C3, charging the second equivalent capacitor C4 and forming a rising high-voltage ramp signal Vout2, and finally forming a bilinear symmetrical scanning high-voltage ramp signal.

[0036] Furthermore, it also includes step 4, where oscilloscope probes are connected to the output terminals of the descending high-voltage ramp signal Vout1 and the ascending high-voltage ramp signal Vout2, respectively. The voltage waveform of the bilinear symmetrical scanning high-voltage ramp signal is optimized by adjusting the first linear regulator Rp1 and the second linear regulator Rp2, thereby achieving adjustment of voltage shape symmetry, voltage value symmetry and linear symmetry.

[0037] Furthermore, in step 3, the retrace time of the corresponding deflection plate is controlled by controlling the discharge time of the first energy storage capacitor C1 and the second energy storage capacitor C3.

[0038] The rise time and fall time of the ramp signal are controlled by the first and second adjustable constant current sources.

[0039] The beneficial effects of this invention are as follows:

[0040] 1. The present invention provides a dual linear symmetrical scanning high voltage ramp signal generation circuit, which, compared with the existing dual symmetrical ramp signal generation circuit, has a simple structure and high linearity, which not only improves the circuit integration but also widens the scanning time adjustment range, effectively improving the reliability and safety of the system.

[0041] 2. The present invention provides a dual linear symmetrical scanning high-voltage ramp signal generation circuit, which employs a high-voltage forward ramp generator and a high-voltage reverse ramp generator. The NMOS transistor and PMOS transistor are a pair of transistors, which can realize two ramp signal outputs with opposite polarities, ensuring that the sum of the potentials between the two deflection plates remains constant, and significantly improving the edge resolution of the stripe image.

[0042] 3. The present invention provides a bilinear symmetrical scanning high-voltage ramp signal generation circuit, which, compared with the traditional single-ended drive, only requires half the voltage swing of each channel to achieve an equivalent deflection electric field, significantly reducing the design difficulty of a single-channel high-voltage module.

[0043] 4. The bilinear symmetrical scanning high-voltage ramp signal generated by this invention can ensure that the potential between the parallel deflection plates remains constant at any given time, which can effectively improve the spatial resolution of the image edge position. Attached Figure Description

[0044] Figure 1 This is a schematic diagram of the bilinear symmetrical scanning high-voltage ramp signal (left) and the synthesized signal (right) in an embodiment of the bilinear symmetrical scanning high-voltage ramp signal generation circuit of the present invention.

[0045] Figure 2 This is a circuit structure diagram of an embodiment of a bilinear symmetrical scanning high-voltage ramp signal generation circuit of the present invention.

[0046] The attached figures are labeled as follows:

[0047] A, Driver chip; B+, High-voltage forward ramp generator; B-, High-voltage reverse ramp generator; Q1, NMOS transistor; R1, First isolation resistor; C1, First energy storage capacitor; Rp1, First linear regulator; C2, First equivalent capacitor; Q2, PMOS transistor; R2, Second isolation resistor; C3, Second energy storage capacitor; Rp2, Second linear regulator; C4, Second equivalent capacitor. Detailed Implementation

[0048] To make the objectives, advantages, and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Those skilled in the art should understand that these embodiments are merely used to explain the technical principles of the present invention and are not intended to limit the scope of protection of the present invention.

[0049] Combination Figure 1 and Figure 2 As shown, this embodiment provides a dual-linear symmetrical scanning high-voltage ramp signal generation circuit, including a driver chip A, a high-voltage forward ramp generator B+, a high-voltage reverse ramp generator B-, a power supply module, and a high-voltage power supply chip.

[0050] The power supply module is connected to the input terminal of the driver chip A to provide it with the input voltage Vin.

[0051] The driver chip A has two output terminals. One output terminal is connected to the high-voltage forward ramp generator B+ to generate a falling edge pulse signal and connect it to the high-voltage forward ramp generator B+. The other output terminal is connected to the high-voltage reverse ramp generator B- to generate a rising edge pulse signal and connect it to the high-voltage reverse ramp generator B-. The falling edge pulse signal and the rising edge pulse signal are linearly symmetrical and have opposite polarities.

[0052] The high-voltage power supply chip is connected to the input terminals of the high-voltage positive ramp generator B+ and the high-voltage reverse ramp generator B- respectively, providing them with positive high voltage +HV and negative high voltage -HV respectively, and the values ​​of positive high voltage +HV and negative high voltage -HV are equal but opposite in direction.

[0053] The output terminals of the high-voltage forward ramp generator B+ and the high-voltage reverse ramp generator B- are used to connect to the upper and lower plates of the stripe tube deflection plate, respectively, to generate a bilinear symmetrical scanning high-voltage ramp signal.

[0054] like Figure 2 As shown, the high-voltage forward ramp generator B+ in this embodiment includes an NMOS transistor Q1, a first isolation resistor R1, a first energy storage capacitor C1, a first linear regulator Rp1, a first equivalent capacitor C2, and a first adjustable constant current source.

[0055] The gate of NMOS transistor Q1 is connected to one of the output terminals of driver chip A to receive a falling edge pulse signal. The drain of NMOS transistor Q1 is connected to one end of the first energy storage capacitor C1, the other end of the first energy storage capacitor C1 is connected to one end of the first linear regulator Rp1, the other end of the first linear regulator Rp1 is connected to one end of the first equivalent capacitor C2, and this connection point serves as an output terminal connected to the upper plate of the stripe tube deflection plate. The other end of the first equivalent capacitor C2 is grounded. The drain of NMOS transistor Q1 is connected to the high-voltage power supply chip through the first isolation resistor R1 to receive the positive high voltage +HV. The first adjustable constant current source serves as a scan time regulator, with one end connected to the source of NMOS transistor Q1 and the other end grounded.

[0056] The high-voltage reverse ramp generator B in this embodiment includes a PMOS transistor Q2, a second isolation resistor R2, a second energy storage capacitor C3, a second linear regulator Rp2, a second equivalent capacitor C4, and a second adjustable constant current source.

[0057] The gate of PMOS transistor Q2 is connected to another output terminal of driver chip A to receive the rising edge pulse signal. The source of PMOS transistor Q2 is connected to one end of the second energy storage capacitor C3, the other end of the second energy storage capacitor C3 is connected to one end of the second linear regulator Rp2, the other end of the second linear regulator Rp2 is connected to one end of the second equivalent capacitor C4, and this connection point serves as the output terminal connected to the lower plate of the stripe tube deflection plate. The other end of the second equivalent capacitor C4 is grounded. The source of PMOS transistor Q2 is connected to the high-voltage power supply chip through the second isolation resistor R2 to receive the negative high voltage -HV. The second adjustable constant current source serves as a scan time regulator, with one end connected to the drain of PMOS transistor Q2 and the other end grounded.

[0058] In this embodiment, both the first linear regulator Rp1 and the second linear regulator Rp2 are adjustable resistors with the same structure, used to achieve linear adjustment of the ramp signal.

[0059] To ensure high symmetry of the output signal, NMOS transistor Q1 and PMOS transistor Q2 are paired transistors with matched parameters; at the same time, the first isolation resistor R1 and the second isolation resistor R2 have the same resistance value; the first energy storage capacitor C1 and the second energy storage capacitor C3 have the same capacitance value; and the first equivalent capacitor C2 and the second equivalent capacitor C4 have the same capacitance value.

[0060] The principle of this invention is to use two symmetrical but oppositely polarized ramp voltages to achieve a scanning circuit with a constant average potential between two deflection plates. Specifically, it uses driver chip A to generate two symmetrical but oppositely polarized drive pulse signals, uses the capacitor discharge of two high-voltage ramp generators to generate two high-voltage ramp signals, uses two adjustable resistors as linear regulators to adjust and optimize the linearity of the two high-voltage ramp signals, uses an adjustable constant current source as a scan time regulator to control the falling / rising edge of the ramp signal, and uses an equivalent capacitor as a retrace time controller to control and adjust the scan time. The scan time in this embodiment can be adjusted from nanoseconds to microseconds, thereby achieving high-precision applications within a wide time window.

[0061] Meanwhile, this embodiment also provides a method for generating a bilinear symmetric scanning high-voltage ramp signal, including the following steps:

[0062] Step 1: Construct the above-mentioned bilinear symmetrical scanning high-voltage ramp signal generation circuit.

[0063] Step 2: The power supply module provides an input voltage Vin to the driver chip A, which causes the driver chip A to generate falling edge pulse signals and rising edge pulse signals, respectively, and connects them to the high-voltage forward ramp generator B+ and the high-voltage reverse ramp generator B-, respectively; In this embodiment, the falling edge pulse signals and rising edge pulse signals are linearly symmetrical and have opposite polarities.

[0064] Meanwhile, the high-voltage power chip provides positive high voltage +HV and negative high voltage -HV to the high-voltage positive ramp generator B+ and the high-voltage reverse ramp generator B-, respectively; the positive high voltage +HV and the negative high voltage -HV have equal values ​​and opposite directions.

[0065] Step 3: After receiving the positive high voltage +HV, the high-voltage forward ramp generator B+ charges the first energy storage capacitor C1 through the first isolation resistor R1. Simultaneously, the NMOS transistor Q1 turns on upon receiving the falling edge pulse signal, forming a charging / discharging circuit with the first energy storage capacitor C1, the first linear regulator Rp1, the first equivalent capacitor C2, and the first adjustable constant current source. This discharges the first energy storage capacitor C1, charging the first equivalent capacitor C2 and generating a falling high-voltage ramp signal Vout1. During this process, the first linear regulator Rp1 adjusts the linearity of the high-voltage ramp signal; the first adjustable constant current source controls the falling edge time of the high-voltage ramp signal; the discharge time of the first energy storage capacitor C1 controls the retrace time of the deflection plate; and the discharge time of the first equivalent capacitor C2 allows for selection of the scan time.

[0066] After receiving the negative high voltage -HV, the high-voltage reverse ramp generator B- charges the second energy storage capacitor C3 through the second isolation resistor R2. Simultaneously, the PMOS transistor Q2 turns on upon receiving the rising edge pulse signal, forming a charging and discharging circuit with the second energy storage capacitor C3, the second linear regulator Rp2, the second equivalent capacitor C4, and the second adjustable constant current source. This discharges the second energy storage capacitor C3, charging the second equivalent capacitor C4 and generating a rising high-voltage ramp signal Vout2. During this process, the second linear regulator Rp2 adjusts the linearity of the high-voltage ramp signal; the second adjustable constant current source controls the rise time of the high-voltage ramp signal; the discharge time of the second energy storage capacitor C3 controls the retrace time of the lower deflection plate; and the discharge time of the second equivalent capacitor C4 allows for selection of the scan time.

[0067] The descending high-pressure ramp signal Vout1 and the ascending high-pressure ramp signal Vout2 together form a bilinear symmetrical scanning high-pressure ramp signal Vout.

[0068] Step 4: Connect oscilloscope probes to the output terminals of the descending high-voltage ramp signal Vout1 and the ascending high-voltage ramp signal Vout2, respectively. Optimize the voltage waveform of the bilinear symmetrical scanning high-voltage ramp signal by adjusting the first linear regulator Rp1 and the second linear regulator Rp2, thereby achieving adjustment of voltage shape symmetry, voltage value symmetry, and linear symmetry.

[0069] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein, and such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the present invention.

Claims

1. A bilinear symmetrical scanning high-voltage ramp signal generation circuit, characterized in that: Includes a driver chip (A), a high-voltage forward ramp generator (B+), a high-voltage reverse ramp generator (B-), a power supply module, and a high-voltage power supply chip; The power supply module is connected to the input terminal of the driver chip (A) to provide it with input voltage; The driver chip (A) has two output terminals. One output terminal is connected to a high-voltage forward ramp generator (B+) to generate a falling edge pulse signal and input it to the high-voltage forward ramp generator (B+). The other output terminal is connected to a high-voltage reverse ramp generator (B-) to generate a rising edge pulse signal and input it to the high-voltage reverse ramp generator (B-). The falling edge pulse signal and the rising edge pulse signal are linearly symmetrical and have opposite polarities. The high-voltage power chip is connected to the input terminals of the high-voltage positive ramp generator (B+) and the high-voltage reverse ramp generator (B-) respectively, providing them with positive high voltage and negative high voltage respectively, and the positive high voltage and negative high voltage have equal values ​​and opposite directions; The output terminals of the high-voltage forward ramp generator (B+) and the high-voltage reverse ramp generator (B-) are respectively used to connect the upper and lower plates of the stripe tube deflection plate to generate a bilinear symmetrical scanning high-voltage ramp signal.

2. The bilinear symmetrical scanning high-voltage ramp signal generation circuit according to claim 1, characterized in that: The high-voltage forward ramp generator (B+) includes an NMOS transistor Q1, a first isolation resistor R1, a first energy storage capacitor C1, a first linear regulator Rp1, a first equivalent capacitor C2, and a first adjustable constant current source. The gate of the NMOS transistor Q1 is connected to one of the output terminals of the driver chip (A) to receive the falling edge pulse signal; the drain of the NMOS transistor Q1 is connected to one end of the first energy storage capacitor C1, the other end of the first energy storage capacitor C1 is connected to one end of the first linear regulator Rp1, the other end of the first linear regulator Rp1 is connected to one end of the first equivalent capacitor C2, and this connection point is connected to the upper plate of the stripe tube deflection plate as an output terminal; the other end of the first equivalent capacitor C2 is grounded. The drain of the NMOS transistor Q1 is connected to the high-voltage power supply chip through the first isolation resistor R1 to receive the positive high voltage. The first adjustable constant current source serves as a scan time regulator, with one end connected to the source of the NMOS transistor Q1 and the other end grounded.

3. The bilinear symmetrical scanning high-voltage ramp signal generation circuit according to claim 2, characterized in that: The high-voltage reverse ramp generator (B-) includes a PMOS transistor Q2, a second isolation resistor R2, a second energy storage capacitor C3, a second linear regulator Rp2, a second equivalent capacitor C4, and a second adjustable constant current source. The gate of the PMOS transistor Q2 is connected to another output terminal of the driver chip (A) to receive the rising edge pulse signal; the source of the PMOS transistor Q2 is connected to one end of the second energy storage capacitor C3, the other end of the second energy storage capacitor C3 is connected to one end of the second linear regulator Rp2, the other end of the second linear regulator Rp2 is connected to one end of the second equivalent capacitor C4, and this connection point is connected to the lower plate of the stripe tube deflection plate as an output terminal, and the other end of the second equivalent capacitor C4 is grounded; The source of the PMOS transistor Q2 is connected to the high-voltage power supply chip through the second isolation resistor R2 to receive negative high voltage. The second adjustable constant current source serves as a scan time regulator, with one end connected to the drain of the PMOS transistor Q2 and the other end grounded.

4. The bilinear symmetrical scanning high-voltage ramp signal generation circuit according to claim 3, characterized in that: The first linear regulator Rp1 and the second linear regulator Rp2 are both adjustable resistors with the same structure, used to achieve linear adjustment of the ramp signal.

5. The bilinear symmetrical scanning high-voltage ramp signal generation circuit according to claim 4, characterized in that: The NMOS transistor Q1 and PMOS transistor Q2 are a pair; The first isolation resistor R1 and the second isolation resistor R2 have the same resistance value; The first energy storage capacitor C1 and the second energy storage capacitor C3 have the same capacitance value. The first equivalent capacitor C2 and the second equivalent capacitor C4 have the same capacitance value.

6. A method for generating a bilinear symmetric scanning high-voltage ramp signal, characterized in that, Includes the following steps: Step 1: Construct the bilinear symmetric scanning high-voltage ramp signal generation circuit as described in any one of claims 1 to 5; Step 2: The power supply module provides an input voltage Vin to the driver chip (A), which causes the driver chip (A) to generate falling edge pulse signals and rising edge pulse signals, respectively, and connects them to the high-voltage forward ramp generator (B+) and the high-voltage reverse ramp generator (B-), respectively; the falling edge pulse signals and rising edge pulse signals are linearly symmetrical and have opposite polarities; Meanwhile, the high-voltage power chip provides positive high voltage +HV and negative high voltage -HV to the high-voltage positive ramp generator (B+) and the high-voltage reverse ramp generator (B-), respectively; the positive high voltage +HV and the negative high voltage -HV have equal values ​​but opposite directions; Step 3: The high-voltage forward ramp generator (B+) generates a descending high-voltage ramp signal on the upper plate of the striped tube deflection plate, while the high-voltage reverse ramp generator (B-) generates a ascending high-voltage ramp signal on the lower plate of the striped tube deflection plate, ultimately forming a bilinear symmetrical scanning high-voltage ramp signal.

7. The method for generating a bilinear symmetric scanning high-voltage ramp signal according to claim 6, characterized in that, Step 3 specifically involves: After receiving the positive high voltage +HV, the high voltage forward ramp generator (B+) charges the first energy storage capacitor C1; after receiving the falling edge pulse signal, the NMOS transistor Q1 turns on and forms a charging and discharging circuit with the first energy storage capacitor C1, the first linear regulator Rp1, the first equivalent capacitor C2 and the first adjustable constant current source, thereby discharging the first energy storage capacitor C1 and charging the first equivalent capacitor C2 to form a falling high voltage ramp signal Vout1; Simultaneously, after receiving the negative high voltage -HV, the high voltage reverse ramp generator (B-) charges the second energy storage capacitor C3; after receiving the rising edge pulse signal, the PMOS transistor Q2 turns on and forms a charging and discharging circuit with the second energy storage capacitor C3, the second linear regulator Rp2, the second equivalent capacitor C4 and the second adjustable constant current source, thereby discharging the second energy storage capacitor C3, charging the second equivalent capacitor C4 and forming a rising high voltage ramp signal Vout2, and finally forming a bilinear symmetrical scanning high voltage ramp signal.

8. The method for generating a bilinear symmetric scanning high-voltage ramp signal according to claim 6, characterized in that: The method also includes step 4, where oscilloscope probes are connected to the output terminals of the descending high-voltage ramp signal Vout1 and the ascending high-voltage ramp signal Vout2, respectively. The voltage waveform of the bilinear symmetrical scanning high-voltage ramp signal is optimized by adjusting the first linear regulator Rp1 and the second linear regulator Rp2, thereby achieving adjustment of voltage shape symmetry, voltage value symmetry and linear symmetry.

9. The method for generating a bilinear symmetric scanning high-voltage ramp signal according to claim 6, characterized in that: In step 3, the retrace time of the corresponding deflection plate is controlled by controlling the discharge time of the first energy storage capacitor C1 and the second energy storage capacitor C3. The rise time and fall time of the ramp signal are controlled by the first and second adjustable constant current sources.

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