Output compression and search method and system for time-to-digital converter of high-speed interface chip

Abstract

The application provides an output compression and search method and system for a time-to-digital converter of a high-speed interface chip, and belongs to the technical field of chip detection. The method comprises the following steps: acquiring N paths of delay signals respectively output by N levels of time delays of the TDC; selecting a plurality of working modes of a multiplexer array through a selection signal configuration to map part of the delay signals to M output ends for output; under a current working mode, judging whether a signal jump is detected according to a current sampling result output, and if not, adjusting a delay amount of a programmable delay line to move a sampling window until the signal jump is detected or a stop condition is met; if the signal jump is detected, switching the working mode according to a detection region where the signal jump is located to narrow a search range; and until the position of the signal jump in the adjacent level of time delay is located. The application realizes output resource compression, hardware cost reduction and self-adaptation and compatibility while maintaining the original time resolution.

Description

Technical Field

[0001] This invention relates to the technical field of chip testing, and in particular to an output compression and search method and system for a time-to-digital converter for a high-speed interface chip. Background Technology

[0002] In high-speed interface chips, the timing relationship between input data and a reference clock needs to be calibrated. A time-to-digital converter (TDC) is typically used to detect the time difference between the input data and the reference clock to perform timing calibration functions such as timing search.

[0003] The commonly used Time-of-Depth (TDC) is a multi-stage delay chain structure. Taking a single channel under test as an example, this channel is configured with a 16-stage TDC: 16 delay units are connected in series, each stage corresponding to a fixed time resolution (approximately 25 ps in 28nm process technology). The input signal propagates step by step along the delay chain, and the reference clock samples the signal at each delay node. Each stage generates 1 bit of sampling result, and the sampling results of 16 stages constitute 16 bits of TDC sampling data, covering a timing search range of approximately 400 ps. The subsequent digital logic determines the adjacent stage where the signal transition occurs by detecting the boundary between 0 and 1 in the sampled data, thereby completing the timing localization.

[0004] However, in the above structure, each Stage corresponds to one output. Traditional solutions require a 16-bit output bus to simultaneously output 16 bits of TDC sampling data to digital logic, along with corresponding output registers, read logic, and routing resources. When the interface chip contains multiple channels under test, each channel needs to be independently configured with the aforementioned output bus and register resources. The output resource overhead increases exponentially with the number of channels, significantly increasing chip area, routing complexity, and power consumption. Reducing the number of TDC stages to lower output overhead would reduce time resolution or shrink the available timing search range, failing to meet the timing detection requirements of high-speed interfaces.

[0005] Therefore, how to reduce the number of TDC outputs, reduce hardware resource overhead such as output bus, registers and wiring, and ensure that timing detection capability is not affected while maintaining the time resolution and timing search range of TDC are unchanged is a technical problem that urgently needs to be solved in this field.

[0006] In view of this, an output compression and search method and system for time-to-digital converters of high-speed interface chips are proposed to solve all or part of the above problems. Summary of the Invention

[0007] To address at least one aspect of the above problems and drawbacks existing in the prior art, embodiments of the present invention provide an output compression and search method and system for a time-to-digital converter of a high-speed interface chip. N stages of delay signals are dynamically mapped to M (M<N) output terminals by selecting a multiplexer array. The search process is divided into two stages: a coarse search stage and a fine search stage. In the coarse search stage, the sampling window is scanned by sequentially cooperating an even mode and an odd mode. If no signal transition is detected, the sampling window is moved through a programmable delay line. If a signal transition is detected, the mode is switched to a first mode, a second mode or the odd mode according to the region where the transition is located to narrow the search range, and the search is repeated until the adjacent stage delay position where the signal transition is located is located. The present invention achieves output resource compression on the premise of maintaining the time resolution of the TDC, and reduces hardware overhead. The technical solution is as follows:

[0008] According to one aspect of the present invention, an output compression and search method for a time-to-digital converter of a high-speed interface chip is provided. The output compression and search method comprises:

[0009] Step S110: acquiring N paths of delay signals respectively output by N stages of delay of the time-to-digital converter, where N is a positive integer;

[0010] Step S120: configuring multiple working modes of the multiplexer array via a selection signal, so as to map part of the delay signals in the N paths of delay signals to M output terminals for output, where M is a positive integer less than N, the delay groups corresponding to the delay signals mapped to the M output terminals by the multiplexer array in different working modes are different, and at any moment, the multiplexer array selects only one of the working modes;

[0011] Step S130: under the current working mode, judging whether a signal transition is detected according to the current sampling results output by the M output terminals,

[0012] if no signal transition is detected, adjusting the delay amount of the programmable delay line to move the sampling window, and repeating steps S110 to S130 until a signal transition is detected or a stop condition is satisfied;

[0013] if a signal transition is detected, switching the working mode of the multiplexer array according to the detection region where the signal transition is located, to narrow the search range;

[0014] Step S140: repeatedly performing step S130 or the step of switching the working mode, until the adjacent stage delay position where the signal transition is located in the N stages of delay of the time-to-digital converter is located.

[0015] According to another aspect of the present invention, an output compression and search system for a time-to-digital converter of a high-speed interface chip is provided. The output compression and search system includes:

[0016] A time-to-digital converter, comprising N stages of delay, each of which outputs N delayed signals;

[0017] The multiplexer array is connected between the output of the time-to-digital converter and the digital logic. The multiplexer array has M outputs and is configured with multiple operating modes. According to the selection signal, a portion of the delay signals from N delay signals are mapped to the M outputs, where M is a positive integer less than N. The delay level grouping corresponding to the delay signals mapped to the M outputs by the multiplexer array is different in different operating modes. At any given time, the multiplexer array selects only one of the operating modes.

[0018] A programmable delay line, connected to the input of a time-to-digital converter, is configured to adjust the delay of the input signal according to a delay control signal to move the sampling window;

[0019] The search control module is connected to the control terminals of the selection multiplexer array and the programmable delay line, respectively. It is configured to output selection signals to configure the operating mode of the selection multiplexer array, and in the current operating mode, to determine whether a signal transition has been detected based on the current sampling results output from the M output terminals.

[0020] If the search control module does not detect a signal transition, it outputs a delay control signal to the programmable delay line to move the sampling window.

[0021] If the search control module detects a signal transition, it switches the operating mode of the multiplexer array according to the detection area where the signal transition occurs, in order to narrow the search range.

[0022] The search control module repeatedly detects until it locates the position of the signal transition in the adjacent delay stage of the N-stage delay of the time-to-digital converter.

[0023] The output compression and search method and system for a time-to-digital converter for a high-speed interface chip provided by embodiments of the present invention have at least one or a portion of the following advantages:

[0024] (1) By selecting the multiplexer array, the N-level delayed output N-channel delayed signals are dynamically mapped to M output terminals (M<N). Combined with signal transition detection and programmable delay line moving sampling window, the output resource compression and complete timing positioning are unified while keeping the TDC time resolution unchanged.

[0025] (2) By defining four working modes, namely the first mode, the second mode, the even mode and the odd mode, a delay-level grouping method that complements the overall time series region is provided for the coarse-fine two-stage search, ensuring that all N-level delay time series information can still be covered under the condition of fixed M output terminals.

[0026] (3) In even or odd mode, the signal transition is determined by detecting whether there is a continuous boundary between 0 and 1 in the sampling results of M output terminals, and the adjacent delay interval where the transition is located is determined according to the boundary position, thus realizing the rapid area positioning in the coarse search stage.

[0027] (4) Based on whether the signal transition is in the first or second half of the region, switch to the corresponding first or second mode to narrow the search range to within the N / 2 level delay, thereby achieving precise positioning in the fine search stage and ensuring a timing resolution equivalent to that of N complete outputs.

[0028] (5) Determine the step size parameter of the sampling window movement according to the unit interval UI corresponding to the current working speed, so that the step size of the sampling window movement is positively correlated with the UI, thereby realizing adaptive search efficiency optimization under different working speeds and avoiding missed detection due to excessively large step size or excessively long search time due to excessively small step size.

[0029] (6) Configure the signal transition detection direction according to the termination type of the target interface standard, that is, detect the first 1 in 0 to 1 or the first 0 in 1 to 0, so as to adapt to the timing search requirements of different high-speed interface standards such as DDR5 and LPDDR5, and have good compatibility.

[0030] (7) Under the preferred architecture of 16-level TDC and 8-channel output, the number of output channels is reduced from 16 to a fixed 8, and the output register and wiring resources are reduced by about 50%, effectively reducing the chip area and power consumption. At the same time, the complementary use of four modes covers the full timing information and maintains a time resolution of 25ps.

[0031] (8) Under the 32-level TDC architecture, it still maintains 8 fixed outputs. Only the number of multiplexer inputs and the bit width of the control selection signal need to be increased without increasing the working mode of the selection multiplexer array, realizing flexible expansion from 16 levels to 32 levels and above.

[0032] (9) Through the collaborative architecture of TDC, selection multiplexer array, programmable delay line and search control module, a complete output compression and search closed-loop system is formed, realizing the unification of output resource optimization and timing positioning functions at the hardware level;

[0033] (10) The search control module realizes the hardware division of coarse-fine two-stage search through the structured division of coarse search unit, sampling window moving unit and fine search unit; the direction configuration register provides flexible signal transition detection direction configuration for different interface standards; the synchronous switching structure of the multiplexer array ensures the consistency and reliability of mode switching. Attached Figure Description

[0034] These and / or other aspects and advantages of the present invention will become apparent and readily understood from the following description of preferred embodiments taken in conjunction with the accompanying drawings, in which:

[0035] Figure 1 This is an overall architecture diagram of the TDC output compression and search method according to an embodiment of the present invention;

[0036] Figure 2 This is an overall flowchart of the TDC output compression and search method according to an embodiment of the present invention;

[0037] Figure 3 This is a schematic diagram illustrating the group selection method in four operating modes of a multiplexer array according to an embodiment of the present invention.

[0038] Figure 4 A schematic diagram of a time-series search process, representing a specific example of the output compression and search method according to the present invention;

[0039] Figure 5 This is a schematic diagram of the principle structure of an 8-group 4-to-1 multiplexer according to an example of the present invention;

[0040] Figure 6 This is a schematic diagram of a search process according to an example of the present invention;

[0041] Figure 7 A schematic diagram of the transmission link connection of a selector multiplexer array in a TDC according to an example of the present invention. Detailed Implementation

[0042] The technical solution of the present invention will be further described in detail below through embodiments and in conjunction with the accompanying drawings. In this specification, the same or similar reference numerals indicate the same or similar components. The following description of the embodiments of the present invention with reference to the accompanying drawings is intended to explain the overall inventive concept of the present invention and should not be construed as a limitation thereof.

[0043] See Figure 1 The diagram shows the overall architecture of the output compression and search method of the time-to-digital converter of the present invention.

[0044] The embodiments of the present invention are applied to the capture circuit (CaptureIC) of high-speed interface chips (e.g., DDR5, LPDDR5). The overall architecture mainly includes: a programmable delay line, a time-to-digital converter (TDC), and a selection multiplexer (Selection MUX) array.

[0045] The time-to-digital converter (TDC) retains its 16-stage delay structure, with each stage corresponding to a delay unit. The time resolution of each stage is approximately 25 picoseconds, and the overall TDC can cover a timing search range of approximately 400 ps. After the signal is input, it first undergoes delay adjustment via a programmable delay line, and then enters the 16-stage TDC. Each stage outputs a delay signal from Stage 0 to Stage 15.

[0046] The core concept of this invention is that a stage selection module is added between the TDC output terminal and the digital logic. The stage selection module is controlled by the feedback of the search control module (e.g., Search Controller, Search Finite State Machine SearchFSM), and is responsible for selecting 8 stages from 16 stages and outputting the corresponding 8-bit sampling results in stages through a fixed 8-bit output bus (b0~b7).

[0047] See Figure 2 This illustrates the overall flow of the TDC output compression and search method of the present invention.

[0048] Combination Figure 1 and Figure 2 As shown, the specific flow of the TDC output compression and search method in various embodiments of the present invention is as follows:

[0049] Step S110: Obtain the N delay signals output by the N-level delay of TDC.

[0050] Taking a 16-stage TDC as an example (N=16), each stage (Stage 0 to Stage 15) generates 1 bit of sampling result, totaling 16 bits of TDC sampling data. Each bit of sampling result reflects the phase state of the input signal after passing through that stage's delay unit. These delayed signals enter the selection multiplexer array in the stage selection module. Theoretically, the specific number of TDC stages can be expanded according to the actual chip, for example, using a 32-stage TDC or a 64-stage TDC.

[0051] Step S120: Select the operating mode of the multiplexer array by selecting the signal configuration, and map a portion of the delayed signals in the N delayed signals to the M output terminals (M < N).

[0052] The multiplexer array consists of multiple multiplexers (MUX). The delay groups corresponding to the delayed signals mapped to the M outputs differ depending on the operating mode of the multiplexer array. Taking a 16-level TDC with 8 fixed outputs as an example (N=16, M=8), the multiplexer array is configured to include four operating modes:

[0053] Mode 1: Outputs Stage 0 to Stage 7 to 8 output terminals;

[0054] Second mode (Mode 2): Output Stage 8~Stage 15 to 8 output terminals;

[0055] Even Mode: Outputs Stages 0, 2, 4, 6, 8, 10, 12, and 14 to 8 output terminals;

[0056] Odd Mode: Outputs Stages 1, 3, 5, 7, 9, 11, 13, and 15 to 8 output terminals.

[0057] See Figure 3 This illustrates the group selection method in four operating modes of the multiplexer array.

[0058] The Select Multiplexer Array implements a strategy of "dynamic reconfiguration mapping under fixed output resources". At any time, the Select Multiplexer Array selects only one of the working modes and outputs a fixed 8-channel output corresponding to the current working mode.

[0059] Step S130: In the current working mode, determine whether a signal transition is detected based on the current sampling results output from the M output terminals.

[0060] The search control module acquires 8-bit sampled results from 8 output terminals and determines whether a signal transition exists based on the distribution of 0s and 1s in the sampled results. Taking the LPDDR5 interface standard as an example (using VSSQ termination), the detection direction is the first 1 in the 0-->1 transition; taking the DDR5 interface standard as an example (using VDDQ termination), the detection direction is the first 0 in the 1-->0 transition.

[0061] Step S131: If no signal transition is detected, adjust the delay amount of the programmable delay line to move the sampling window, and reacquire the N-channel delayed signals output by the N-level delay of TDC until a signal transition is detected or the stop condition is met.

[0062] When the search control module determines that there is no signal transition within the current sampling window, it outputs a delay control signal to the programmable delay line. By adjusting the delay of the programmable delay line, the sampling window is moved forward or backward by a certain timing length. After the movement, steps S110 to S130 are executed again to detect signal transitions in the new sampling window until a signal transition is detected or the preset search boundary (stop condition) is reached.

[0063] Step S132: If a signal transition is detected, switch the operating mode of the multiplexer array according to the detection area where the signal transition occurs, and narrow the search range.

[0064] When a signal transition is detected during the coarse search phase (even-number mode, odd-number mode), the delay interval of the adjacent stage where the signal transition occurs is determined based on the boundary position of 0 and 1 in the M-bit sampling result. This determines whether the transition is located in the first half (Stage 0~Stage 7) or the second half (Stage 8~Stage 15) of the TDC. If it is in the first half, the multiplexer array's operating mode is switched to the first mode, mapping only the delayed signals from each stage of the first half to the eight output terminals. If it is in the second half, the second mode is switched, mapping only the delayed signals from each stage of the second half to the eight output terminals.

[0065] Step S140: Repeat step S130 or switch the operating mode of the multiplexer array until the signal transition is located at the adjacent delay level in the N-level delay of the TDC.

[0066] After switching to the first or second mode, signal sampling and signal transition detection are performed again in the narrowed area. Based on the output results, it is determined which two adjacent delay stages the signal transition occurred between, thereby achieving a 25ps time resolution positioning equivalent to N-channel complete output.

[0067] See Figure 4 This illustrates a specific example of a time-series search process.

[0068] like Figure 4 As shown, the actual signal transition is located between Stage 9 and Stage 10. The multiplexer array first performs a coarse search in even mode to determine that the signal transition is located between Stage 8 and Stage 10; then it switches to the second mode to further observe Stage 8 to Stage 15 for a fine search; finally, it is determined that the signal transition is located between Stage 9 and Stage 10.

[0069] In a preferred embodiment, the mapping relationship of the four operating modes of the multiplexer array is specifically explained as follows:

[0070] Let N be the number of delay stages and the corresponding number of delay signals in the TDC, M be the number of fixed output terminals, and K be a positive integer, where N = 2^K and M = K. The four operating modes are defined as follows:

[0071] Mode 1: Used to map the K delayed signals output from stages 0 to K-1 (i.e., the first half of the time zone) to M output terminals. Mode 1 is suitable for local searching of the first half of the time zone during the fine search phase.

[0072] Mode 2: This mode maps the K delayed signals from stage K to stage 2K-1 (i.e., the second half of the region) to M output terminals. Mode 2 is suitable for local searching of the second half of the region during the fine search phase.

[0073] Even Mode: This mode maps the M delayed signals (numbered even in N stages of delay) to M output terminals. The delay levels in Even Mode are: Stage 0, 2, 4, ..., 2K-2 (i.e., Stage 2i, i=0, 1, ..., K-1). Even Mode covers the entire timing search range but the sampling interval is two stages of delay, making it suitable for the coarse search phase.

[0074] Odd Mode: This mode maps M delayed signals from the odd-numbered delay outputs of N delay stages to M output terminals. The delays for each stage in Odd Mode are: Stage 1, 3, 5, ..., 2K-1 (i.e., Stage 2i+1, i=0, 1, ..., K-1). Odd Mode also covers the overall timing search range and complements Even Mode, and is also suitable for the coarse search stage.

[0075] Taking a 16-level TDC as an example (where N=16, K=8, M=8): the first mode outputs Stage 0~Stage 7; the second mode outputs Stage 8~Stage 15; the even mode outputs Stage 0, 2, 4, 6, 8, 10, 12, 14; and the odd mode outputs Stage 1, 3, 5, 7, 9, 11, 13, 15.

[0076] Taking a 32-level TDC as an example (N=32, K=16, M=8), the fixed 8-channel output is maintained. In this case, K=16 is not equal to M, but the definition of the four modes remains unchanged: the first mode outputs Stage 0~Stage 7; the second mode outputs Stage 8~Stage 15; even-numbered modes output Stages 0, 2, 4, 6, 8, 10, 12, 14; odd-numbered modes output Stages 1, 3, 5, 7, 9, 11, 13, 15. When N=32 and M=8, only 8 channels are output, i.e., the lower 8 or higher levels in the first half and the lower 8 or higher levels in the second half. The corresponding search range boundaries need to be adjusted accordingly, but the search process remains the same. The correspondence between the various working modes is shown in Table 1.

[0077] Table 1. Mapping relationship between the four operating modes of the multiplexer array

[0078]

[0079] In a preferred embodiment, the specific implementation method for detecting signal transitions in the current operating mode is described below:

[0080] When the multiplexer array is selected to operate in even or odd mode, it enters the coarse search stage. The search control module determines whether a signal transition is detected based on whether there is a continuous boundary between 0 and 1 in the M-bit sampling results output by the M output terminals.

[0081] During the coarse search phase, the multiplexer array first samples in even mode. If no signal transition is detected, it switches to odd mode for sampling. When the multiplexer array is operating in even or odd mode, the coarse search phase begins. The search control module determines whether a signal transition has been detected based on whether there are consecutive 0 and 1 boundaries in the M-bit sampling results output from the M output terminals.

[0082] Taking the LPDDR5 interface standard as an example, the detection direction is the first 1 in the 0-->1 transition. In even mode, the search control module acquires the 8-bit sampled results from the 8 output terminals. Since the delays of each stage of the TDC are sequentially delayed in time, when the transition edge of the input signal is within the timing window of the TDC, the delayed output result is as follows: the delay stage output before the transition edge is 0, and the delay stage output after the transition edge is 1, thus forming a continuous boundary between 0 and 1. The search control module detects whether this boundary exists; if it exists, it determines that a signal transition has been detected.

[0083] When a signal transition is detected, the search control module further determines the adjacent delay interval where the signal transition occurs based on the boundary position of 0 and 1 in the M-bit sampling result. For example, in even-number mode, if the output 8-bit sampling result is "00001111", it indicates that the signal transition occurred between the 4th sampling point (Stage 6) and the 5th sampling point (Stage 8), and the corresponding adjacent delay interval is between Stage 6 and Stage 8. Since the sampling interval in even-number mode is two-level delay, equivalent to 50ps resolution, the coarse search stage narrows this interval to between two even-number levels, providing regional guidance for the subsequent fine search stage.

[0084] Taking the DDR5 interface standard as an example, the detection direction is the first 0 in the 1-->0 transition. Its detection principle is similar to LPDDR5, the difference being that the search control module detects the boundary from 1 to 0 in the sampling results, that is, the delay stage output is 1 before the transition edge and 0 after the transition edge. Detecting the boundary position can determine the adjacent delay stage interval where the signal transition occurs.

[0085] The search process of this invention is a strategy that uses the 8-channel TDC results output each time to determine whether a signal transition has been detected, and then adjusts the delay of the programmable delay line accordingly before searching again.

[0086] In a preferred embodiment, the specific implementation of switching the operating mode to narrow the search range after detecting a signal transition is described below:

[0087] When the search control module detects a signal transition in the even or odd mode of the selected multiplexer array, it determines the adjacent delay interval where the signal transition is located based on the boundary position of 0 and 1 in the M-bit sampling result, and then determines whether the interval is located in the first half (Stage 0~Stage K-1) or the second half (Stage K~Stage 2K-1) of the TDC.

[0088] Taking a 16-level TDC (N=16, K=8) as an example, if the boundary position indicator signal transition is between Stage 6 and Stage 8, then the signal transition falls within the coverage area of ​​the first half of the TDC (Stage 0~Stage 7), thus switching to the first mode or odd mode to enter the fine search phase. If the boundary position indicator signal transition is between Stage 8 and Stage 10, then the signal transition falls within the coverage area of ​​the second half of the TDC (Stage 8~Stage 15), thus switching to the second mode or odd mode to enter the fine search phase.

[0089] In the actual search process, during the fine search phase, based on the boundary position information output by the coarse search, one can flexibly switch to any one of the first mode, the second mode, or the odd mode to complete the precise positioning with the optimal path.

[0090] After switching to the first or second mode, the multiplexer array maps only the delayed signals of each stage of the corresponding half-zone to M output terminals. At this time, the sampling results output by the M output terminals correspond to the continuous delay states of each stage within the half-zone, restoring the resolution to 25 ps. Based on the precise boundary between 0 and 1 in the sampling results, the search control module can locate the adjacent delay stage position of the signal transition within the corresponding half-zone, thus achieving 25 ps resolution positioning.

[0091] Continue with Figure 4 The search process shown in the example illustrates:

[0092] At this point, the actual signal transition is located between Stage 9 and Stage 10. The first stage is a coarse search, using an even-mode scan of the multiplexer array. No signal transition is detected in the first even-mode search. Therefore, the signal sampling window needs to be moved by shifting the programmable delay line. After one sampling window shift, another even-mode scan is performed, and the output is: Stage 0=0, Stage 2=0, Stage 4=0, Stage 6=0, Stage 8=0, Stage 10=1, Stage 12=1, Stage 14=1 (i.e., "00000111"). This indicates that the signal transition is located between Stage 8 and Stage 10. Since both Stage 8 and Stage 10 are located in the latter half of the region (Stage 8~Stage 15), the second mode is switched to observe only the continuous output of Stage 8~Stage 15. The output results are Stage 8=0, Stage 9=0, Stage 10=1, ..., Stage 15=1 (i.e. "00111111"). Finally, it is determined that the signal transition is located between Stage 9 and Stage 10, achieving a resolution of 25ps.

[0093] In a preferred embodiment, such as Figure 4 As shown, in the coarse search phase, it is highly likely that the initial scans of even or odd modes failed to detect the approximate range of signal transitions. Therefore, adaptive adjustment is required by moving the sampling window. The specific implementation method for adjusting the sampling window is explained below:

[0094] When the search control module does not detect a signal transition in the current operating mode of the selected multiplexer array, it needs to adjust the delay of the programmable delay line to move the sampling window. The step size parameter for window movement is determined based on the current operating rate, and this step size parameter represents the number of delay stages of the TDC corresponding to each movement of the sampling window. The search control module outputs a delay control signal to the programmable delay line according to this step size parameter, adjusting the delay of the programmable delay line and moving the entire sampling window by the timing length corresponding to this step size parameter.

[0095] The step size parameter is positively correlated with the unit interval (UI) corresponding to the current operating rate. The principle is that when the operating rate is high, the UI is small, and the timing search window needs a more precise step size to avoid skipping signal transitions; when the operating rate is low, the UI is large, and a larger step size can be used to improve search efficiency.

[0096] Taking the 10Gbps high-speed mode as an example, one UI takes approximately 100ps, while the time resolution of a single-level TDC latency is 25ps. Therefore, each window movement uses a 4-level latency step (i.e., setting 4 Steps = 100ps). Taking the 5Gbps low-speed mode as an example, one UI takes approximately 200ps. Therefore, each window movement uses an 8-level latency step (i.e., setting 8 Steps = 200ps).

[0097] The step size selection in each embodiment of the present invention is not based on the dynamic switching after calculating the timing margin in real time during the search process, but on the UI size corresponding to the current working speed, which can be automatically configured adaptively according to different working speed scenarios.

[0098] In a preferred embodiment, the specific implementation method for establishing the mathematical relationship between the step size parameter of the moving sampling window and the time resolution of UI and TDC is further described as follows:

[0099] The step size parameter S of the delay amount of the programmable delay line satisfies: S=UI / Tres, where UI is the unit interval corresponding to the current operating rate, Tres is the time resolution of the single-stage delay of the TDC, and S takes a positive integer, representing the number of delay stages of the TDC corresponding to each sampling window movement.

[0100] Typically, the time resolution Tres for a single-stage latency in TDC is 25ps. When the UI corresponding to the current operating speed is the first value (e.g., UI = 100ps, corresponding to a high-speed mode of 10Gbps), S takes the first positive integer, i.e., S = 100ps / 25ps = 4 steps. When the UI corresponding to the current operating speed is the second value (e.g., UI = 200ps, corresponding to a low-speed mode of 5Gbps), S takes the second positive integer, i.e., S = 200ps / 25ps = 8 steps. The first value of UI is less than the second value, and the first positive integer of S is less than the second positive integer, meaning the step size parameter is positively correlated with UI.

[0101] Those skilled in the art will understand that the specific values ​​mentioned above are merely illustrative examples. In practical applications, the corresponding UI value and step size parameter can be configured according to specific process conditions and the interface standard of the high-speed interface chip. For example, for other operating rates (such as 6.4Gbps, 8Gbps, etc.), the corresponding step size parameter can be calculated according to S=UI / Tres and rounded to an appropriate positive integer value.

[0102] In a specific embodiment, the implementation method of configuring different signal transition detection directions according to different interface standards of the high-speed interface chip is described as follows:

[0103] Because different high-speed interface standards use different termination methods, the detection direction of signal transition edges is different.

[0104] When the termination type is Type 1 (e.g., VSSQ termination used by LPDDR5, i.e., ground termination), it is necessary to detect the first 1 in the signal transition from 0 to 1. In this termination method, the signal line is pulled down to ground (VSSQ) through a resistor, and the data transition edge during signal transmission is a change from low level to high level. Therefore, the search control module needs to detect the boundary position from 0 to 1 in the TDC sampling results.

[0105] When the termination type is type 2 (e.g., VDDQ termination used by DDR5, i.e., power supply termination), it is necessary to detect the first 0 in the signal transition from 1 to 0. In this termination method, the signal line is pulled up to the power supply terminal (VDDQ) through a resistor, and the data transition edge during signal transmission is a change from high level to low level. Therefore, the search control module needs to detect the boundary position from 1 to 0 in the TDC sampling results.

[0106] In practical applications, the signal transition detection direction corresponding to the termination type of the target interface standard can be stored in the direction configuration register. During initialization, the search control module reads the configuration value of this direction configuration register to determine the currently used detection direction.

[0107] Thus, the output compression and search method of the present invention can be compatible with multiple high-speed interface standards such as DDR5, LPDDR5, and LPDDR4, and can adapt to the timing search requirements of different interfaces through register configuration without changing the hardware structure of TDC.

[0108] In a specific embodiment, a preferred embodiment is a 16-level TDC (N=16) and 8-channel fixed output (M=8), and the specific implementation of the output compression and search method of the present invention is further described in detail.

[0109] like Figure 1 As shown, the TDC maintains a 16-level delay structure, with a time resolution of 25ps for each level of delay, and a total coverage timing search range of 400ps. Four operating modes are selected for the multiplexer array: Mode 1, Mode 2, Even Mode, and Odd Mode. The delay groupings corresponding to each mode are shown in Table 1 above.

[0110] The selection multiplexer array consists of eight groups of 4-to-1 multiplexers (MUX arrays). Each group of multiplexers corresponds to one output, and the four inputs of each group of multiplexers are connected to the corresponding delay outputs for the four operating modes. All eight groups of 4-to-1 multiplexers are controlled by the same 2-bit selection signal SEL<1:0> to synchronously switch the operating modes of the selection multiplexer array.

[0111] See Figure 5 The diagram illustrates the principle structure of an example 8-group 4-to-1 multiplexer.

[0112] like Figure 5 As shown, the eight groups of 4-to-1 multiplexers output P0_NEW to P7_NEW respectively. For the i-th group of MUX (i=0,1, … , 7), its four input terminals are connected to: Stage i (i=0~7, i.e., Stage 0~7) corresponding to the first mode, Stage i+8 (i=0~7, i.e., Stage 8~15) corresponding to the second mode, Stage 2i (i=0~7, i.e., Stage 0, 2, 4, 6, 8, 10, 12, 14) corresponding to the even mode, and Stage 2i+1 (i=0~7, i.e., Stage 1, 3, 5, 7, 9, 11, 13, 15) corresponding to the odd mode. When the 2-bit selection signal SEL<1:0>=00, the first mode is selected; when SEL<1:0>=01, the second mode is selected; when SEL<1:0>=10, the even mode is selected; when SEL<1:0>=11, the odd mode is selected.

[0113] See Figure 6The diagram shows an example search flowchart.

[0114] In the first stage, coarse search: the search control module first controls the multiplexer array to operate in even mode and performs one sampling judgment. If a signal transition is detected in even mode, it directly enters the third stage (fine search); if no signal transition is detected, it controls the multiplexer array to switch to odd mode and performs another sampling judgment. If no signal transition is still detected in odd mode, it enters the second stage (sampling window movement); if a signal transition is detected in odd mode, it enters the third stage (fine search).

[0115] The second stage involves moving the sampling window: when no signal transition is detected in the current sampling window, the search control module moves the input signal sampling position via a programmable delay line. The step size parameter is determined based on the current operating rate: for the 10Gbps high-speed mode (UI≈100ps), a 4-step movement step is used; for the 5Gbps low-speed mode (UI≈200ps), an 8-step movement step is used. After completing the sampling window movement, the first stage of coarse searching is performed again.

[0116] The third stage, fine-tuning search: After detecting the area where the signal transition occurs, the search control module switches to the corresponding first mode, second mode, or odd mode based on whether the signal transition is located in the first or second half of the region, thus narrowing the search range. For example, if the signal transition is in the first half of the region, it can switch to the first mode or odd mode; if it is in the second half, it can switch to the second mode or odd mode. In the switched mode, the search range is narrowed to an 8-level delay region, and finally, through local search, the exact location of the two adjacent delay levels where the signal transition occurs is precisely determined, achieving a 25ps resolution positioning.

[0117] For details on the implementation process, please refer to [link / reference]. Figure 4 The example of the search and location process shown is not repeated here.

[0118] Taking a single Data Queue (DQ) channel in a 28nm process as an example, the output registers and wiring area corresponding to 16 TDC outputs in existing technologies is approximately 320μm × 120μm. By adopting the output compression and search method of this invention, since the output bit width is reduced from 16 bits to 8 bits (i.e., from a 16-bit output bus to an 8-bit output bus), the corresponding output registers and related wiring resources can theoretically be reduced by about 50%, and the corresponding area can also be reduced by about 50%. The MUX array itself has a small area, so the reduction in registers and wiring resources is negligible.

[0119] Furthermore, the reduced number of outputs also reduces the number of cross-region wirings, which is beneficial for optimizing chip layout and routing. In terms of power consumption, the reduced number of output registers and output drivers helps reduce overall digital logic switching activity and output load.

[0120] In one specific embodiment, the present invention also provides a scalable implementation scheme with 32 levels of TDC (N=32), the specific implementation method of which is described below:

[0121] The TDC includes 32 delay levels: Stage 0 to Stage 31, and still maintains 8 fixed outputs (M=8). The selection multiplexer array still consists of 8 groups of 4-to-1 multiplexers, each group of 4-to-1 multiplexers corresponds to one output terminal, and the input terminals are respectively connected to the output terminals of the delay stages corresponding to each working mode in the 32 delay levels.

[0122] Since N=32 and M=8, meaning 32-level delay is compressed into 8 outputs, the number of inputs and control logic for each multiplexer group are correspondingly expanded. The operating mode can then be defined as:

[0123] First mode: Output Stage 0~Stage 7 (the lower 8 levels of the first half);

[0124] Second mode: Output Stage 8~Stage 15 (the 8 higher stages in the first half);

[0125] Third mode: Output Stage 16~Stage 23 (the lower 8 levels of the second half);

[0126] Fourth mode: Output Stage 24~Stage 31 (8 levels higher in the latter half);

[0127] The fifth mode is the even-numbered mode: the even-numbered delay levels in Stages 0, 2, 4, ..., 30 correspond to the 8 output channels;

[0128] The sixth mode is the odd-number mode: the odd-number delay levels corresponding to the 8 outputs in Stage 1, 3, 5, ..., 31.

[0129] Since the number of working modes has been expanded to P=6, the bit width of the selection signal is expanded accordingly based on the formula ceil(log2P)=ceil(log26)=3 bits.

[0130] For the N=32 expansion scheme, a multi-level, step-by-step narrowing strategy can be adopted in the fine search phase: first, a coarse search using even / odd number modes is used to determine the approximate region where the signal transition occurs; then, the mode is switched to the corresponding half-region to gradually narrow the range, ultimately locating the adjacent delay position where the signal transition occurs. The overall search process is consistent with the 16-level TDC implementation, both following a three-stage process: "coarse search --> sampling window movement (judging whether adaptive adjustment is needed based on whether a signal transition is detected) --> step-by-step fine search".

[0131] Those skilled in the art will understand that this embodiment is also applicable to the expansion of a 64-level TDC, maintaining 8 fixed outputs, only requiring an increase in the number of operating modes and the number of multiplexer inputs, as well as an expansion of the selection signal bit width.

[0132] To implement the output compression and search methods of the above embodiments, the present invention also provides an output compression and search system for TDC.

[0133] like Figure 1 As shown, the output compression and search system mainly includes: a time-to-digital converter (TDC), a selection multiplexer array, a programmable delay line, and a search control module.

[0134] Time-to-Digital Converter (TDC): This consists of N delay stages, each outputting a delayed signal. Each stage corresponds to a single delay unit, and the stages are connected in series. After the input signal is delayed through each stage, the output of each stage carries a delayed signal with phase information. For example, a 16-stage TDC has a time resolution of 25 ps for each delay stage, and a total timing search range of 400 ps.

[0135] Selection multiplexer array: Connected between the output of the TDC and the digital logic, it has M outputs and multiple operating modes (M < N). It is used to map a portion of the delayed signals from N delayed signals to the M outputs based on a selection signal. The delay level grouping corresponding to the delayed signals mapped to the M outputs differs in different operating modes. Taking a 16-level TDC with 8 outputs as an example, the selection multiplexer array consists of 8 groups of 4-to-1 multiplexers, with four operating modes (mode 1, mode 2, even mode, and odd mode), controlled by a 2-bit selection signal SEL<1:0>.

[0136] Programmable delay line: Connected to the input of the TDC, it is used to adjust the delay of the input signal according to the delay control signal to move the sampling window. The programmable delay line can adopt a Digital Controlled Delay Line (DCDL) structure. By adjusting its delay level through the delay control signal, the phase position of the input signal entering the TDC is changed, so as to move the sampling window as a whole by a preset step size parameter.

[0137] The search control module is connected to the control terminals of the selection multiplexer array and the programmable delay line, respectively. It outputs selection signals to configure the operating mode of the selection multiplexer array and, in the current operating mode, determines whether a signal transition is detected based on the current sampling results output from the M output terminals. If no signal transition is detected, a delay control signal is output to the programmable delay line to move the sampling window; if a signal transition is detected, the operating mode of the selection multiplexer array is switched according to the detection area where the signal transition occurs to narrow the search range. The search control module repeats the above operations until the adjacent delay level position of the signal transition within the N-level delay of the TDC is located.

[0138] The search control module can be implemented using a hardware finite state machine (HFSM), a microcontroller unit (MCU), or a digital signal processor (DSP), or other control modules or chips. Using a hardware finite state machine is preferred, as it effectively reduces latency and improves response speed. The state transition logic implemented within this hardware finite state machine corresponds to, for example... Figure 6 The search algorithm flow is shown below.

[0139] In a specific embodiment, the mapping relationship between the various operating modes of the multiplexer array selected in the output compression and search system is as follows:

[0140] Let N be the number of delay stages in the TDC, M be the number of fixed outputs, and K be a positive integer, where N = 2K and M = K. Then the operating modes of the multiplexer array include:

[0141] Mode 1: Maps the K delayed signals from delay stages 0 to (K-1) to M output terminals. Taking N=16 and K=8 as an example, Mode 1 outputs Stage 0 to Stage 7.

[0142] Mode 2: Maps the K delayed signals from delay stages K to 2K-1 to M output terminals. Taking N=16 and K=8 as an example, Mode 2 outputs Stage 8 to Stage 15.

[0143] Even Mode: Maps the M delayed signals from the even-numbered delay stage in the N-stage delay stages to M output terminals. Taking N=16 and M=8 as an example, the even mode output stages are 0, 2, 4, 6, 8, 10, 12, and 14.

[0144] Odd Mode: Maps the M delayed signals from the odd-numbered delay stages in the N-stage delay stages to M output terminals. Taking N=16 and M=8 as an example, the Odd Mode output stages are Stage 1, 3, 5, 7, 9, 11, 13, and 15.

[0145] The mapping relationship between the four modes can be configured via selection signals, and the switching between modes is dynamically controlled by the search control module according to the current search stage. Furthermore, at any given time, the multiplexer array will only execute one of the operating modes.

[0146] In one specific embodiment, the internal structure of the search control module is further configured to include a coarse search unit, a sampling window movement unit, and a fine search unit.

[0147] The coarse search unit controls whether the multiplexer array operates in even or odd mode, and determines whether a signal transition is detected based on the presence of a 0-1 boundary in the M-bit sampled results from the M output terminals. The coarse search unit first outputs a selection signal to configure the multiplexer array to even (or odd) mode, then reads the M-bit sampled results from the M output terminals and checks for consecutive 0-1 boundaries. If a boundary exists, a signal transition is detected, and the boundary position is output to the fine search unit; if no boundary exists, a "not detected" indication signal is sent to the sampling window movement unit.

[0148] Sampling window movement unit: When the coarse search unit does not detect a signal transition, it determines the step size parameter based on the current operating rate and outputs a delay control signal to the programmable delay line according to the step size parameter, thereby moving the sampling window by the timing length corresponding to the step size parameter. The sampling window movement unit can be configured with a step size parameter lookup table to store the step size parameter values ​​corresponding to different operating rates.

[0149] For example, 10Gbps corresponds to a step size of 4 steps, and 5Gbps corresponds to a step size of 8 steps. When the "not detected" indication signal is received from the coarse search unit, the sampling window moving unit searches for the corresponding step size parameter according to the current operating rate, generates the corresponding delay control signal, and outputs it to the programmable delay line.

[0150] Fine search unit: After the coarse search unit detects a signal transition, it switches the multiplexer array to the first mode, the second mode, or the odd mode according to whether the signal transition is located in the first or second half of the TDC, and locates the adjacent stage delay position of the signal transition in the corresponding half of the sampling result after switching.

[0151] The fine search unit obtains the boundary position information from the coarse search unit, determines whether the area corresponding to the boundary position is located in the first half or the second half, and then outputs the corresponding selection signal to switch the multiplexer array to the first mode (first half) or the second mode (second half). It reads the sampling result after switching, accurately locates the adjacent stage delay position where the signal transition occurs, and outputs the location result.

[0152] In a specific embodiment, the adaptive configuration of the step size of the sampling window moving unit is implemented as follows:

[0153] When the sampling window moving unit determines the step size parameter based on the current operating rate, the step size parameter S satisfies: S = UI / Tres, where UI is the unit interval corresponding to the current operating rate, Tres is the time resolution of the single-level delay of TDC, and S is a positive integer. For specific adjustments to the step size parameter, please refer to the descriptions of the above method embodiments; they will not be repeated here.

[0154] For example, the sampling window moving unit can configure the UI value corresponding to the current operating rate through internal registers, and can also obtain the current operating rate configuration information from the host computer through an external bus interface (such as I2C bus, SPI bus, etc.), and then calculate or find the corresponding step size parameter S. By configuring the step size parameter, the output compression and search system can adaptively adjust the search step size in different operating modes, balancing search efficiency and search accuracy.

[0155] In a preferred embodiment, in order to achieve signal transition detection direction adaptation to support different interface standards, a direction configuration register is also set in the output compression and search system.

[0156] The direction configuration register is connected to or integrated into the search control module to store the signal transition detection direction corresponding to the termination type of the target interface standard. During the initialization phase and / or when switching the operating mode of the multiplexer array, the search control module reads the detection direction information stored in the direction configuration register and executes the corresponding signal transition detection logic accordingly.

[0157] Specifically, the direction configuration register can be programmed via external interfaces (such as boundary scan) or serial peripheral interfaces (such as Serial Peripheral Interface, SPI), or the default configuration can be automatically loaded by the fuse or non-volatile memory (NVM) of the internal control chip of the output compression and search system when the control chip starts up. The direction configuration register allows the output compression and search system to flexibly adapt to different interface standards, enhancing the system's versatility and compatibility.

[0158] In a preferred embodiment, the circuit implementation structure for selecting the multiplexer array is as follows:

[0159] The multiplexer array comprises M groups of multiplexers (MUX), each group of multiplexers having multiple inputs and one output, with the output of each group of multiplexers serving as one of M fixed outputs.

[0160] like Figure 5 As shown, taking a 16-level TDC (N=16) and 8-channel fixed output (M=8) as an example, the selection multiplexer array includes 8 groups of 4-to-1 multiplexers. Each group of 4-to-1 multiplexers has 4 data input terminals, 1 data output terminal, and 1 selection input terminal (actually a 2-bit selection signal SEL<1:0>). The 8 groups of 4-to-1 multiplexers output P0_NEW to P7_NEW respectively. For the specific data input / output paths and their mapping relationship with the operating modes, please refer to the descriptions of the aforementioned method embodiments, which will not be repeated here.

[0161] See Figure 7 The diagram shows the transmission link connection principle of the multiplexer array in the TDC.

[0162] The multiplexer array is positioned between the analog output and digital logic of the TDC, serving as a resource reduction hub between the analog and digital domains. For example... Figure 7 As shown, the TDC output nodes of Stage 0 to Stage 15 of the analog section are selected by the multiplexer array and then transmitted to the digital section for processing.

[0163] For example, in the extended embodiment with N=32 and M=8, the multiplexer array still consists of 8 groups of multiplexers, but the number of inputs of each group of multiplexers needs to be increased accordingly based on the number of operating modes (e.g., 6-to-1 or 8-to-1 multiplexers, etc.), and the control signal bit width also needs to be extended.

[0164] The output compression and search methods of the above embodiments of the present invention do not rely on hardware recognition of the "first 1" or "first 0" during the search process. Instead, they determine whether a signal transition is detected by analyzing the eight-channel TDC results output each time, and adjust the delay of the programmable delay line accordingly before performing further searches. By selecting different operating modes of the multiplexer array to form complementary timing coverage, the signal transition position is gradually located through multiple rounds of searching, while avoiding missed detection of signal transitions due to a single operating mode not covering the overall timing range. This output compression and search method is suitable for applications such as Automated Test Equipment (ATE) or Built-in Self-Test (BIST) for chips.

[0165] The output compression and search method and system for a time-to-digital converter for a high-speed interface chip provided by embodiments of the present invention have at least one or a portion of the following advantages:

[0166] (1) By selecting the multiplexer array, the N-level delayed output N-channel delayed signals are dynamically mapped to M output terminals (M<N). Combined with signal transition detection and programmable delay line moving sampling window, the output resource compression and complete timing positioning are unified while keeping the TDC time resolution unchanged.

[0167] (2) By defining four working modes, namely the first mode, the second mode, the even mode and the odd mode, a delay-level grouping method that complements the overall time series region is provided for the coarse-fine two-stage search, ensuring that all N-level delay time series information can still be covered under the condition of fixed M output terminals.

[0168] (3) In even or odd mode, the signal transition is determined by detecting whether there is a continuous boundary between 0 and 1 in the sampling results of M output terminals, and the adjacent delay interval where the transition is located is determined according to the boundary position, thus realizing the rapid area positioning in the coarse search stage.

[0169] (4) Based on whether the signal transition is in the first or second half of the region, switch to the corresponding first or second mode to narrow the search range to within the N / 2 level delay, thereby achieving precise positioning in the fine search stage and ensuring a timing resolution equivalent to that of N complete outputs.

[0170] (5) Determine the step size parameter of the sampling window movement according to the unit interval UI corresponding to the current working speed, so that the step size of the sampling window movement is positively correlated with the UI, thereby realizing adaptive search efficiency optimization under different working speeds and avoiding missed detection due to excessively large step size or excessively long search time due to excessively small step size.

[0171] (6) Configure the signal transition detection direction according to the termination type of the target interface standard, that is, detect the first 1 in 0 to 1 or the first 0 in 1 to 0, so as to adapt to the timing search requirements of different high-speed interface standards such as DDR5 and LPDDR5, and have good compatibility.

[0172] (7) Under the preferred architecture of 16-level TDC and 8-channel output, the number of output channels is reduced from 16 to a fixed 8, and the output register and wiring resources are reduced by about 50%, effectively reducing the chip area and power consumption. At the same time, the complementary use of four modes covers the full timing information and maintains a time resolution of 25ps.

[0173] (8) Under the 32-level TDC architecture, it still maintains 8 fixed outputs. Only the number of multiplexer inputs and the bit width of the control selection signal need to be increased without increasing the working mode of the selection multiplexer array, realizing flexible expansion from 16 levels to 32 levels and above.

[0174] (9) Through the collaborative architecture of TDC, selection multiplexer array, programmable delay line and search control module, a complete output compression and search closed-loop system is formed, realizing the unification of output resource optimization and timing positioning functions at the hardware level;

[0175] (10) The search control module realizes the hardware division of coarse-fine two-stage search through the structured division of coarse search unit, sampling window moving unit and fine search unit; the direction configuration register provides flexible signal transition detection direction configuration for different interface standards; the synchronous switching structure of the multiplexer array ensures the consistency and reliability of mode switching.

[0176] While some embodiments of the present general inventive concept have been shown and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the present general inventive concept, the scope of which is defined by the claims and their equivalents.

Claims

1. A method for output compression and search of a time-to-digital converter for a high-speed interface chip, characterized in that, The output compression and search method includes: Step S110: Obtain the N delayed signals output by the N-stage delay of the time-to-digital converter, where N is a positive integer; Step S120: Select multiple operating modes of the multiplexer array by selecting the signal to map a portion of the delayed signals in the N delayed signals to M output terminals, where M is a positive integer less than N. The delay groups corresponding to the delayed signals mapped to the M output terminals by the multiplexer array are different in different operating modes, and at any time, the multiplexer array selects only one of the operating modes. Step S130: In the current operating mode, determine whether a signal transition is detected based on the current sampling results output from the M output terminals. If the signal transition is not detected, the delay of the programmable delay line is adjusted to move the sampling window, and steps S110 to S130 are repeated until the signal transition is detected or the stop condition is met. If the signal transition is detected, the operating mode of the selection multiplexer array is switched according to the detection area where the signal transition occurs, thereby narrowing the search range. The operating mode includes an even mode and an odd mode. In the coarse search stage, the selection multiplexer array first samples in the even mode and then samples in the odd mode. Step S140: Repeat step S130 or the step of switching the working mode until the position of the signal transition in the adjacent delay stage in the N-stage delay of the time-to-digital converter is located.

2. The output compression and search method according to claim 1, characterized in that, The various working modes include: The first mode is configured to map the K-channel delay signals from level 0 to level K-1 delay outputs to the M output terminals; The second mode is configured to map the K-channel delay signals from the Kth stage to the (2K-1)th stage delay output to the M output terminals; Even mode, wherein the even mode is configured to map the M delay signals of the even-numbered delay outputs in the N-level delay to the M output terminals; Odd mode, wherein the odd mode is configured to map the M delay signals of the delay outputs numbered odd-numbered in the N-level delay to the M output terminals; Where N=2K, M=K, and K is a positive integer.

3. The output compression and search method according to claim 2, characterized in that, In the current operating mode, determining whether a signal transition is detected based on the current sampling results output from the M output terminals includes: When the selection multiplexer array operates in the even mode or the odd mode, it is determined whether the signal transition is detected based on whether there is a continuous boundary between 0 and 1 in the M-bit sampling results output by the M output terminals. When the signal transition is detected, the adjacent delay interval where the signal transition is located is determined based on the boundary position of 0 and 1 in the M-bit sampling result.

4. The output compression and search method according to claim 3, characterized in that, If the signal transition is detected, the operating mode of the selection multiplexer array is switched according to the detection area where the signal transition occurs, in order to narrow the search range, including: Based on the adjacent stage delay interval where the signal transition is located, it is determined whether the signal transition is located in the first half or the second half of the time-to-digital converter. If the signal transition is located in the first half of the region, the selection multiplexer array is switched to the first mode or the odd mode, and only the delayed signals of each level of the delay output in the first half of the region are mapped to the M output terminals. If the signal transition is located in the latter half of the region, the selection multiplexer array is switched to the second mode or the odd mode, and only the delayed signals of each stage of the delayed output in the latter half of the region are mapped to the M output terminals; In the switched working mode, the delay position of the signal transition in the adjacent stage in the first half or the second half is located according to the current sampling results output by the M output terminals.

5. The output compression and search method according to any one of claims 1-4, characterized in that, The adjustment of the delay of the programmable delay line to move the sampling window includes: The step size parameter is determined based on the current operating rate, and the step size parameter represents the number of delay stages of the time-to-digital converter corresponding to each movement of the sampling window; The delay of the programmable delay line is adjusted according to the step size parameter so as to move the entire sampling window by the timing length corresponding to the step size parameter; The step size parameter is positively correlated with the unit interval corresponding to the current working rate.

6. The output compression and search method according to claim 5, characterized in that, The delay step parameter S of the programmable delay line satisfies: S=UI / Tres, where UI is the unit interval corresponding to the current operating rate, Tres is the time resolution of the single-stage delay of the time-to-digital converter, and S takes a positive integer. When the UI corresponding to the current working speed is the first value, S takes the first positive integer; When the UI corresponding to the current working speed is the second value, S takes the second positive integer; The first value is less than the second value, and the first positive integer is less than the second positive integer.

7. The output compression and search method according to claim 5, characterized in that, The output compression and search method also includes: The detection direction of the signal transition is determined according to the termination type of the target interface standard; When the termination type is the first type, the first 1 in the signal transition from 0 to 1 is detected; When the termination type is type 2, the first 0 in the signal transition from 1 to 0 is detected.

8. The output compression and search method according to claim 1, characterized in that, The time-to-digital converter has a 16-stage delay, N=16, M=8, and the multiple operating modes of the selected multiplexer array include: The first mode is configured to map the 8 delayed signals from the 0th to the 7th stage delay outputs to 8 output terminals; The second mode is configured to map the 8 delayed signals from the 8th to the 15th delay outputs to 8 output terminals; Even-number mode, which is configured to map the 8 delayed signals of the 0th, 2nd, 4th, 6th, 8th, 10th, 12th and 14th delay outputs to 8 output terminals; Odd mode, which is configured to map the 8 delayed signals of the 1st, 3rd, 5th, 7th, 9th, 11th, 13th and 15th delay outputs to 8 output terminals.

9. The output compression and search method according to claim 1, characterized in that, The time-to-digital converter has an N-level delay, and the selection multiplexer array consists of 8 groups of multiplexers. Each group of multiplexers corresponds to an output terminal, and the input terminal of each group of multiplexers is connected to the output terminal of the delay stage corresponding to each working mode in the N-level delay. The bit width of the selection signal is calculated using the formula ceil(log2P), where P is the number of the various operating modes.

10. An output compression and search system for a time-to-digital converter in a high-speed interface chip, characterized in that, The output compression and search system includes: A time-to-digital converter, comprising N stages of delay, wherein the N stages of delay output N delayed signals respectively; The multiplexer array is selected and connected between the output of the time-to-digital converter and the digital logic. The multiplexer array has M outputs and is configured with multiple operating modes. According to the selection signal, a portion of the delay signals in the N delay signals are mapped to the M outputs, where M is a positive integer less than N. The delay level grouping corresponding to the delay signals mapped to the M outputs by the multiplexer array is different in different operating modes, and at any given time, the multiplexer array selects only one of the operating modes. A programmable delay line, connected to the input of the time-to-digital converter, is configured to adjust the delay of the input signal according to a delay control signal to move the sampling window; A search control module, connected to both the control terminal of the selection multiplexer array and the control terminal of the programmable delay line, is configured to output the selection signal to configure the operating mode of the selection multiplexer array, and, in the current operating mode, determine whether a signal transition is detected based on the current sampling results output from the M output terminals; wherein... If the search control module does not detect the signal transition, it outputs the delay control signal to the programmable delay line to move the sampling window; If the search control module detects the signal transition, it switches the operating mode of the selection multiplexer array according to the detection area where the signal transition occurs, so as to narrow the search range. The operating mode includes an even mode and an odd mode. In the coarse search stage, the search control module controls the selection multiplexer array to first sample in the even mode and then sample in the odd mode. The search control module repeatedly detects until it locates the position of the signal transition in the adjacent delay level of the N-level delay of the time-to-digital converter.

11. The output compression and search system according to claim 10, characterized in that, The various working modes include: The first mode is configured to map the K-channel delay signals from level 0 to level K-1 delay outputs to the M output terminals; The second mode is configured to map the K-channel delay signals from the Kth stage to the (2K-1)th stage delay output to the M output terminals; Even mode, wherein the even mode is configured to map the M delay signals of the even-numbered delay outputs in the N-level delay to the M output terminals; Odd mode, wherein the odd mode is configured to map the M delay signals of the delay outputs numbered odd-numbered in the N-level delay to the M output terminals; Where N=2K, M=K, and K is a positive integer.

12. The output compression and search system according to claim 11, characterized in that, The search control module includes: A coarse search unit is configured to control the selection multiplexer array to operate in the even mode or the odd mode, and to determine whether the signal transition is detected based on whether there is a boundary between 0 and 1 in the M-bit sampling results output by the M output terminals. A sampling window moving unit is configured to determine a step size parameter based on the current operating rate when the coarse search unit does not detect the signal transition, and output the delay control signal to the programmable delay line according to the step size parameter, so as to move the sampling window by the timing length corresponding to the step size parameter; The fine search unit is configured to, after the coarse search unit detects the signal transition, switch the selection multiplexer array to the first mode, the second mode, or the odd mode according to whether the signal transition is located in the first half or the second half of the time-to-digital converter, and locate the adjacent stage delay position of the signal transition in the first half or the second half of the time-to-digital converter according to the sampling result after switching.

13. The output compression and search system according to any one of claims 10-12, characterized in that, The output compression and search system also includes a direction configuration register, which is configured to store the signal transition detection direction corresponding to the termination type of the target interface standard. The search control module detects the first 1 in a signal transition from 0 to 1 or the first 0 in a signal transition from 1 to 0, based on the signal transition detection direction stored in the direction configuration register.

14. The output compression and search system according to claim 13, characterized in that, The selection multiplexer array includes M groups of multiplexers, each group of multiplexers is configured with multiple input terminals and one output terminal, and the output terminal of each group of multiplexers serves as one of the M output terminals. The multiple inputs of each group of multiplexers are respectively connected to the outputs of the delays corresponding to each working mode in the N-level delays; The M groups of multiplexers are controlled by the same selection signal to synchronously switch operating modes.

Images