Micro-display wafer grading photoelectric test method and test system

Abstract

The application discloses a micro-display wafer grading photoelectric test method and a test system. The method comprises the following steps: calling corresponding test configuration parameters according to device type information; performing aging pretreatment on each die in a to-be-tested row of dies through a row-level probe card; applying a lighting electrical signal to the to-be-tested row of dies after aging pretreatment, collecting fast screening detection data of each die in a lighting process until full-wafer fast screening data are obtained; marking dies meeting adverse judgment conditions as unqualified and removing the dies, marking target dies from the remaining dies according to a preset screening condition; performing photoelectric characteristic test on each target die through a single-die probe card to obtain precision measurement data of each target die; and integrating the full-wafer fast screening data and the precision measurement data of each target die to generate a test result of the to-be-tested wafer. The application can reduce the time consumed by die-by-die needle detection, and only performs precision measurement on the screened target dies, so that the test efficiency is improved while realizing automatic detection.

Description

Technical Field

[0001] This application belongs to the field of optoelectronic testing technology for microdisplay wafers, specifically relating to a hierarchical optoelectronic testing method and system for microdisplay wafers. Background Technology

[0002] In the manufacturing process of microdisplay chips, wafer-level optoelectronic inspection is a core process for controlling chip yield. Currently, the mainstream inspection method in the industry is point-by-point probing of each die on the wafer. This involves using probes to power each die individually, sequentially testing parameters such as image quality, spectrum, viewing angle, and current-voltage characteristics. As wafer sizes continue to increase, the number of dies on a single wafer increases significantly, leading to a continuous increase in the overall testing time for a single wafer due to this die-by-die testing approach.

[0003] For a long time, the perception that yield control accuracy can only be guaranteed by performing full-parameter testing on every single die on the wafer has limited the R&D efforts of equipment manufacturers. They have consistently focused on improving single-die testing speed, failing to break free from the technical framework of full-die testing. While some solutions have attempted to increase testing speed by lighting up each row sequentially, the essence remains full-wafer, row-by-row inspection. Each die still needs to undergo a complete full-parameter testing process, thus not fundamentally reducing the testing workload.

[0004] Meanwhile, most solutions lack a pre-aging process, resulting in insufficient stability of optoelectronic test data. This makes it difficult to effectively streamline the test process while ensuring test accuracy, and fails to meet the test efficiency requirements of mass production. Summary of the Invention

[0005] This application provides a graded optoelectronic testing method and system for microdisplay wafers, which can reduce the time spent on point-by-point probing of the wafers and perform precise testing only on the selected target wafers, thereby improving testing efficiency while achieving automated testing.

[0006] To address the aforementioned technical problems, this application provides a method for hierarchical photoelectric testing of microdisplay wafers, comprising the following steps: Obtain the device type information of the wafer under test, and call the corresponding test configuration parameters based on the device type information; The row-level probe card is aligned and pressed with the test row dies of the wafer under test, and the aging pretreatment of each die in the test row dies is performed through the row-level probe card. An illumination electrical signal is applied to the test row of grains after aging pretreatment, and rapid screening detection data of each grain is collected simultaneously during the illumination process of the test row of grains. Replace the test row of the die, repeat the aging pretreatment and the application of the lighting electrical signal until the full wafer fast screening data integrating all row die fast screening test data is obtained; Based on the whole wafer fast screening data, the grains that meet the defect judgment conditions are marked as unqualified and removed, and the target grains to be finely tested are marked from the remaining grains according to the preset screening conditions. The target crystals are sequentially aligned and pressed with the single-crystal probe cards. The photoelectric properties of each target crystal are then tested using the single-crystal probe cards to obtain precise measurement data for each target crystal. The test results of the wafer to be tested are generated by integrating the full wafer rapid screening data with the precision measurement data of each target grain.

[0007] As a further improvement of this application, the device type information includes at least silicon-based micro light-emitting diode wafers and silicon-based micro organic light-emitting diode wafers, and both the silicon-based micro light-emitting diode wafers and silicon-based micro organic light-emitting diode wafers are provided with corresponding row-level probe cards and single-crystal probe cards.

[0008] As a further improvement to this application, the aging pretreatment of each grain in the row-level probe card includes: An aging pulse current adapted to the device type information is synchronously applied to each die in the test row.

[0009] As a further improvement to this application, the synchronous acquisition of rapid screening detection data of each grain during the illumination process of the grain under test includes: Simultaneously collect the appearance image data, luminescence quality image data, and basic electrical data of each grain in the test row.

[0010] As a further improvement to this application, the step of marking and removing grains that meet the defect determination criteria as unqualified includes: If the basic electrical parameters of the current grain exceed the preset threshold, it is determined that the current grain has an open circuit or a short circuit, and the current grain is marked as unqualified and removed. If the appearance image data of the current grain indicates that the current grain has an appearance defect, then the current grain is marked as unqualified and discarded. If the current chip is determined to have lighting failure, linear defects, or spot defects based on the luminous image quality data of the current chip, then the current chip will be marked as unqualified and discarded.

[0011] As a further improvement to this application, the step of marking the target grains to be precisely measured from the remaining grains according to preset screening conditions includes: A preset ratio is used to extract grains that have never been rejected and have not been marked as suspected defects. The extracted grains and suspected defects are marked as target grains to be precisely tested. If the basic electrical parameters of the grain are located within a preset range of suspicious parameters, or if there are suspicious image features in the appearance image data of the grain, or if there are suspicious abnormal features in the luminescence image data of the grain, then the current grain will be marked as a suspicious defective grain.

[0012] As a further improvement of this application, if there are suspicious image features in the appearance image data of the grain, then the subsurface infrared image of the current grain is acquired, and the presence of subsurface crack extension and the direction of the extension line of the current grain is identified based on the subsurface infrared image.

[0013] As a further improvement to this application, the photoelectric property testing of each target grain includes: Each target crystal is sequentially subjected to image quality detection, spectral parameter testing, viewing angle characteristic testing, and current and voltage characteristic testing until the photoelectric characteristic testing of all target crystals is completed.

[0014] As a further improvement to this application, the generation of test results for the wafer under test includes: The test results are generated, which include the yield distribution information of each grain in the wafer under test, the coordinates of the defective grains, and the precise measurement data of each target grain.

[0015] As a further improvement to this application, this application also provides a micro-display wafer hierarchical optoelectronic testing system, comprising: The calling module is used to obtain the device type information of the wafer under test and call the corresponding test configuration parameters based on the device type information; The aging module is used to align and press the row-level probe card with the test row dies of the wafer under test, and to perform aging pretreatment on each die in the test row dies through the row-level probe card. The acquisition module is used to apply a lighting electrical signal to the test row of grains after aging pretreatment, and simultaneously acquire the fast screening detection data of each grain during the lighting process of the test row of grains; The execution module is used to replace the test row of dies, repeat the aging pretreatment and the application of the lighting electrical signal until the full wafer fast screening data integrating all row die fast screening test data is obtained; The marking module is used to mark and remove grains that meet the defect judgment conditions based on the full wafer fast screening data, and to mark the target grains to be finely tested from the remaining grains according to the preset screening conditions. The testing module is used to sequentially align and press the target dies with the single-die probe card, and then use the single-die probe card to test the photoelectric properties of each target die to obtain precise measurement data for each target die. An integration module is used to integrate the full wafer rapid screening data with the precision measurement data of each target grain to generate the test results of the wafer to be tested.

[0016] This application provides a microdisplay wafer hierarchical photoelectric testing method and system. After aligning and pressing row-level probe cards with the dies in the row to be tested, the row-level probe cards perform aging pretreatment on each die in the current row. Then, a lighting signal is applied, and rapid screening data for each die is simultaneously acquired during the lighting process. After completing one row, the process is repeated for the next row, performing the aging pretreatment and applying the lighting signal until full-wafer rapid screening data is obtained. Based on the full-wafer rapid screening data, dies that meet the defect judgment criteria are marked as unqualified and removed. Target dies to be precisely tested are then marked from the remaining dies according to preset screening conditions. The target dies are sequentially aligned and pressed with single-die probe cards, and photoelectric characteristic tests are performed to obtain precise measurement data for each target die. Finally, the full-wafer rapid screening data and precise measurement data are integrated to generate the test results.

[0017] In this way, the row-level probe card can simultaneously power and acquire data from the entire row of chips, significantly reducing the time required for preliminary testing compared to chipping each chip individually. Aging pretreatment ensures the chips reach a stable state before testing, guaranteeing the reliability of the rapid screening data. During the rapid screening stage, coarse defective chips are removed, and only suspected defective chips and a predetermined proportion of good chips are sent to the precision testing stage. This avoids high-precision testing resources being consumed by a large number of coarse defect screenings, while ensuring the accuracy of yield assessment for target chips in the precision testing stage, thereby improving testing efficiency while maintaining yield control accuracy. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only a part of the embodiments of this application, and not all of the embodiments. For those skilled in the art, other drawings obtained from these drawings without creative effort are all within the scope of protection of this application.

[0019] Figure 1 A flowchart of a microdisplay wafer grading optoelectronic testing method provided in an embodiment of this application.

[0020] Figure 2 This is a flowchart illustrating the alignment and pressing of row-level probe cards with the die to be tested in the microdisplay wafer hierarchical photoelectric testing method provided in this application embodiment.

[0021] Figure 3 This is a flowchart illustrating the process of changing the die in the row to be tested in the microdisplay wafer grading optoelectronic testing method provided in this application embodiment.

[0022] Figure 4 This is a flowchart illustrating the process of removing defective grains in the microdisplay wafer grading optoelectronic testing method provided in this application embodiment.

[0023] Figure 5 This is a schematic diagram of an optional microdisplay wafer grading optoelectronic testing device provided in an embodiment of this application.

[0024] Figure 6 for Figure 5 The image shows a top view of a microdisplay wafer grading optoelectronic testing device.

[0025] Figure 7 This is a functional block diagram of the microdisplay wafer grading optoelectronic testing system provided in an embodiment of this application.

[0026] Explanation of reference numerals in the attached figures: 10-Base; 11-Wafer carrier stage; 12-Wafer under test; 13-Probe card; 14-Test station; 15-Switching unit; 16-Adsorption component; 17-Image acquisition assembly; 18-Knockout area; 19-Guide rail. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0028] To make the description of this disclosure more detailed and complete, illustrative descriptions of the implementation methods and specific embodiments of this application are provided below; however, this is not the only form of implementing or utilizing the specific embodiments of this application. The implementation methods cover the features of multiple specific embodiments and the method steps and their order for constructing and operating these specific embodiments. However, other specific embodiments can also be used to achieve the same or equivalent functions and step sequences. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0029] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in sequences other than those illustrated or described herein.

[0030] In the description of the embodiments of this application, unless otherwise stated, " / " means "or". For example, A / B can mean A or B. The word "and / or" in the text is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of this application, "multiple" means two or more. Other quantifiers should be understood similarly. The preferred embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application. Furthermore, the embodiments of this application and the features in the embodiments can be combined with each other without conflict.

[0031] In the manufacturing process of microdisplay chips, wafer-level optoelectronic inspection is a core process for controlling chip yield. Currently, the mainstream inspection method in the industry is point-by-point probing of each die on the wafer. This involves using probes to power each die individually, sequentially testing parameters such as image quality, spectrum, viewing angle, and current-voltage characteristics. As wafer sizes continue to increase, the number of dies on a single wafer increases significantly, leading to a continuous increase in the overall testing time for a single wafer due to this die-by-die testing approach.

[0032] For a long time, the perception that yield control accuracy can only be guaranteed by performing full-parameter testing on every single die on the wafer has limited the R&D efforts of equipment manufacturers. They have consistently focused on improving single-die testing speed, failing to break free from the technical framework of full-die testing. While some solutions have attempted to increase testing speed by lighting up each row sequentially, the essence remains full-wafer, row-by-row inspection. Each die still needs to undergo a complete full-parameter testing process, thus not fundamentally reducing the testing workload.

[0033] Meanwhile, most solutions lack a pre-aging process, resulting in insufficient stability of optoelectronic test data. This makes it difficult to effectively streamline the test process while ensuring test accuracy, and fails to meet the test efficiency requirements of mass production.

[0034] In view of this, please refer to Figures 1-7 This application proposes a graded optoelectronic testing method and system for microdisplay wafers, which can reduce the time spent on point-by-point probing of the wafers and perform precise testing only on the selected target wafers, thereby improving testing efficiency while achieving automated testing.

[0035] Please refer to Figure 1 This is a flowchart of a microdisplay wafer grading photoelectric testing method provided in an embodiment of this application. The microdisplay wafer grading photoelectric testing method includes the following steps: Step S1: Obtain the device type information of the wafer under test, and call the corresponding test configuration parameters based on the device type information; In this embodiment of the application, before performing optoelectronic testing on the wafer under test, it is first necessary to obtain the device type information of the wafer under test, and then call the corresponding test configuration parameters based on the device type information.

[0036] It is understandable that different types of wafers under test have different electrical response and luminescence characteristics, and the corresponding test configuration parameters cannot be directly applied. If the same set of test configuration parameters is used to test different types of wafers under test, problems such as driver mismatch and abnormal imaging acquisition will occur, causing the acquired fast screening test data to deviate from the actual working state of the chip.

[0037] Furthermore, after obtaining the device type information of the wafer under test, the appropriate test configuration parameters are automatically called according to the device type information to ensure that the subsequent test process is compatible with the device characteristics of the wafer under test itself.

[0038] As an optional implementation, the device type information includes at least silicon-based micro LED wafers and silicon-based micro organic LED wafers, each of which is equipped with a corresponding row-level probe card and a single-crystal probe card.

[0039] In one optional embodiment, silicon-based micro LED (Micro Light Emitting Diode) wafers and silicon-based micro organic light emitting diode (Micro OLED) wafers are two mainstream types of microdisplay wafers. They differ in die size, electrode arrangement, and number of pins. The number, spacing, and arrangement of probe pins of row-level probe cards and single-die probe cards need to be adapted to the electrode structure of the corresponding wafer.

[0040] Therefore, this application provides corresponding row-level probe cards and single-die probe cards for the two types of wafers mentioned above, ensuring reliable contact between the probes and the electrodes of the die to be tested during subsequent alignment and crimping operations.

[0041] It should be noted that those skilled in the art can replace the above row-level probe cards and single-crystal probe cards with corresponding probe card types adapted to other microdisplay wafer specifications according to actual testing needs, and are not limited to the Micro LED wafers and Micro OLED wafers in the above examples.

[0042] As an optional implementation, the test configuration parameters include electrical drive parameters, optical imaging parameters, and coarse defect judgment threshold parameters that match the device type information.

[0043] In this embodiment, the test configuration parameters include electrical drive parameters, optical imaging parameters, and coarse defect judgment threshold parameters that match the device type information.

[0044] Among them, the electrical driving parameters are used to provide parameter basis for aging pretreatment and lighting electrical signals, ensuring that the electrical signal applied to the die is within the device's allowable operating range, preventing the electrical signal from being too large and causing irreversible damage to the die under test, and also avoiding the electrical signal being too small to complete aging pretreatment and lighting excitation.

[0045] Furthermore, different types of wafers under test have different brightness ranges. Matching the corresponding optical imaging parameters can ensure that the acquired appearance image and luminescence quality image are within the effective imaging range, reducing data distortion caused by overexposure or underexposure.

[0046] Furthermore, the coarse defect judgment threshold parameter can provide a numerical judgment benchmark for subsequent identification of defective dies. Since the normal operating parameter ranges of different types of wafers are inconsistent, adopting a coarse defect judgment threshold parameter that is compatible with the current device type information can improve the accuracy of subsequent marking of defective dies.

[0047] Step S2: Align and press the row-level probe card with the test row dies of the wafer under test, and perform aging pretreatment on each die in the test row dies through the row-level probe card; In this embodiment of the application, after obtaining the device type information of the wafer under test, it is necessary to determine the corresponding row-level probe card according to the device type information. During the test, the row-level probe card is kept fixed. In this application, the test row dies of the wafer under test are aligned and pressed with the row-level probe card so that the probes of the row-level probe card form reliable contact with the electrodes of each die in the test row die.

[0048] Specifically, the probe arrangement of the row-level probe card corresponds one-to-one with the electrode positions of each die in the row to be tested. After alignment and crimping are completed, current and voltage signals can be transmitted to the electrodes of each die via the probes. If the alignment and crimping are inaccurate or the contact is poor, the subsequently applied electrical signals cannot reach the die normally, the aging pretreatment and lighting operations cannot be effectively performed, and the collected rapid screening test data will also be distorted.

[0049] Understandably, after the alignment and crimping are completed, each die in the row-level probe card is subjected to aging pretreatment. Aging pretreatment involves applying specific electrical excitation to each die in the row-level probe card before the formal power-on test, so that the internal state of the die transitions from an initial unstable state to a relatively stable working state, thereby improving the reliability of subsequent test data.

[0050] As an optional implementation method, please refer to Figure 2The step of aligning and pressing the row-level probe card with the test row die of the wafer under test includes: Step S20: Retrieve the row-level probe card that matches the device type information; Step S21: Move the wafer under test so that the test row die of the wafer under test is aligned and in contact with the probe pin of the row probe card.

[0051] In this embodiment, wafers of different device types differ in die size, electrode arrangement and pin count. The number, spacing and arrangement of probe pins of the corresponding row probe cards also differ. Therefore, it is necessary to retrieve the row probe card that matches the device type based on the device type information obtained in step S1.

[0052] Furthermore, after the row-level probe card is retrieved, its position remains fixed. Alignment with the probe card is achieved by moving the wafer under test. During testing, the current row of chips to be tested needs to be moved directly below the row-level probe card, and then the wafer under test is moved vertically upwards, so that the electrodes of each chip in the row under test are aligned and in contact with the corresponding probe pins on the row-level probe card. Throughout the entire testing process, the position of the row-level probe card remains unchanged, and alignment for each row of chips is achieved by moving the wafer under test.

[0053] Specifically, after each row of chips is tested, the wafer under test is moved downwards to separate the probe from the chip electrode. Then, it moves forward one row in the horizontal plane, and then moves upwards to align the chips of the next row under test with the probe pins. This process is repeated row by row. By moving the wafer under test to achieve alignment, the alignment consistency between each row of chips and the probe card can be guaranteed.

[0054] As an optional implementation, the aging pretreatment of each grain in the row to be tested using the row-level probe card includes: An aging pulse current adapted to the device type information is synchronously applied to each die in the test row.

[0055] In this embodiment of the application, after the alignment and crimping are completed, the probes of the row-level probe card have made contact with the electrodes of each die in the row of the die to be tested. Next, the row-level probe card synchronously applies an aging pulse current to each die in the row of the die to be tested.

[0056] Furthermore, the aging pulse current is adapted to the device type information. Different types of chips have different tolerances to current amplitude, pulse width, and pulse count. The adapted pulse current parameters enable the chip to reach a relatively stable operating state in a short time. Since the probe pins of the row-level probe card correspond one-to-one with each chip in the row under test, the aging pulse current can be asynchronously distributed to all chips in the current row. This asynchronous application method can complete the aging preprocessing of a single chip in milliseconds. Compared with related technologies that apply the current to each chip sequentially after moving the probe, this reduces the total time consumption and improves the overall testing efficiency.

[0057] In an optional embodiment, this application preferably performs an electrical initialization pre-aging treatment on each die on the wafer before the wafer is first lit up or immediately after the wafer is packaged. An initialization current higher than the normal operating current is applied to each die on the wafer under test and maintained for a predetermined time to achieve the aging pre-treatment of each die.

[0058] It is understandable that after the silicon-based organic light-emitting diode (OLED) wafer is manufactured, its light-emitting units often contain a certain number of interface states and trapped charges. These defects can lead to a certain degree of instability in the initial electrical parameters and luminous efficiency of the device. By applying an initial current higher than the normal operating current, these interface states, trapped charges, and early defects can be released or eliminated under controllable conditions, thereby bringing the device's electrical parameters and luminous efficiency into a relatively stable operating range. In this way, this application can reduce the difficulty of subsequent display uniformity calibration, improve the long-term reliability of the device, and differ from the aging process during normal use.

[0059] Furthermore, after the aging pretreatment is completed, the photoelectric properties of the crystal tend to stabilize. When the lighting signal is applied and the fast screening test data is collected, the obtained electrical data and optical images can reflect the true performance of the crystal under stable working conditions, avoiding data deviation caused by unstable performance in the early stage of power-on.

[0060] Step S3: Apply a lighting electrical signal to the test row of grains after aging pretreatment, and simultaneously collect the fast screening detection data of each grain during the lighting process of the test row of grains; In this embodiment of the application, after the aging pretreatment is completed, each die in the test row has entered a relatively stable working state. At this time, a lighting electrical signal is applied to each die in the current row through the row-level probe card.

[0061] Similarly, the lighting signal is matched with the device type information. Different types of chips have different operating voltages and drive currents, and the appropriate electrical signal enables the chip to emit light normally under rated operating conditions. After the lighting signal is applied, each chip in the current row is lit up synchronously. During the lighting process, the fast screening detection data of each chip in the current row is collected synchronously.

[0062] As an optional implementation, the synchronous acquisition of rapid screening detection data of each grain during the illumination process of the grain under test includes: Simultaneously collect the appearance image data, luminescence quality image data, and basic electrical data of each grain in the test row.

[0063] It's understandable that synchronous acquisition means collecting multiple types of data within the same time window, rather than collecting them step-by-step. Since the electrical response and luminescence state of the chip occur simultaneously upon illumination, synchronous acquisition ensures that the collected data are time-aligned, reflecting the chip's overall performance under the same operating conditions. If acquisition is done step-by-step, the chip's electrical and optical parameters may drift due to different power-on times, leading to a lack of a unified benchmark for subsequent judgment.

[0064] In an optional embodiment, the rapid screening test data includes at least the appearance image data, luminescence quality image data, and basic electrical data of the crystal. The appearance image data reflects the presence of physical defects on the crystal surface, the luminescence quality image data reflects whether the crystal emits light normally when illuminated, and the basic electrical data reflects whether the internal circuitry of the crystal is conductive. All of these can serve as the basis for subsequently marking unqualified crystals.

[0065] Step S4: Replace the test row of dies, repeat the aging pretreatment and the application of the illumination electrical signal until the full wafer fast screening data integrating all row die fast screening test data is obtained; In this embodiment of the application, after the rapid screening test data acquisition of the current row of dies is completed, the test object needs to be switched to the next row of dies, and the alignment pressing and aging pretreatment in step S2 and the application of the lighting electrical signal and the synchronous acquisition of rapid screening test data in step S3 are repeated for the next row of dies.

[0066] Since the probes of the row-level probe card correspond to the electrode positions of a single row of chips, only one row of chips can be powered and data acquired at a time. After one row of chips has been tested, the next row of chips needs to be moved under the row-level probe card so that the probes can make contact with the electrodes of the next row of chips before subsequent tests can be performed.

[0067] During the row-by-row switching process, after each change of the die in the row to be tested, the entire process of aging pretreatment, applying a lighting electrical signal, and synchronously acquiring rapid screening test data is repeated. That is, each row of dies undergoes the same aging pretreatment process when entering the test, and after aging stabilization, a lighting electrical signal is applied and data acquisition is completed.

[0068] This ensures consistency in testing conditions across rows of dies, preventing discrepancies between fast screening data and other row data caused by some rows of dies not undergoing aging pretreatment. After all rows of dies on the entire wafer have completed the above operations, the fast screening data of each row of dies are integrated according to their respective row positions on the wafer to form full-wafer fast screening data that integrates the fast screening data of all rows of dies.

[0069] As an optional implementation method, please refer to Figure 3 The replacement of the test row grain includes: Step S40: Separate the row-level probe card from the current test row die; Step S41: Move the wafer under test so that the row probe card makes contact with the next row of test dies of the wafer under test.

[0070] In an optional embodiment, when replacing the die under test, the row-level probe card is first separated from the current die under test. The separation operation involves removing the probes of the row-level probe card from the electrode surface of the current die, so that the probes and electrodes are no longer in contact. After separation, the wafer under test is moved so that the row-level probe card makes contact with the next row of dies under test.

[0071] In this embodiment of the application, since the position of the row probe card remains fixed during the test, it is necessary to move the wafer under test to achieve row switching, move the next row of dies to directly below the row probe card, so that the electrodes of each die in the next row are aligned and in contact with the probes of the row probe card.

[0072] Furthermore, the separation-then-movement method of this application can avoid damage caused by the probe scratching the die surface during wafer movement. As the above replacement operation is repeated, the wafer under test completes the fast screening test row by row until all rows of dies have been tested.

[0073] Furthermore, after all rows of dies have completed rapid screening, the rapid screening data of each row of dies are integrated according to the row and column positions of the dies on the wafer to form full-wafer rapid screening data covering all row-level die rapid screening data. This full-wafer rapid screening data includes the appearance image data, luminescence image data, and basic electrical data of each die on the wafer under test during the row-level rapid screening stage.

[0074] Step S5: Based on the full wafer fast screening data, mark the grains that meet the defect judgment conditions as unqualified and remove them, and mark the target grains to be finely tested from the remaining grains according to the preset screening conditions. In this embodiment of the application, after obtaining the full wafer fast screening data, it is necessary to classify each grain according to the full wafer fast screening data. The classification is based on the appearance image data, luminescence image data and basic electrical data of each grain collected in the fast screening stage.

[0075] Specifically, it is necessary to judge each grain in the whole wafer fast screening data according to the defect judgment criteria, and mark the grains that meet the defect judgment criteria as unqualified and remove them.

[0076] As an optional implementation method, please refer to Figure 4 The step of marking and removing grains that meet the defect criteria as unqualified includes: Step S50: If the basic electrical parameters of the current grain exceed the preset threshold, it is determined that the current grain has an open circuit or a short circuit, and the current grain is marked as unqualified and removed. Step S51: If the appearance image data of the current grain indicates that the current grain has an appearance defect, then the current grain is marked as unqualified and discarded. Step S52: If the current chip is determined to have lighting failure, linear defects, or spot defects based on the current chip's luminous image quality data, then the current chip is marked as unqualified and discarded.

[0077] In an optional embodiment, the basic electrical data includes the current and voltage values ​​of each die during the lighting process. The preset thresholds are upper and lower limits of electrical parameters that match the device type information. When the current value is lower than the preset threshold, it indicates an open circuit in the die's internal circuitry, preventing normal current flow. When the current value is higher than the preset threshold, it indicates a short circuit in the die, resulting in an abnormally large current increase. These two situations correspond to open and short circuits, respectively, and are considered directly identifiable electrical defects. Dies that meet the defect criteria are marked as unqualified and discarded.

[0078] Furthermore, the appearance image data records the physical morphology of the grain surface. By analyzing this image, it is possible to identify whether the grain has appearance defects such as cracks, surface contamination, or pad misalignment. If the appearance image data of the current grain determines that the current grain has the above-mentioned appearance defects, then the current grain is marked as unqualified and rejected.

[0079] Furthermore, the luminescent image data records the luminescence performance of the chip in the lit state. By analyzing this image, it is possible to identify whether the chip has lighting failures such as full-screen non-lighting, large-area pixel failure, dark spots, bright spots, or poor lines. If the luminescent image data of the current chip determines that the current chip has the above-mentioned lighting failures, poor lines, or poor spots, then the current chip is marked as unqualified and discarded.

[0080] It is understandable that the defect judgment conditions corresponding to the above basic electrical data, appearance image data and light emission image data are independent of each other. As long as the current grain meets any one of the defect judgment conditions, it will be marked as unqualified and rejected.

[0081] As an optional implementation, the step of marking the target grains to be precisely measured from the remaining grains according to preset screening conditions includes: A preset ratio is used to extract grains that have never been rejected and have not been marked as suspected defects. The extracted grains and suspected defects are marked as target grains to be precisely tested. If the basic electrical parameters of the grain are located within a preset range of suspicious parameters, or if there are suspicious image features in the appearance image data of the grain, or if there are suspicious abnormal features in the luminescence image data of the grain, then the current grain will be marked as a suspicious defective grain.

[0082] In actual testing, although the rapid screening test data of some grains did not meet the criteria for defective grains, they also did not reach the level of normal grains, and their state was between normal and abnormal.

[0083] It is understandable that the preset screening conditions are set for these boundary state grains. This application marks grains whose basic electrical parameters are within the preset suspicious parameter range, grains with suspicious image features in appearance image data, and grains with suspicious abnormal features in luminescent image quality image data as suspicious defective grains.

[0084] For example, if a grain surface exhibits lines resembling cracks, but the width or contrast of these lines is too low to be directly identified as crack defects during rapid screening, then these lines constitute suspicious image features. Similarly, if an area resembling contamination or signs of pad misalignment appear in the appearance image, but these conditions do not reach the threshold for determining appearance defects, they also fall into the category of suspicious image features.

[0085] In luminescent images, if the brightness of a localized area of ​​a grain is lower than that of its surrounding area but it is not completely extinguished, or if an abnormal grayscale area resembling a dark or bright spot appears in the image but does not reach the threshold for determining lighting failure, then this anomaly constitutes a suspicious anomaly feature. Both the aforementioned suspicious image features and suspicious anomaly features indicate a potential risk to the grain and require confirmation through subsequent precise measurements.

[0086] Furthermore, for the grains that are not marked as unqualified or suspected defective, a portion of them are selected according to a preset ratio and marked as target grains. These target grains and the aforementioned suspected defective grains are jointly marked as target grains, to be confirmed in the subsequent precision testing stage.

[0087] As an optional implementation, if there are suspicious image features in the appearance image data of the grain, a subsurface infrared image of the current grain is acquired, and the presence and direction of subsurface crack extension in the current grain are identified based on the subsurface infrared image.

[0088] In this embodiment of the application, for grains with suspicious image features in the appearance image data, their subsurface infrared images can be further acquired in the precision measurement stage.

[0089] It is understandable that the appearance image data is a visible light image of the grain surface, which can reflect the physical morphology of the grain surface. However, for defects at the subsurface level, such as the extension of cracks located below the grain surface, visible light cannot penetrate the surface layer to identify them.

[0090] Specifically, infrared light can penetrate the shallow surface of grains. Therefore, by acquiring subsurface infrared images, structural information below the grain surface can be obtained, thereby identifying whether there are subsurface cracks extending into the current grain and the direction of the extension lines.

[0091] For example, if a suspicious line in the external image appears as a continuous image feature penetrating the interior of the grain and extending to the grain edge in the infrared image, it indicates that the crack has extended to the subsurface region, and the grain has internal structural damage. If no extending image feature is observed in the infrared image, the suspicious line is merely a surface scratch or surface crack, and has not affected the interior of the grain. The above infrared verification steps can further confirm the suspicious image features.

[0092] Step S6: Sequentially align and press the target crystal with the single-crystal probe card, and use the single-crystal probe card to perform photoelectric characteristic tests on each target crystal to obtain precise measurement data for each target crystal; In this embodiment, after the target dies are marked, each target die needs to be tested for its photoelectric properties. Since the probe arrangement of the single-die probe card corresponds to the electrode position of a single die, only one die can be powered and signal transmitted at a time. Therefore, each target die needs to be aligned and pressed onto the single-die probe card in sequence.

[0093] Furthermore, the alignment and crimping method is similar to that of row-level probe cards. The position of the single-crystal probe card remains fixed. By moving the wafer under test, the current target die is moved to a position below the single-crystal probe card, allowing the probes of the single-crystal probe card to make contact with the electrodes of the die. After each target die is aligned and crimped, the electrical signal required for testing is applied to the die through the single-crystal probe card to perform photoelectric characteristic testing and obtain precise measurement data for the die.

[0094] After the precise measurement data of the current target die is collected, the single-die probe card is separated from the die. The wafer under test is moved to move the next target die under the single-die probe card for alignment, pressing and testing. This process is repeated until all target dies have been tested.

[0095] Understandably, the rapid screening stage has already completed the acquisition of appearance images, luminescence quality images, and basic electrical parameters for each die on the entire wafer, obtaining rapid screening test data for each die. Based on this, the fine testing stage only tests the target dies, and the number of target dies is far less than the total number of dies on the entire wafer; therefore, the total time spent on the fine testing stage is controllable. Optoelectronic property testing is a further refined inspection based on row-level rapid screening, and the obtained fine testing data is used to make the final yield determination for the target dies.

[0096] As an optional implementation, the photoelectric property testing of each target grain includes: Each target crystal is sequentially subjected to image quality detection, spectral parameter testing, viewing angle characteristic testing, and current and voltage characteristic testing until the photoelectric characteristic testing of all target crystals is completed.

[0097] In the embodiments of this application, the photoelectric characteristic tests performed on each target chip include at least image quality detection, spectral parameter testing, viewing angle characteristic testing, and current and voltage characteristic testing.

[0098] Image quality inspection assesses the quality of the emitted light from the target chip when it is illuminated, including at least the detection of luminous brightness, brightness uniformity, and pixel integrity. Spectral parameter testing involves performing spectral analysis on the light emitted by the target chip to obtain parameters such as wavelength distribution, peak wavelength, and color coordinates.

[0099] Furthermore, viewing angle characteristic testing involves measuring the luminous brightness of the target chip at different angles to obtain characteristic data on how its brightness changes with the viewing angle. Current-voltage characteristic testing involves applying a varying voltage signal to the target chip and measuring the corresponding current response, or applying a varying current signal and measuring the corresponding voltage response, to obtain electrical parameters of the target chip such as driving voltage, operating current, and power consumption.

[0100] In this way, after performing the above photoelectric property tests on all target grains one by one, the precise measurement data of all target grains are obtained.

[0101] Step S7: Integrate the full wafer fast screening data with the precision measurement data of each target grain to generate the test results of the wafer to be tested.

[0102] In this embodiment, after all target dies have completed photoelectric property testing, the precise measurement data of each target die has been acquired. At this time, all test data of the wafer under test includes the whole wafer fast screening data acquired in step S4, which covers the appearance image data, light emission image quality data, and basic electrical data of all dies on the wafer under test; and the precise measurement data of each target die acquired in step S6, which covers the image quality detection results, spectral parameters, viewing angle characteristic data, and current and voltage characteristic data of each die marked as a target die.

[0103] Based on this, the above whole-wafer rapid screening data is integrated with the precision measurement data of each target grain to generate the test results of the wafer to be tested.

[0104] As an optional implementation, the generation of test results for the wafer under test includes: The test results are generated, which include the yield distribution information of each grain in the wafer under test, the coordinates of the defective grains, and the precise measurement data of each target grain.

[0105] In an optional embodiment, the test results of the wafer under test include at least the yield distribution information of each grain in the wafer under test, the coordinates of the defective grains, and the test results of the precise measurement data of each target grain.

[0106] The yield distribution information for each die reflects whether each die on the wafer under test is marked as a qualified or unqualified die. The test results should also include the location coordinates of unqualified dies, which are used to separate unqualified dies from qualified dies in subsequent wafer dicing or sorting processes.

[0107] In addition, the test results also include precise measurement data for each target die, which includes specific values ​​obtained from image quality inspection, spectral parameter testing, viewing angle characteristic testing, and current and voltage characteristic testing. At this point, the entire testing process for the wafer under test is complete.

[0108] In an optional embodiment, it can be achieved through Figure 5 and Figure 6 The microdisplay wafer grading optoelectronic testing equipment shown performs the testing methods described in the above embodiments.

[0109] In this specific embodiment, the optoelectronic testing equipment includes a base 10, and a testing station 14, a wafer carrier stage 11, a switching unit 15, and an image acquisition component 17 disposed on the base 10. The testing station 14 is equipped with a probe holder for mounting probe cards 13. The wafer carrier stage 11 includes a vacuum adsorption chuck (not shown) for adsorbing the wafer 12 to be tested, and a moving component (not shown) connected to the vacuum adsorption chuck. The moving component drives the vacuum adsorption chuck to move, thereby moving the wafer 12 to be tested below the testing station 14.

[0110] Furthermore, the optoelectronic testing equipment also includes a probe card set, which comprises at least one row-level probe card and at least one single-die probe card. The probe pins of the row-level probe card are arranged along the row direction for simultaneously supplying power to multiple dies in the same row on the wafer 12 under test; the probe pins of the single-die probe card are arranged corresponding to the electrode positions of a single die for independently supplying power and transmitting signals to a single die on the wafer 12 under test. Both the row-level probe card and the single-die probe card have a cutout area 18 that extends through the thickness direction of the probe card 13. When the probe card 13 is mounted on the probe card holder and in contact with the wafer, the main body of the probe card 13 covers the wafer, and the image acquisition component 17 can acquire the appearance image and luminous quality image of the wafer under test through the cutout area 18 without removing the probe card 13 during image acquisition.

[0111] The switching unit 15 includes an adsorption element 16, which is movably arranged along the guide rail 19. It is used to pick up the corresponding row-level probe card or single-crystal probe card as needed in the testing phase, and move the picked-up probe card 13 to the probe card holder for installation or remove it from the probe card holder.

[0112] The photoelectric testing method for microdisplay wafer grading provided in this application will be described in detail below with reference to the photoelectric testing equipment.

[0113] First, the vacuum adsorption chuck adsorbs and fixes the wafer 12 under test, and then the moving component moves the wafer 12 under test to below the test station 14. The device type information of the wafer 12 under test is obtained, and the corresponding test configuration parameters are called according to the device type information, including electrical drive parameters, optical imaging parameters and coarse defect judgment threshold parameters that match the device type.

[0114] Further, the switching unit 15, based on the device type information, uses the adsorption element 16 to pick up the corresponding row-level probe card from the probe card group and moves it to the probe card holder for installation. Subsequently, the moving component in the wafer carrier stage 11 drives the vacuum adsorption chuck to move, aligning the current row of dies on the wafer under test 12 with the probes of the row-level probe card. After alignment and pressing are completed, an aging pulse current is synchronously applied to each die in that row through the row-level probe card to complete the aging pretreatment.

[0115] After the aging pretreatment is completed, a lighting electrical signal is applied to each die in the current row through the row-level probe card to make them light up synchronously. During the lighting process, the image acquisition component 17 moves above the cutout area 18 of the row-level probe card and acquires the appearance image and luminous quality image of each die in the current row through the cutout area 18, and simultaneously acquires the basic electrical data of each die.

[0116] After the fast screening test data of the current row of dies is acquired, the moving component drives the vacuum adsorption chuck to move downwards to separate the probe from the electrode of the current row of dies. Then, it steps one row in the horizontal plane and moves upwards to align and contact the probe of the row probe card with the next row of dies. The aging pretreatment, the application of the lighting electrical signal and the synchronous acquisition of fast screening test data are repeated for the next row of dies until all rows of dies have completed the fast screening test. The fast screening test data of each row of dies are then integrated into the whole wafer fast screening data.

[0117] Furthermore, based on the basic electrical data, appearance image data, and luminescence image data in the whole wafer fast screening data, the grains that meet the defect judgment criteria are marked as unqualified and removed. According to the preset screening conditions, the grains whose basic electrical parameters are in the suspicious parameter range, whose appearance image data has suspicious image features, and whose luminescence image data has suspicious abnormal features are marked as suspicious defective grains. The suspicious defective grains and the grains that have never been removed and have not been marked as suspicious defects are jointly marked as target grains to be precisely tested.

[0118] Based on this, the switching unit 15 uses the adsorption component 16 to remove the row-level probe card from the probe card holder, and then picks up the corresponding single-crystal probe card and moves it onto the probe card holder for installation. The moving component moves the current target crystal to the bottom of the single-crystal probe card for alignment and pressing. The single-crystal probe card is used to perform image quality detection, spectral parameter testing, viewing angle characteristic testing, and current-voltage characteristic testing on the target crystal to obtain precise measurement data for the target crystal. After the current target crystal is tested, the same test is performed on the next target crystal in sequence until all target crystals have been precisely measured.

[0119] Furthermore, the data from the full wafer rapid screening is integrated with the precise measurement data of each target die to generate the test results for wafer 12. These test results include the yield distribution information of each die, the location coordinates of defective dies, and the precise measurement data of each target die.

[0120] At this point, the entire testing process for the current wafer 12 is completed. The current wafer 12 is removed from the vacuum adsorption chuck and unloaded. Then, the next wafer 12 is placed on the vacuum adsorption chuck, and the above steps are repeated to begin the graded optoelectronic testing of the next wafer 12.

[0121] It should be noted that the aforementioned testing equipment is only used to explain and illustrate the method provided in this application, demonstrating that the method has hardware support in actual testing. Those skilled in the art can use other testing equipment structures capable of switching between row-level probe cards and single-chip probe cards, as well as image acquisition functions, to execute the method steps of this application.

[0122] Furthermore, the graded photoelectric testing method provided in this application does not depend on the testing equipment with the specific structure described above. Any equipment structure capable of implementing the same testing process can be used to implement the method of this application, as should be known by those skilled in the art.

[0123] Based on the above-described microdisplay wafer hierarchical optoelectronic testing method, please refer to... Figure 7 This application also provides a micro-display wafer grading optoelectronic testing system, comprising: The calling module is used to obtain the device type information of the wafer under test and call the corresponding test configuration parameters based on the device type information; The aging module is used to align and press the row-level probe card with the test row dies of the wafer under test, and to perform aging pretreatment on each die in the test row dies through the row-level probe card. The acquisition module is used to apply a lighting electrical signal to the test row of grains after aging pretreatment, and simultaneously acquire the fast screening detection data of each grain during the lighting process of the test row of grains; The execution module is used to replace the test row of dies, repeat the aging pretreatment and the application of the lighting electrical signal until the full wafer fast screening data integrating all row die fast screening test data is obtained; The marking module is used to mark and remove grains that meet the defect judgment conditions based on the full wafer fast screening data, and to mark the target grains to be finely tested from the remaining grains according to the preset screening conditions. The testing module is used to sequentially align and press the target dies with the single-die probe card, and then use the single-die probe card to test the photoelectric properties of each target die to obtain precise measurement data for each target die. An integration module is used to integrate the full wafer rapid screening data with the precision measurement data of each target grain to generate the test results of the wafer to be tested.

[0124] For other details regarding the implementation of the above technical solution by the micro-display wafer hierarchical optoelectronic testing system, please refer to the description in the micro-display wafer hierarchical optoelectronic testing method provided in the above application embodiments, which will not be repeated here.

[0125] This application provides a microdisplay wafer hierarchical photoelectric testing method and system. After aligning and pressing row-level probe cards with the dies in the row to be tested, the row-level probe cards perform aging pretreatment on each die in the current row. Then, a lighting signal is applied, and rapid screening data for each die is simultaneously acquired during the lighting process. After completing one row, the process is repeated for the next row, performing the aging pretreatment and applying the lighting signal until full-wafer rapid screening data is obtained. Based on the full-wafer rapid screening data, dies that meet the defect judgment criteria are marked as unqualified and removed. Target dies to be precisely tested are then marked from the remaining dies according to preset screening conditions. The target dies are sequentially aligned and pressed with single-die probe cards, and photoelectric characteristic tests are performed to obtain precise measurement data for each target die. Finally, the full-wafer rapid screening data and precise measurement data are integrated to generate the test results.

[0126] In this way, the row-level probe card can simultaneously power and acquire data from the entire row of chips, significantly reducing the time required for preliminary testing compared to chipping each chip individually. Aging pretreatment ensures the chips reach a stable state before testing, guaranteeing the reliability of the rapid screening data. During the rapid screening stage, coarse defective chips are removed, and only suspected defective chips and a predetermined proportion of good chips are sent to the precision testing stage. This avoids high-precision testing resources being consumed by a large number of coarse defect screenings, while ensuring the accuracy of yield assessment for target chips in the precision testing stage, thereby improving testing efficiency while maintaining yield control accuracy.

[0127] It should be noted that, in the several embodiments provided in this application, it should be understood that the disclosed devices, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed between each other can be through some interfaces, or indirect coupling or communication connection between devices or units, and can be electrical, mechanical, or other forms.

[0128] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0129] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for hierarchical photoelectric testing of microdisplay wafers, characterized in that, Includes the following steps: Obtain the device type information of the wafer under test, and call the corresponding test configuration parameters based on the device type information; The row-level probe card is aligned and pressed with the test row dies of the wafer under test, and the aging pretreatment of each die in the test row dies is performed through the row-level probe card. An illumination electrical signal is applied to the test row of grains after aging pretreatment, and rapid screening detection data of each grain is collected simultaneously during the illumination process of the test row of grains. Replace the test row of the die, repeat the aging pretreatment and the application of the lighting electrical signal until the full wafer fast screening data integrating all row die fast screening test data is obtained; Based on the whole wafer fast screening data, the grains that meet the defect judgment conditions are marked as unqualified and removed, and the target grains to be finely tested are marked from the remaining grains according to the preset screening conditions. The target crystals are sequentially aligned and pressed with the single-crystal probe cards. The photoelectric properties of each target crystal are then tested using the single-crystal probe cards to obtain precise measurement data for each target crystal. The test results of the wafer to be tested are generated by integrating the full wafer rapid screening data with the precision measurement data of each target grain.

2. The microdisplay wafer hierarchical photoelectric testing method as described in claim 1, characterized in that, The device type information includes at least silicon-based micro LED wafers and silicon-based micro organic LED wafers, and both the silicon-based micro LED wafers and silicon-based micro organic LED wafers are equipped with corresponding row-level probe cards and single-crystal probe cards.

3. The microdisplay wafer hierarchical photoelectric testing method as described in claim 1, characterized in that, The aging pretreatment of each grain in the row to be tested using the row-level probe card includes: An aging pulse current adapted to the device type information is synchronously applied to each die in the test row.

4. The microdisplay wafer hierarchical photoelectric testing method as described in claim 1, characterized in that, The synchronous acquisition of rapid screening detection data for each grain during the illumination process of the grain under test includes: Simultaneously collect the appearance image data, luminescence quality image data, and basic electrical data of each grain in the test row.

5. The microdisplay wafer hierarchical photoelectric testing method as described in claim 4, characterized in that, The step of marking and removing grains that meet the defect criteria as unqualified includes: If the basic electrical parameters of the current grain exceed the preset threshold, it is determined that the current grain has an open circuit or a short circuit, and the current grain is marked as unqualified and removed. If the appearance image data of the current grain indicates that the current grain has an appearance defect, then the current grain is marked as unqualified and discarded. If the current chip is determined to have lighting failure, linear defects, or spot defects based on the luminous image quality data of the current chip, then the current chip will be marked as unqualified and discarded.

6. The microdisplay wafer hierarchical photoelectric testing method as described in claim 5, characterized in that, The step of marking the target grains to be precisely tested from the remaining grains according to preset screening conditions includes: A preset ratio is used to extract grains that have never been rejected and have not been marked as suspected defects. The extracted grains and suspected defects are marked as target grains to be precisely tested. If the basic electrical parameters of the grain are located within a preset range of suspicious parameters, or if there are suspicious image features in the appearance image data of the grain, or if there are suspicious abnormal features in the luminescence image data of the grain, then the current grain will be marked as a suspicious defective grain.

7. The microdisplay wafer hierarchical photoelectric testing method as described in claim 6, characterized in that, If there are suspicious image features in the appearance image data of the grain, then the subsurface infrared image of the current grain is acquired, and the presence and direction of subsurface crack extension are identified based on the subsurface infrared image.

8. The microdisplay wafer hierarchical photoelectric testing method as described in claim 1, characterized in that, The photoelectric property testing of each target grain includes: Each target crystal is sequentially subjected to image quality detection, spectral parameter testing, viewing angle characteristic testing, and current and voltage characteristic testing until the photoelectric characteristic testing of all target crystals is completed.

9. The microdisplay wafer hierarchical photoelectric testing method as described in claim 1, characterized in that, The test results generated for the wafer under test include: The test results are generated, which include the yield distribution information of each grain in the wafer under test, the coordinates of the defective grains, and the precise measurement data of each target grain.

10. A microdisplay wafer grading optoelectronic testing system, characterized in that, include: The calling module is used to obtain the device type information of the wafer under test and call the corresponding test configuration parameters based on the device type information; The aging module is used to align and press the row-level probe card with the test row dies of the wafer under test, and to perform aging pretreatment on each die in the test row dies through the row-level probe card. The acquisition module is used to apply a lighting electrical signal to the test row of grains after aging pretreatment, and simultaneously acquire the fast screening detection data of each grain during the lighting process of the test row of grains; The execution module is used to replace the test row of dies, repeat the aging pretreatment and the application of the lighting electrical signal until the full wafer fast screening data integrating all row die fast screening test data is obtained; The marking module is used to mark and remove grains that meet the defect judgment conditions based on the full wafer fast screening data, and to mark the target grains to be finely tested from the remaining grains according to the preset screening conditions. The testing module is used to sequentially align and press the target dies with the single-die probe card, and then use the single-die probe card to test the photoelectric properties of each target die to obtain precise measurement data for each target die. An integration module is used to integrate the full wafer rapid screening data with the precision measurement data of each target grain to generate the test results of the wafer to be tested.

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