Metal gate connection hole and method of manufacturing the same, semiconductor processing equipment
Patent Information
- Application Number
- CN202610912480.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-06-23
- Publication Date
- 2026-11-03
AI Technical Summary
In semiconductor technology, the RC time delay phenomenon of metal electrodes is severe, especially under small size conditions. The presence of the adhesion layer leads to increased resistance and affects device performance.
A first metal layer is pre-formed on top of the metal gate as a seed layer. By selectively depositing a second metal layer, the adhesion layer is eliminated, and the preparation method of the metal gate connection hole is optimized. The structure of the bottom and sidewall of the trench is changed by the first metal layer, so that the second metal layer is deposited only in the trench.
It significantly reduces the resistance of the connection holes, improves the RC delay phenomenon in the circuit, and enhances the performance of the device.
Smart Images
Figure CN123035940A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and more specifically, to a metal gate interconnection hole, its preparation method, and semiconductor process equipment. Background Technology
[0002] With the development of semiconductor technology, the number of transistors that can be accommodated per unit area of a chip is constantly increasing, and various key structures are also shrinking. Under small size conditions, the resistance of metal electrodes increases significantly due to the size effect. Therefore, the RC time delay phenomenon caused by the coupling effect of resistance and capacitance becomes more and more serious.
[0003] In related technologies, chemical vapor deposition is generally used for metal deposition. Before depositing the metal electrode, an adhesion layer needs to be deposited to prevent the metal from cracking. However, the presence of the adhesion layer will increase the resistance, aggravate the RC delay, and affect the device performance. Summary of the Invention
[0004] The purpose of this invention is to provide a metal gate interconnect and its preparation method, as well as semiconductor process equipment, to improve the technical problem of severe RC time delay in metal gate interconnects in related technologies.
[0005] The method for preparing a metal gate interconnection hole provided by the present invention includes: A gate stack is provided, the gate stack comprising a metal gate and a metal front dielectric layer, wherein the metal front dielectric layer and the metal gate are arranged alternately. A first metal layer is formed on top of the metal gate; A dielectric capping layer and an intermetallic dielectric layer are formed sequentially from bottom to top on the upper surfaces of both the metal front dielectric layer and the first metal layer, and the dielectric capping layer and the intermetallic dielectric layer are patterned to form a trench that exposes the first metal layer. A second metal layer is selectively deposited within the trench to form a metal electrode.
[0006] Preferably, as one possible implementation, in the provided gate stack, the top surface of the metal gate is flush with the top surface of the metal front dielectric layer; the formation of a first metal layer on top of the metal gate includes: A portion of the material of the metal gate is removed to reduce the height of the metal gate, so that the upper surface of the metal gate is lower than the upper surface of the metal front dielectric layer, and a groove is formed between the metal front dielectric layers. The first metal layer is formed within the groove; wherein the top surface of the first metal layer is flush with the top surface of the metal front medium.
[0007] Preferably, as one possible implementation, forming the first metal layer within the groove includes: The first metal layer is formed on the gate stack; Remove the portion of the first metal layer that is above the metal front dielectric layer.
[0008] Preferably, as one possible implementation, after forming the groove and before forming the first metal layer, the method further includes: The edges and corners of the metal front dielectric layer are softened to make the opening of the groove flared.
[0009] Preferably, as one possible implementation, after softening the corners and before forming the first metal layer, the method further includes: A supplementary dielectric layer is formed on the gate stack; Remove the supplementary dielectric layer covering the top of the metal gate and the top of the metal front dielectric layer, and retain the supplementary dielectric layer covering the sidewall of the recess.
[0010] Preferably, as one possible implementation, a dry etching process is used to soften the edges and corners; And / or, the supplementary dielectric layer is formed using a plasma-enhanced atomic layer deposition process; And / or, an anisotropic plasma etching process is used to remove the supplementary dielectric layer covering the middle of the metal gate and above the metal front dielectric layer; And / or, the material of the supplementary dielectric layer is silicon nitride, silicon oxide, and / or silicon oxynitride; And / or, the thickness of the supplementary dielectric layer formed on the gate stack is 2~5 nm.
[0011] Preferably, as one possible implementation, in the step of softening the corners of the metal front dielectric layer, the process gas includes Ar, the gas flow rate is 5~20 sccm, the process temperature is 0~40℃, the process pressure is 0~50 mtorr, the source RF power is 0~300W, and the bias RF power is 0~500W. And / or, in the step of forming a supplementary dielectric layer on the gate stack, the process gas includes SiH2Cl2, N2 and Ar, the gas flow rate is 5~20 slm, the process temperature is 300~500℃, the process pressure is 1~20 torr, and the RF power is 300~580W. And / or, in the step of removing the supplementary dielectric layer covering the top of the metal gate and the top of the metal front dielectric layer, the process gas includes CF4 and Ar, the gas flow rate is 5~50 sccm, the process temperature is -10~20℃, the process pressure is 0~20 mtorr, the source RF power is 0~300W, and the bias RF power is 0~100W.
[0012] Preferably, as one possible implementation, the first metal layer is formed using a physical vapor deposition process; And / or, the material of the first metal layer is ruthenium, cobalt, or ruthenium; And / or, the dielectric capping layer is formed using a plasma-enhanced chemical vapor deposition process; and / or, the material of the dielectric capping layer is silicon nitride or silicon oxynitride; And / or, the intermetallic dielectric layer is formed using a plasma-enhanced chemical vapor deposition process; and / or, the material of the intermetallic dielectric layer is an oxide or a nitride.
[0013] Preferably, as one possible implementation, the depth of the groove is 5~20nm and the aspect ratio is 0.4~1; And / or, the thickness of the first metal layer formed on the gate stack is 100~200nm.
[0014] Preferably, as one possible implementation, a dry etching process is used to remove part of the material of the metal gate to form the groove; And / or, the first metal layer is planarized using a chemical mechanical polishing process to remove the portion of the first metal layer that is above the metal front dielectric layer, so that the upper surface of the first metal layer is flush with the upper surface of the metal front dielectric layer.
[0015] Preferably, as one possible implementation, in the step of removing part of the material from the metal gate, the process gas is a halogen gas, the halogen gas includes BCl3 and / or CF4, the gas flow rate is 5~50 sccm, the process temperature is -10~20℃, the process pressure is 0~50 mtorr, the source RF power is 0~1000W, and the bias RF power is 0~100W; And / or, in the step of forming the first metal layer on the gate stack, the process gas includes tungsten hexafluoride and any one of silane and borane, the gas flow rate is 5~20 slm, the process temperature is 200~400°C, and the process pressure is 1~20 torr.
[0016] The metal gate connection hole provided by the present invention is prepared by any of the above-described methods.
[0017] The semiconductor process equipment provided by the present invention includes a process chamber, an air intake assembly, an upper electrode assembly, a lower electrode assembly, and a controller. The controller is characterized in that it includes at least one processor and at least one memory, wherein the memory stores a computer program, and the computer program, when executed by the processor, implements the method for preparing the metal gate interconnect as described above.
[0018] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention pre-forms a first metal layer on top of the metal gate to serve as a seed layer, thereby enabling the selective deposition of a second metal layer within the channel. Before depositing the second metal layer, pretreatment can alter the dangling bonds of the first metal layer at the bottom of the trench, the dielectric capping layer on the trench sidewalls, and the intermetallic dielectric layer. This ensures that the second metal layer can only be deposited starting from the seed layer, without being deposited on the dielectric capping layer and the intermetallic dielectric layer, thus achieving selective deposition. Consequently, there is no need to consider the lattice compatibility between the second metal layer and the dielectric capping layer and the intermetallic dielectric layer, eliminating the need for an adhesion layer and allowing all vias to be filled with metal. Therefore, via resistance can be significantly reduced, RC delay in the circuit can be improved, and device performance can be enhanced. Attached Figure Description
[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0020] Figure 1 This is a schematic diagram of the structure of a metal gate connection hole in related technologies; Figure 2 A schematic flowchart illustrating the method for preparing a metal gate interconnection hole according to an embodiment of the present invention; Figures 3-9 This is a schematic diagram of the corresponding steps in the method for preparing a metal gate connection hole provided in an embodiment of the present invention; Figure 10 This is a schematic diagram of the structure of the metal gate connection hole provided in an embodiment of the present invention; Figure 11 This is a schematic diagram of the structure of a semiconductor process equipment provided in an embodiment of the present invention. Detailed Implementation
[0021] In the 22nm and above technology generations, planar transistor structures can meet device requirements; however, in the 3-22nm technology generations, the short-channel effect severely affects device performance, forcing the device structure to change from planar to FinFET (Fin Field Effect Transistor).
[0022] See Figure 1 In related technologies, a dielectric capping layer 120 and an intermetallic dielectric layer 130 are first deposited on the gate stack 110, and then a metal electrode connection hole structure is formed through photolithography, etching and other processes. Since the metal gate 111 formed by various dielectrics and metals is below the metal electrode 140, an adhesion layer 150 (a Ti / TiN combination layer) needs to be deposited first, and then the metal electrode 140 is deposited. The adhesion layer 150 is used as a transition layer between the metal electrode 140 and the dielectric (including the intermetallic dielectric 130 and the dielectric capping layer 120). The adhesion layer 150 has a good lattice fit with both the dielectric and the metal. Therefore, the metal electrode 140 will not suffer from excessive stress due to lattice mismatch, which can solve the problem of cracking of the metal electrode 140.
[0023] However, the presence of the adhesion layer 150 increases the via resistance and degrades device performance. Especially at 5nm and more advanced technology nodes, the via size on the metal gate 111 needs to be below 16nm to reduce the risk of short circuits between adjacent metal electrodes 140. At this size, the adhesion layer 150 thickness is 2-3nm, with Ti around 1nm and TiN around 2nm, while the metal fill size is only around 13nm, significantly increasing the via resistance and reducing device performance. This leads to a substantial increase in resistance. Therefore, in advanced processes, optimizing the RC delay phenomenon in the circuit is crucial for improving device performance.
[0024] This invention proposes a method for preparing metal gate interconnects that eliminates the need for an adhesion layer and optimizes device performance.
[0025] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0026] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings.
[0027] Figure 2 This is a schematic flowchart illustrating a method for fabricating a metal gate interconnect via according to an embodiment of the present invention. The method includes: S102 provides a gate stack, which includes a metal gate and a metal front dielectric layer, with the metal front dielectric layer and the metal gate arranged alternately.
[0028] The structure of the gate stack is as follows: Figure 3 As shown.
[0029] S104, a first metal layer is formed on top of the metal gate.
[0030] S106, a dielectric capping layer and an intermetallic dielectric layer are formed sequentially from bottom to top on the upper surfaces of both the metal front dielectric layer and the first metal layer, and the dielectric capping layer and the intermetallic dielectric layer are patterned to form a trench that exposes the first metal layer.
[0031] See Figure 10 The dielectric capping layer 230 can be formed by plasma-enhanced chemical vapor deposition, and its material can be silicon nitride or silicon oxynitride; the intermetallic dielectric layer 212 can be formed by plasma-enhanced chemical vapor deposition, and its material can be oxide or nitride.
[0032] S108, a second metal layer is selectively deposited in the trench to form a metal electrode.
[0033] The material of the second metal layer 250 can be a dock.
[0034] In this embodiment, a first metal layer 220 is formed on top of the metal gate 211 in the gate stack 210 beforehand, so as to use the first metal layer 220 as a seed layer, thereby making it possible to selectively deposit the second metal layer 250 in the channel. Before depositing the second metal layer 250, the dangling bonds of the first metal layer 220 at the bottom of the trench and the dielectric capping layer 230 and the intermetallic dielectric layer 240 on the sidewall of the trench can be changed through pretreatment, so that the second metal layer 250 can only be deposited from the seed layer and will not be deposited on the dielectric capping layer 230 and the intermetallic dielectric layer 240, thus forming selective deposition. In this way, there is no need to consider the lattice adaptation problem between the second metal layer 250 and the dielectric capping layer 230 and the intermetallic dielectric layer 240, thereby eliminating the need for an adhesion layer and making the interconnects completely filled with metal. Therefore, the interconnect resistance can be significantly reduced, the RC delay phenomenon in the circuit can be improved, and the device performance can be enhanced.
[0035] See Figure 3 In fact, in the gate stack 210 provided in step S102 above, the top surface of the metal gate 211 is flush with the top surface of the metal front dielectric layer 212. Based on this, step S104 above may specifically include: removing part of the material of the metal gate 211 to reduce the height of the metal gate 211, so that the upper surface of the metal gate 211 is lower than the upper surface of the metal front dielectric layer 212, thereby forming a groove 213 between the metal front dielectric layers 212, forming a... Figure 4 The structure shown; subsequently, a first metal layer 220 can be formed in the groove 213, and the top surface of the first metal layer 220 is flush with the top surface of the metal front dielectric layer 212, forming as shown. Figure 9 The structure shown means that the first metal layer 220 only covers the top of the metal gate 211 and does not cover the metal front dielectric 212, thus meeting the structural requirements.
[0036] Specifically, a dry etching process can be used to remove part of the material from the metal gate 211 to form a groove 213. The process gas is a halogen gas, such as BCl3, CF4, or a combination of both, with a gas flow rate of 5~50 sccm, a process temperature of -10~20℃, a process pressure of 0~50 mtorr, a source RF power of 0~1000W, and a bias RF power of 0~100W. Under these process conditions, etching of the metal gate 211 can be achieved, and the depth of the groove 213 formed by etching can be controlled by controlling the etching time.
[0037] Preferably, see Figure 8 and Figure 9 First, a first metal layer 220 can be formed on the gate stack 210, and then the portion of the first metal layer 220 above the metal front dielectric layer 212 can be removed. Thus, the remaining first metal layer 220 will be entirely contained within the groove 213 at the top of the metal gate 211, achieving the aforementioned objective. It should be noted that compared to directly forming the first metal layer 220 locally within the groove 213, the process of completely covering the top of the gate stack 210 with the first metal layer 220 is more feasible, and the presence of the groove 213 reduces the difficulty of removing excess first metal layer 220. The material of the first metal layer 220 can be selected from ruthenium, cobalt, or ruthenium. These materials have low resistivity, are not easily diffused, and are resistant to high temperatures, meeting the performance requirements of the first metal layer 220. Preferably, the material of the first metal layer 220 is ruthenium.
[0038] Specifically, a physical vapor deposition process can be used to deposit the first metal layer 220, which helps to optimize the purity and improve the conductivity of the first metal layer 220, thereby further reducing the resistance of the interconnect. The process gas includes tungsten hexafluoride and any one of silane and borane, with a gas flow rate of 5~20 slm, a process temperature of 200~400℃, and a process pressure of 1~20 torr. Under these process conditions, the metal dock can be deposited to obtain the first metal layer 220.
[0039] Preferably, the depth of the groove 213 can be set to 5~20nm and the aspect ratio is 0.4~1. At this lower aspect ratio, the difficulty of filling the first metal layer 220 into the groove 213 can be reduced; especially for physical vapor deposition process, the low aspect ratio can ensure the compactness of the filling of the first metal layer 220 in the groove 213.
[0040] Specifically, the thickness of the first metal layer 220 formed on the gate stack 210 can be 100~200nm.
[0041] Specifically, a chemical mechanical polishing process can be used to planarize the first metal layer 220 and stop at the metal pre-dielectric layer 212 to remove the portion of the first metal layer 220 that is higher than the metal pre-dielectric layer 212, so that the upper surface of the first metal layer 220 is flush with the upper surface of the metal pre-dielectric layer 212.
[0042] After forming the groove 213 and before forming the first metal layer 220, the method provided in this embodiment may further include: softening the edges and corners of the metal pre-dielectric layer 212 to make the opening of the groove 213 flared out, forming a shape such as... Figure 5 The structure shown facilitates the subsequent filling of the first metal layer 220 into the groove 213. Specifically, a dry etching process can be used to soften the edges and corners. The process gas includes Ar, the gas flow rate is 5~20 sccm, the process temperature is 0~40℃, the process pressure is 0~50 mtorr, the source RF power is 0~300W, and the bias RF power is 0~500W. Under these process conditions, dry etching of the metal front dielectric layer 212 can be achieved, softening the edges and corners, increasing the sidewall inclination angle of the groove 213, and making the opening of the groove 213 flared.
[0043] See Figure 6 and Figure 7 Before forming the first metal layer 220 after softening the corners, the method provided in this embodiment further includes: forming a supplementary dielectric layer 260 on the gate stack 210; removing the supplementary dielectric layer 260 covering the top of the metal gate 211 and the top of the metal front dielectric layer 212, and retaining the supplementary dielectric layer 260 covering the sidewalls of the recess 213. This reduces the opening of the recess 213, preventing short circuits between the metal gate 211 and the adjacent source / drain electrode metal lines due to an excessively large opening, thus ensuring circuit effectiveness. Specifically, the material of the supplementary dielectric layer 260 can be selected as any one or a combination of silicon nitride, silicon oxide, and silicon oxynitride, thereby enabling it to function as a dielectric layer.
[0044] Specifically, a supplementary dielectric layer 260 can be formed on the gate stack 210 using a plasma-enhanced atomic layer deposition process. The process gases include SiH2Cl2, N2, and Ar, with a gas flow rate of 5~20 slm, a process temperature of 300~500℃, a process pressure of 1~20 torr, and a radio frequency power of 300~580W. Under these process conditions, the material of the deposited supplementary dielectric layer 260 meets the above requirements.
[0045] Specifically, an anisotropic plasma etching process can be used to etch the supplementary dielectric layer 260. Under this process, the plasma etching rate of the supplementary dielectric layer 260 covering the middle of the metal gate 211 and above the metal front dielectric layer 212 is faster, while the etching rate of the supplementary dielectric layer 260 covering the sidewalls of the recess 213 is slower. Therefore, after all the supplementary dielectric layer 260 covering the middle of the metal gate 211 and above the metal front dielectric layer 212 is etched away, a certain thickness of the supplementary dielectric layer 260 will still remain on the sidewalls of the recess 213. Thus, the purpose of retaining the supplementary dielectric layer 260 only at the sidewalls of the recess 213 can be achieved. The process gases include CF4 and Ar, with a gas flow rate of 5~50 sccm, a process temperature of -10~20℃, a process pressure of 0~20 mtorr, a source RF power of 0~300W, and a bias RF power of 0~100W. Under these process conditions, the aforementioned anisotropic plasma etching effect can be achieved.
[0046] Preferably, the thickness of the supplementary dielectric layer 260 formed on the gate stack 210 can be set to 2~5nm. At this thickness, the supplementary dielectric layer 260 that is finally left on the sidewall of the groove 213 can meet the requirements for the reduction of the opening of the groove 213, so that the metal gate 211 and the adjacent source and drain electrode metal lines will not be short-connected.
[0047] See Figure 3 The aforementioned gate stack 210 can be formed by first depositing a silicon dioxide layer 280, a source / drain epitaxial layer 290 and a metal front dielectric layer 212 on a substrate 270 in sequence, then removing the dummy gate, filling the metal gate 211, and finally performing chemical mechanical polishing.
[0048] Figure 10 This is a schematic diagram of a metal gate connection hole provided in an embodiment of the present invention. The metal gate connection hole is prepared by the metal gate connection hole preparation method in any of the above embodiments.
[0049] The metal gate connection hole provided in this embodiment is made by the metal gate connection hole preparation method in any of the above embodiments, and therefore has all the advantages of any of the above embodiments. It has low resistance, improves the RC delay phenomenon in the circuit, and can improve device performance.
[0050] Figure 11 A semiconductor process apparatus provided in one embodiment of the present invention includes a process chamber 310, an inlet assembly 320, an upper electrode assembly 330, a lower electrode assembly 340, and a controller. Figure 11 (Not shown in the diagram). The controller includes at least one processor and at least one memory, in which a computer program is stored, which, when executed by the processor, implements the method of any of the above embodiments.
[0051] For example, the controller can be a host computer or a slave computer. The controller can open the valve of the air inlet assembly 320 to introduce the corresponding process gas into the process chamber 310; the controller can also control the flow rate of the process gas by controlling the opening and closing degree of the valve of the air inlet assembly 320. The controller can also control the air extraction assembly 350 to extract air from the process chamber 310, thereby controlling the gas pressure inside the process chamber 310 and removing reaction byproducts.
[0052] The upper electrode assembly 330 includes an RF coil 331, an upper RF power supply 332, and an upper matching unit 333. The controller is also used to control the upper RF power supply 332 to provide upper electrode power to the RF coil 331 through the upper matching unit 333, so that the RF coil 331 excites the process gas inside the process chamber 310 to generate plasma.
[0053] The lower electrode assembly 340 includes a wafer carrier 341, a lower RF power supply 342, and a lower matching unit 343. The controller further controls the lower RF power supply 342 to provide lower electrode power to the lower electrode of the wafer carrier 341 through the lower matching unit 343, thereby providing an RF bias voltage to the lower electrode of the wafer carrier 341 to adsorb plasma above the target film layer and bombard the target film layer. The wafer carrier 341 includes an electrostatic chuck.
[0054] The semiconductor process equipment in this application embodiment can be either an inductively coupled plasma (ICP) etching apparatus or a capacitively coupled plasma (CCP) etching apparatus. This application embodiment does not limit the type of semiconductor process equipment.
[0055] The semiconductor process equipment provided in this embodiment of the invention has the same technical features as the method for preparing metal gate interconnects provided in the above embodiments, so it can also solve the same technical problems and achieve the same technical effects.
[0056] This embodiment also provides a machine-readable storage medium storing machine-executable instructions. When the machine-executable instructions are called and executed by a processor, the machine-executable instructions cause the processor to implement the above-described method for preparing the metal gate connection hole.
[0057] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the above-described equipment and apparatus can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.
[0058] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes: USB flash drives, portable hard drives, and read-only memory (ROM). Various media that can store program code, such as random access memory (RAM), magnetic disks, or optical disks.
[0059] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method for preparing a metal gate interconnect, characterized in that, include: A gate stack is provided, the gate stack comprising a metal gate and a metal front dielectric layer, wherein the metal front dielectric layer and the metal gate are arranged alternately. A first metal layer is formed on top of the metal gate; A dielectric capping layer and an intermetallic dielectric layer are formed sequentially from bottom to top on the upper surfaces of both the metal front dielectric layer and the first metal layer, and the dielectric capping layer and the intermetallic dielectric layer are patterned to form a trench that exposes the first metal layer. A second metal layer is selectively deposited within the trench to form a metal electrode.
2. The method for preparing a metal gate connection hole according to claim 1, characterized in that, In the provided gate stack, the top surface of the metal gate is flush with the top surface of the metal front dielectric layer; the formation of a first metal layer on top of the metal gate includes: A portion of the material of the metal gate is removed to reduce the height of the metal gate, so that the upper surface of the metal gate is lower than the upper surface of the metal front dielectric layer, and a groove is formed between the metal front dielectric layers. The first metal layer is formed within the groove; wherein the top surface of the first metal layer is flush with the top surface of the metal front medium.
3. The method for preparing a metal gate connection hole according to claim 2, characterized in that, The formation of the first metal layer within the groove includes: The first metal layer is formed on the gate stack; Remove the portion of the first metal layer that is above the metal front dielectric layer.
4. The method for preparing a metal gate connection hole according to claim 2, characterized in that, After forming the groove and before forming the first metal layer, the method further includes: The edges and corners of the metal front dielectric layer are softened to make the opening of the groove flared.
5. The method for preparing a metal gate connection hole according to claim 4, characterized in that, After softening the corners and before forming the first metal layer, the method further includes: A supplementary dielectric layer is formed on the gate stack; Remove the supplementary dielectric layer covering the top of the metal gate and the top of the metal front dielectric layer, and retain the supplementary dielectric layer covering the sidewall of the recess.
6. The method for preparing a metal gate connection hole according to claim 5, characterized in that, The edges and corners are softened using a dry etching process; And / or, the supplementary dielectric layer is formed using a plasma-enhanced atomic layer deposition process; And / or, an anisotropic plasma etching process is used to remove the supplementary dielectric layer covering the middle of the metal gate and above the metal front dielectric layer; And / or, the material of the supplementary dielectric layer is silicon nitride, silicon oxide, and / or silicon oxynitride; And / or, the thickness of the supplementary dielectric layer formed on the gate stack is 2~5 nm.
7. The method for preparing a metal gate connection hole according to claim 5, characterized in that, In the step of softening the corners of the metal front dielectric layer, the process gas includes Ar, the gas flow rate is 5~20 sccm, the process temperature is 0~40℃, the process pressure is 0~50 mtorr, the source RF power is 0~300W, and the bias RF power is 0~500W. And / or, in the step of forming a supplementary dielectric layer on the gate stack, the process gas includes SiH2Cl2, N2 and Ar, the gas flow rate is 5~20 slm, the process temperature is 300~500℃, the process pressure is 1~20 torr, and the RF power is 300~580W. And / or, in the step of removing the supplementary dielectric layer covering the top of the metal gate and the top of the metal front dielectric layer, the process gas includes CF4 and Ar, the gas flow rate is 5~50 sccm, the process temperature is -10~20℃, the process pressure is 0~20 mtorr, the source RF power is 0~300W, and the bias RF power is 0~100W.
8. The method for preparing a metal gate interconnect according to any one of claims 1-7, characterized in that, The first metal layer is formed using a physical vapor deposition process; And / or, the material of the first metal layer is ruthenium, cobalt, or ruthenium; And / or, the dielectric capping layer is formed using a plasma-enhanced chemical vapor deposition process; and / or, the material of the dielectric capping layer is silicon nitride or silicon oxynitride; And / or, the intermetallic dielectric layer is formed using a plasma-enhanced chemical vapor deposition process; and / or, the material of the intermetallic dielectric layer is an oxide or a nitride.
9. The method for preparing a metal gate connection hole according to claim 3, characterized in that, The groove has a depth of 5~20nm and an aspect ratio of 0.4~1; And / or, the thickness of the first metal layer formed on the gate stack is 100~200nm.
10. The method for preparing a metal gate connection hole according to claim 3, characterized in that, The groove is formed by removing part of the material from the metal gate using a dry etching process. And / or, the first metal layer is planarized using a chemical mechanical polishing process to remove the portion of the first metal layer that is above the metal front dielectric layer, so that the upper surface of the first metal layer is flush with the upper surface of the metal front dielectric layer.
11. The method for preparing a metal gate connection hole according to claim 3, characterized in that, In the step of removing part of the material from the metal gate, the process gas is a halogen gas, including BCl3 and / or CF4, the gas flow rate is 5~50 sccm, the process temperature is -10~20℃, the process pressure is 0~50 mtorr, the source RF power is 0~1000W, and the bias RF power is 0~100W. And / or, in the step of forming the first metal layer on the gate stack, the process gas includes tungsten hexafluoride and any one of silane and borane, the gas flow rate is 5~20 slm, the process temperature is 200~400°C, and the process pressure is 1~20 torr.
12. A metal gate connection hole, characterized in that, It is prepared by the method of preparing the metal gate connection hole according to any one of claims 1-11.
13. A semiconductor process apparatus, comprising a process chamber, an inlet assembly, an upper electrode assembly, a lower electrode assembly, and a controller, characterized in that, The controller includes at least one processor and at least one memory, the memory storing a computer program that, when executed by the processor, implements the method for preparing a metal gate interconnect as described in any one of claims 1-11.