Substrate structure of electronic device and manufacturing method of electronic device

Abstract

The present disclosure provides a substrate structure of an electronic device and a manufacturing method of an electronic device. The substrate structure of the electronic device includes a substrate, a plurality of through holes, a plating auxiliary layer, and a conductive member. The substrate has a first surface and a second surface opposite to each other. The plurality of through holes penetrates the substrate. The plating auxiliary layer is disposed on the first surface, and at least part of the plating auxiliary layer extends to a sidewall of at least one of the plurality of through holes. The conductive member is disposed in at least one of the plurality of through holes. The electronic device provided by the present disclosure has improved reliability.

Description

Technical Field

[0001] This disclosure relates to an electronic device, and more particularly to the design and manufacturing method of an electronic device having a substrate structure. Background Technology

[0002] In the process of forming electronic devices, electroplating is used to form conductive elements in the vias of a substrate to form a substrate structure. However, when the depth-to-width ratio of the vias to be formed is high, the conductive elements formed in the vias using existing electroplating processes will have voids. This will make the signal transmission in electronic devices including the aforementioned substrate structure prone to abnormalities due to defects in the conductive elements, which will lead to a decrease in the reliability of the electronic devices. Summary of the Invention

[0003] This disclosure relates to a substrate structure for an electronic device, which can have relatively high reliability.

[0004] According to some embodiments disclosed herein, the substrate structure of an electronic device includes a substrate, a plurality of through-holes, an electroplating auxiliary layer, and a conductive element. The substrate has a first surface and a second surface opposite to each other. The plurality of through-holes penetrate the substrate. The electroplating auxiliary layer is disposed on the first surface, and at least a portion of the electroplating auxiliary layer extends to the sidewall of at least one of the plurality of through-holes. The conductive element is disposed in at least one of the plurality of through-holes.

[0005] This disclosure relates to a method for manufacturing an electronic device that can produce an electronic device with relatively high reliability.

[0006] According to some embodiments of this disclosure, a method for manufacturing an electronic device includes the following steps: Providing a substrate structure, which includes the following steps: Providing a substrate having a plurality of through-holes, wherein the substrate has a first surface and a second surface opposite to each other, and an electroplating auxiliary layer is disposed on the sidewalls of the plurality of through-holes near the first surface. Placing the substrate on a carrier plate, wherein the first surface faces a seed layer disposed on the carrier plate. Performing an electroplating process to form conductive elements in at least one of the plurality of through-holes, wherein the electroplating process includes a bottom-up electroplating process. Performing at least one process on the substrate structure to form an electronic device. Attached Figure Description

[0007] Figure 1A This is a schematic flowchart of a method for manufacturing an electronic device according to an embodiment of the present disclosure;

[0008] Figure 1B This is a partial top view schematic diagram of the substrate structure of an electronic device according to some embodiments of the present disclosure;

[0009] Figure 1C This is a partial cross-sectional schematic diagram of the substrate structure of an electronic device according to an embodiment of the present disclosure;

[0010] Figure 2 This is one embodiment of the method for fixing a substrate to a carrier plate disclosed herein;

[0011] Figure 3 This is another embodiment of the method for fixing a substrate to a carrier plate disclosed herein;

[0012] Figure 4 This is yet another embodiment of the method for fixing a substrate to a carrier plate disclosed herein;

[0013] Figure 5 This is a schematic flowchart of a method for manufacturing an electronic device according to another embodiment of the present disclosure;

[0014] Figure 6A This is a cross-sectional schematic diagram of an electronic device according to an embodiment of the present disclosure;

[0015] Figure 6B This is a partial top view schematic diagram of an electronic device according to an embodiment of the present disclosure. Detailed Implementation

[0016] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0017] This disclosure can be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that, for ease of understanding and for the sake of brevity, many of the drawings in this disclosure depict only a portion of the electronic device, and certain components in the drawings are not drawn to scale. Furthermore, the number and dimensions of the components in the drawings are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0018] Throughout this disclosure and in the appended claims, certain terms are used to refer to specific elements. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same element. This document is not intended to distinguish between elements that have the same function but different names. In the following description and claims, words such as “comprising,” “containing,” and “having” are open-ended terms and should therefore be interpreted as “containing but not limited to…”. Thus, when the terms “comprising,” “containing,” and / or “having” are used in the description of this disclosure, they specify the presence of the corresponding feature, area, step, operation, and / or component, but do not exclude the presence of one or more of the corresponding feature, area, step, operation, and / or component.

[0019] The directional terms used herein, such as "up," "down," "front," "back," "left," and "right," are for illustrative purposes only and are not intended to limit this disclosure. The accompanying drawings illustrate general features of the methods, structures, and / or materials used in specific embodiments. However, these drawings should not be construed as defining or limiting the scope or nature covered by these embodiments.

[0020] When a component (e.g., a membrane or region) is referred to as "on another component," it can be directly on that component, or there may be other components between them. Conversely, when a component is referred to as "directly on another component," there are no components between them. Furthermore, when a component is referred to as "on another component," the two components are vertically related in the planar view, and this component can be above or below the other component, depending on the orientation of the device.

[0021] The terms "equal to" or "same as", "substantially" or "approximately" are generally interpreted as being within 20% of a given value or range, or within 10%, 5% or 0.5% of a given value or range.

[0022] The ordinal numbers used in the specification and claims, such as "first," "second," etc., to modify elements, do not in themselves imply or represent any prior ordinal number of that element (or those elements), nor do they represent the order of one element with another, or the order of manufacturing processes. The use of these ordinal numbers is solely to clearly distinguish one named element from another element with the same name. The claims and specification may not use the same terminology; therefore, a first element in the specification may be a second element in the claims.

[0023] It should be understood that the features in the following embodiments can be replaced to complete other embodiments without departing from the spirit of this disclosure. Features between the embodiments can be arbitrarily mixed and matched as long as they do not violate the spirit of the invention or conflict with it.

[0024] The electrical connections or couplings described in this disclosure can refer to direct or indirect connections. In the case of a direct connection, the endpoints of the two circuit components are directly connected or connected to each other by a conductor segment. In the case of an indirect connection, there are other suitable components between the endpoints of the two circuit components.

[0025] In this disclosure, the definitions of thickness, length, width, area, and roughness can be obtained through observation using optical microscopes, scanning electron microscopes, or transmission electron microscopes. On an uneven surface, the distance difference between the peaks and valleys of the surface undulations can be defined as the roughness of that surface. The surface undulations are observed under appropriate magnification, and the roughness range is determined by comparing the undulations using a sample of unit length (e.g., 10 micrometers). Here, "appropriate magnification" means a surface roughness (Rz) or average roughness (Ra) where at least 10 undulation peaks can be observed under this magnification.

[0026] The process of the electronic device disclosed herein can be provided, for example, through a wafer-level package (WLP) or panel-level package (PLP) process, which can be a chip-first or chip-last (RDL first) process.

[0027] The electronic devices disclosed herein can be applied to power modules, semiconductor packaging devices, display devices, light-emitting devices, backlight devices, antenna devices, sensing devices, or splicing devices, but are not limited thereto. The electronic devices may have peripheral systems such as drive systems, control systems, and light source systems to support display devices, antenna devices, wearable devices, automotive devices, or splicing devices. The electronic devices may include packaging devices such as High Bandwidth Memory (HBM) packages, Chip on Wafer on Substrate (CoWoS) packaging structures, System on a Chip (SoC), System in a Package (SiP), Antenna in Package (AiP), Co-packaged Optics (CPO), or various combinations of the above devices, but are not limited thereto.

[0028] Please refer to Figure 1A and Figure 1B In this embodiment, the substrate structure 100a can be formed by performing the following steps, but this disclosure is not limited thereto.

[0029] Step (1): Form a seed layer S on the carrier plate C1.

[0030] The carrier plate C1 may possess a certain degree of rigidity and insulation. In other words, the rigidity of the carrier plate C1 may be greater than that of the redistribution layer or add-on structure formed thereon, thereby reducing the likelihood of warping when the carrier plate C1 is used to support the substrate structure, redistribution layer, or add-on structure of this embodiment. It is worth noting that the "rigidity" referred to in this disclosure can be tested using a universal testing machine (UTM). In some embodiments, the material of the carrier plate C1 may include a transparent material. For example, the material of the carrier plate C1 may be glass, alkali-free glass, quartz glass, or other suitable materials. In this embodiment, the carrier plate C1 is a glass carrier plate.

[0031] The seed layer S can be formed on the substrate C1 by electroplating, atomic deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), or a combination thereof. In some embodiments, the seed layer S may include stacked multilayer conductive layers. For example, the seed layer S may include copper and titanium layers stacked on top of each other, but this disclosure is not limited thereto.

[0032] In this embodiment, before forming the seed layer S on the carrier plate C1, a release layer RL1 is first formed on the carrier plate C1. In other words, the release layer RL1 is disposed between the seed layer S and the carrier plate C1.

[0033] With the release layer RL1, components subsequently formed on the carrier plate C1 can be easily separated from it. The material of the release layer RL1 may include a matrix selected from organic resins, oxides, or polymer composites, and may contain a decomposing agent selected from heat-sensitive compounds, photoreactive compounds, redox-active salts, or moisture-sensitive compounds.

[0034] Step (2): Provide a substrate 10 having multiple through holes VH, wherein an electroplating auxiliary layer 20 is disposed in the multiple through holes VH.

[0035] The substrate 10 may be made of, for example, a suitable ceramic material. For instance, the substrate 10 may be made of transparent materials, glass, alkali-free glass, quartz glass, or other suitable materials. The coefficient of thermal expansion of the substrate 10 may be between 2 ppm / K and 10 ppm / K, the thickness of the substrate 10 may be between 500 micrometers and 2000 micrometers, and the light transmittance of the substrate 10 may be greater than or equal to 80%, wherein the light includes white light. In this embodiment, the substrate 10 has surfaces 10s1, 10s2, and 10s3. Specifically, the substrate 10 has surfaces 10s1 and 10s2 that are opposite to each other in the Z direction (the normal direction of the substrate 10), and a surface 10s3 connected to surfaces 10s1 and 10s2, wherein surface 10s1 can be considered as the lower surface of the substrate 10, surface 10s2 as the upper surface of the substrate 10, and surface 10s3 as the side surface of the substrate 10. In some embodiments, substrate processing can be performed on substrate 10 by performing corresponding etching and / or laser processes, for example, forming multiple through-holes VH through substrate 10.

[0036] An electroplating auxiliary layer 20 is disposed on at least one side of the substrate 10. Specifically, in this embodiment, the electroplating auxiliary layer 20 is disposed on the surface 10s1 of the substrate 10, and at least a portion of the electroplating auxiliary layer 20 extends to the sidewall of at least one of the plurality of vias VH. In some embodiments, the material of the electroplating auxiliary layer 20 may include copper (Cu), titanium (Ti), tungsten (W), or a combination thereof. In other embodiments, the electroplating auxiliary layer 20 is disposed on the surface 10s2 of the substrate 10, and at least another portion of the electroplating auxiliary layer 20 extends to the sidewall of at least one of the plurality of vias VH.

[0037] In some embodiments, the substrate 10 has a height H1 in the Z direction, the electroplating auxiliary layer 20 has a height H2 in the Z direction, and the via VH has a width D1 in a direction perpendicular to the Z direction (e.g., direction X or direction Y). In this embodiment, the ratio between the height H1 of the substrate 10, the height H2 of the electroplating auxiliary layer 20, and the width D1 of the via VH may be 2:1.75:1, but this disclosure is not limited thereto.

[0038] In addition, in this embodiment, before forming the electroplating auxiliary layer 20, a buffer layer BF is first formed on the sidewalls of the plurality of vias VH. The material of the buffer layer BF may include suitable organic and / or inorganic materials. In some embodiments, the buffer layer BF may include a multilayer stacked structure of inorganic / organic / inorganic layers. By providing the buffer layer BF to cover the sidewalls of the vias VH, it can be used to fill pits, unevenness, or microcracks generated on the substrate 10 during the electronic device fabrication process, thereby reducing the possibility of the substrate 10 cracking. According to some embodiments, the buffer layer BF may be disposed on at least one surface of the substrate 10.

[0039] Step (3): Place the substrate 10 on the carrier plate C1.

[0040] In this embodiment, the surface 10s1 of the substrate 10 faces the seed layer S on the carrier plate C1. That is, the seed layer S can be disposed between the electroplating auxiliary layer 20 and the release layer RL1. In some embodiments, an adhesive material AD can be provided on the substrate. According to some embodiments, the adhesive material AD can overlap the substrate 10 and the seed layer S to fix the substrate 10 to the carrier plate C1, and the adhesive material AD can directly contact the side surface 10s3 of the substrate 10, such as... Figure 1B The diagram shown is a top view. In some embodiments, the adhesive material AD includes tape.

[0041] Step (4): Perform a metallization process to form a conductive element 30 in the through hole VH.

[0042] In this embodiment, the metallization process includes a bottom-up plating process. Specifically, by allowing the conductive material (typically copper) to grow from the bottom of the via VH (near the surface 10s1 of the substrate 10), air can be gradually expelled, reducing the possibility of voids in the formed conductive element 30. The presence of the plating auxiliary layer 20 facilitates the bottom-up plating process. The formed conductive element 30 may, for example, slightly protrude from the via VH and may be formed on a portion of the surface 10s2 of the substrate 10, but this disclosure is not limited thereto. In some embodiments, the material of the conductive element 30 may include copper (Cu), aluminum (Al), molybdenum (Mo), tungsten (W), gold (Au), chromium (Cr), nickel (Ni), platinum (Pt), titanium (Ti), silver (Ag), tantalum (Ta), metal nitrides, other suitable conductive materials, or combinations thereof. Additionally, in some embodiments, the material of the conductive element 30 may be the same as or different from the material of the plating auxiliary layer 20.

[0043] In some embodiments, before step (4), an annealing process is performed on the seed layer S and the electroplating auxiliary layer 20.

[0044] In detail, in some embodiments, a eutectic system can be formed by annealing the seed layer S and the electroplating auxiliary layer 20. Through the formation of the eutectic system, a conductive component 30 with relatively stable and / or relatively good thermal conductivity can be formed after subsequent electroplating processes.

[0045] In some embodiments, the eutectic system may include a binary eutectic system. For example, a binary eutectic system may include Cu / Sn, Cu / Au, Cu / Ag, or other suitable binary eutectic alloys, but this disclosure is not limited thereto. In other embodiments, the eutectic system may include a ternary eutectic system, which may include suitable ternary eutectic alloys.

[0046] Step (5): Remove the seed layer S and the electroplating auxiliary layer 20 located on the surface 10s1 of the substrate 10.

[0047] In this embodiment, removing the seed layer S and the electroplating auxiliary layer 20 located on the surface 10s1 of the substrate 10 may include the following steps. First, a carrier plate C2 and a release layer RL2 disposed on the carrier plate C2 are provided. Next, the substrate 10 is placed on the carrier plate C2, wherein the surface 10s2 of the substrate 10 faces the release layer RL2 on the carrier plate C2. Then, the substrate 10 is separated from the carrier plate C1 using the release layer RL1. Then, a first planarization process is performed to remove the seed layer S and the electroplating auxiliary layer 20 located on the surface 10s1 of the substrate 10. In some embodiments, the first planarization process may include a polishing process using a polishing element GD, but this disclosure is not limited thereto.

[0048] By removing a portion of the seed layer S and the electroplating auxiliary layer 20, the surface of the conductive element 30 exposed on one side of the through-hole VH can be coplanar with the surface 10s1 of the substrate 10.

[0049] Step (6): Remove the conductive element 30 located on the surface 10s2 of the substrate 10.

[0050] In this embodiment, removing the conductive element 30 located on the surface 10s2 of the substrate 10 may include the following steps. First, a carrier plate C3 and a release layer RL3 disposed on the carrier plate C3 are provided. Next, the substrate 10 is placed on the carrier plate C3, wherein the surface 10s1 of the substrate 10 faces the release layer RL3 on the carrier plate C3. Then, the substrate 10 is separated from the carrier plate C2 using the release layer RL2. Then, a second planarization process is performed to remove the conductive element 30 located on the surface 10s2 of the substrate 10. In some embodiments, the second planarization process may include a polishing process using a polishing element GD, but this disclosure is not limited thereto.

[0051] By removing a portion of the conductive element 30, the surface of the conductive element 30 exposed on the other side of the through hole VH can be coplanar with the surface 10s2 of the substrate 10.

[0052] In addition, after removing the conductive element 30 located on the surface 10s2 of the substrate 10, the substrate 10 is separated from the carrier plate C3 by the release layer RL3.

[0053] This completes the fabrication of substrate structure 100a. In this embodiment, at least one corresponding process can be performed on substrate structure 100a to form, for example... Figure 6A The electronic device 1 shown will be described in detail in the following embodiments.

[0054] Please refer to Figure 1C In some other embodiments of the substrate structure 100b, the electroplating auxiliary layer 20 may also be disposed on the sidewall of the plurality of through holes VH near the surface 10s2 of the substrate 10, but this disclosure is not limited thereto.

[0055] Please refer to Figure 2 This illustrates a method for fixing a substrate 10 to a carrier plate C1. Specifically, in step (3) of this embodiment, the substrate 10 is fixed to the carrier plate C1 using a holder H.

[0056] In this embodiment, a clamp H can be disposed on surfaces 10s2 and 10s3 of the substrate 10 to fix the substrate 10 onto the carrier plate C1, which can reduce the possibility of the substrate 10 shifting during subsequent electroplating processes. Specifically, the clamp H may include upper and lower portions located on two opposing surfaces (surfaces 10s1 and 10s2) of the substrate 10 to reliably clamp and fix the substrate 10. Furthermore, the clamp H can reduce the possibility of the electroplating solution used in the electroplating process eroding the corresponding surfaces of the substrate 10.

[0057] Additionally, in this embodiment, the fixture H may include contact pins CP. The contact pins CP may contact the seed layer 10 disposed on the surface 10s1 of the substrate 10, which can be used to uniformly distribute the current used in subsequent electroplating processes, thereby improving the uniformity of the formed conductive part 30.

[0058] Please refer to Figure 3 This illustrates another method for fixing the substrate 10 to the carrier plate C1. Specifically, in step (1) of this embodiment, an adhesive layer A1 is formed on the seed layer S.

[0059] In this embodiment, the adhesive layer A1 comprises a conductive adhesive layer. Specifically, the adhesive layer A1 may, for example, comprise an insulating film and a plurality of conductive particles dispersed therein. For instance, the adhesive layer A1 may comprise an anisotropic conductive film (ACF), but this disclosure is not limited thereto. In some embodiments, the adhesive layer A1 may have a thermal conductivity of 425–485 W / (m·°C) and may have a thermal conductivity of 1.6 W / (m·°C). 10 -6 The impedance is μΩ-cm, but this disclosure is not limited to this.

[0060] Based on this, after step (3), the surface 10s1 of the substrate 10 faces the adhesive layer A1 on the carrier plate C1. In addition, when step (5) is performed, the adhesive layer A1 located on the surface 10s1 of the substrate 10 is also removed.

[0061] Please refer to Figure 4 This illustrates yet another method for fixing the substrate 10 to the carrier plate C1. Specifically, in step (1) of this embodiment, an adhesive layer A2 is formed on the seed layer S.

[0062] In this embodiment, the adhesive layer A2 is made of a thermosetting resin layer. In step (3), after the substrate 10 is placed on the carrier plate C1, the surface 10s1 of the substrate 10 faces the adhesive layer A2 on the carrier plate C1. Then, a suitable patterning process is used to remove the adhesive layer A2 that exposes the multiple vias VH to facilitate subsequent electroplating processes.

[0063] Since the material of the adhesive layer A2 includes a thermosetting resin layer, the adhesive layer A2 can be used to prevent the electroplating solution used in the electroplating process from flowing into the through hole from the surface 10s3 and / or surface 10s1 of the substrate 10, thereby reducing the possibility of the electroplating solution corroding the corresponding surface of the substrate 10.

[0064] In addition, during step (5), the adhesive layer A2 on the surface 10s1 of the substrate 10 is also removed.

[0065] Please refer to Figure 5 This illustrates a method for forming a substrate structure 100c. In this embodiment, the main difference between the method for forming the substrate structure 100c and the method for forming the substrate structure 100a is that, in step (2), the electroplating auxiliary layer 20 includes a first portion 22 and a second portion 24, and the second portion 24 covers the first portion 22.

[0066] In this embodiment, the processes used to form the first portion 22 and the second portion 24 may be different from each other. For example, the first portion 22 may be formed by sputtering, and the second portion 24 may be formed by electroless plating, but this disclosure is not limited thereto. In some embodiments, the materials of the first portion 22 and the second portion 24 may be different from each other. For example, the material of the first portion 22 may include copper, and the material of the second portion 24 may include gold or nickel, but this disclosure is not limited thereto.

[0067] Figure 6A This is a cross-sectional schematic diagram of an electronic device according to an embodiment of the present disclosure, and Figure 6B This is a partial top view schematic diagram of an electronic device according to an embodiment of the present disclosure.

[0068] Please refer to Figure 6A In this embodiment, at least one corresponding process can be performed on the substrate structure 100 to form the electronic device 1, which may include the process of forming a plurality of electronic components 2 on the substrate structure 100, but this disclosure is not limited thereto. It is worth noting that the substrate structure 100 may be at least one of the substrate structures 100a, 100b and 100c described above. In this embodiment, the substrate structure 100 may serve as an interposer for the electronic device 1, but this disclosure is not limited thereto.

[0069] In this embodiment, the circuit structure ES1 is disposed on the surface 10s2 of the substrate 10 and at least partially overlaps a plurality of vias VH. In some embodiments, the circuit structure ES1 includes at least one insulating layer IL1 and at least one conductive layer M1. The material of the insulating layer IL1 may include an ajinomoto build-up film (ABF). The conductive layer M1 may include photosensitive polyimide (PSPI), polyimide (PI), epoxy resin, or other suitable insulating materials. The conductive layer M1 may include a suitable conductive material, which may be the same as or similar to the material of the conductive element 30.

[0070] Please refer to Figure 6BIn this embodiment, the region in the substrate structure 100 where multiple vias VH are provided can be divided into a dense region 102 and a sparse region 104. The multiple vias VH in the dense region 102 are arranged more densely, while the multiple vias VH in the sparse region 104 are arranged more sparsely. Specifically, adjacent vias VH in the dense region 102 have a cutoff p1, and adjacent vias VH in the sparse region 104 have a cutoff p2, wherein the cutoff p1 is less than twice the cutoff p2. It is worth noting that "adjacent" or "nearby" in this disclosure refers to two of multiple elements (e.g., multiple vias VH) arranged along a direction, and these two elements having a minimum distance or minimum spacing. In some embodiments, the conductivity of the electroplating auxiliary layer 20 material in the multiple vias VH in the dense region 102 is greater than the conductivity of the electroplating auxiliary layer 20 material in the multiple vias VH in the sparse region 104.

[0071] In this embodiment, the electronic device 1 further includes a plurality of connection units CU1. The plurality of connection units CU1 are disposed on the circuit structure ES1 so that the circuit structure ES1 can be electrically connected to a plurality of electronic components 2, which will be described later, through the plurality of connection units CU1. The materials of the plurality of connection units CU1 may include tin, copper, nickel, silver, gold, gallium, or other suitable materials.

[0072] In this embodiment, the circuit structure ES1 includes a redistribution structure, which can be used to redistribute lines and / or further increase the fan-out area of ​​the lines. The purpose of the redistribution structure is to extend the interconnects to a wider spacing or to redistribute the interconnects to another interconnect with a different spacing. Based on this, identical or different electronic components 2 can be disposed on and electrically connected to the circuit structure ES1. Specifically, multiple electronic components 2 are disposed on and electrically connected to the circuit structure ES1. In this embodiment, the multiple electronic components 2 include three electronic components 2a, 2b, and 2c, but this disclosure is not limited to these numbers. Electronic components 2a, 2b, and 2c may, for example, each be a system-on-a-chip (SoC), dynamic random access memory (DRAM), high bandwidth memory (HBM), static random access memory (SRAM), cache memory, graphics processing unit (GPU), central processing unit (CPU), digital signal processor (DSP), or application-specific integrated circuit (ASIC), but this disclosure is not limited thereto. In this embodiment, the three electronic components 2a, 2b, and 2c can be electrically connected to the circuit structure ES1 through the corresponding connection unit CU1 and the circuit structure ES2. The circuit structure ES2 includes at least one insulating layer IL2 and at least one conductive layer M2, and the materials of the insulating layer IL2 and the conductive layer M2 can be the same as or similar to the materials of the insulating layer IL1 and the conductive layer M1, respectively.

[0073] In this embodiment, the electronic device 1 further includes a plurality of connection units CU2. The plurality of connection units CU2 are disposed on one side of the surface 10s1 of the substrate 10 and are electrically connected to the conductive element 30 in the substrate structure 100. The material of the plurality of connection units CU2 may be the same as or similar to the material of the plurality of connection units CU1, which will not be described in detail here.

[0074] In this embodiment, the electronic device 1 further includes another substrate structure 100'. The substrate structure 100' may also be at least one of the substrate structures 100a, 100b, and 100c described above. In this embodiment, the substrate structure 100' may serve as an integrated circuit substrate (IC substrate) of the electronic device 1, but this disclosure is not limited thereto.

[0075] In this embodiment, the electronic device 1 further includes a circuit structure ES3. The circuit structure ES3 is disposed on the surface 10s2 of the substrate 10 in the substrate structure 100', and at least partially overlaps a plurality of through holes VH. In some embodiments, the circuit structure ES3 includes at least one insulating layer IL3 and at least one conductive layer M3, and the materials of the insulating layer IL3 and the conductive layer M3 may be the same as or similar to the materials of the insulating layer IL1 and the conductive layer M1, respectively.

[0076] In this embodiment, the electronic device 1 further includes a plurality of connection units CU3. The plurality of connection units CU3 are disposed on one side of the surface 10s1 of the substrate 10 in the substrate structure 100' and are electrically connected to the conductive element 30 in the substrate structure 100'. The materials of the plurality of connection units CU3 may be the same as or similar to the materials of the plurality of connection units CU1, which will not be described in detail here.

[0077] In summary, in the manufacturing methods of electronic devices provided in some embodiments of this disclosure, by providing an electroplating auxiliary layer on the sidewalls of multiple through-holes near the surface of the substrate, conductive elements formed in the multiple through-holes can be achieved using a bottom-up electroplating process. This allows for the uniform formation of conductive elements in through-holes with a high aspect ratio, reducing the possibility of voids in the conductive elements. Based on this, the reliability of the electronic devices provided in some embodiments of this disclosure can be improved.

[0078] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A substrate structure for an electronic device, characterized in that, The substrate structure includes: A substrate having a first surface and a second surface that are opposite to each other; Multiple through holes penetrate the substrate; An electroplating auxiliary layer is disposed on the first surface, and at least a portion of the electroplating auxiliary layer extends to the sidewall of at least one of the plurality of through holes; and A conductive element is disposed in at least one of the plurality of through holes.

2. The substrate structure of the electronic device according to claim 1, comprising a dense region and a sparse region, wherein there is a first intercept between adjacent vias in the dense region, and a second intercept between adjacent vias in the sparse region, wherein the first intercept is less than twice the second intercept.

3. The substrate structure of the electronic device according to claim 2, wherein the conductivity of the material of the conductive element located in the dense region is greater than the conductivity of the material of the conductive element located in the sparse region.

4. The substrate structure of the electronic device according to claim 1, wherein the material of the electroplating auxiliary layer includes a eutectic alloy.

5. The substrate structure of the electronic device according to claim 1, wherein the substrate structure further comprises: A buffer layer is disposed on the sidewall of the plurality of through holes and located between the conductive element and the substrate.

6. A method for manufacturing an electronic device, characterized in that, include: A substrate structure is provided, wherein the step of providing the substrate structure includes: A substrate having a plurality of through holes is provided, wherein the substrate has a first surface and a second surface opposite to each other, an electroplating auxiliary layer is disposed on the first surface, and at least a portion of the electroplating auxiliary layer extends to the sidewall of at least one of the plurality of through holes; The substrate is placed on a first carrier plate, wherein the first surface faces the seed layer disposed on the first carrier plate; An electroplating process is performed to form a conductive element in at least one of the plurality of through holes, wherein the electroplating process includes a bottom-up electroplating process; and The substrate structure is subjected to at least one process to form the electronic device.

7. The method for manufacturing an electronic device according to claim 6, wherein the substrate structure includes dense regions and sparse regions. The plurality of through holes formed in the dense region have a first intercept between adjacent pairs, and the plurality of through holes formed in the sparse region have a second intercept between adjacent pairs, wherein the first intercept is less than twice the second intercept.

8. The method of manufacturing an electronic device according to claim 6, wherein after the substrate is placed on the first carrier plate, the substrate is fixed to the first carrier plate by a clamp, the clamp including a contact and the contact contacting the seed layer.

9. The method of manufacturing an electronic device according to claim 6, further comprising forming an adhesive layer on the seed layer disposed on the first carrier plate, wherein the adhesive layer comprises a conductive adhesive layer.

10. The method for manufacturing an electronic device according to claim 6, wherein before performing the electroplating process, the method further includes an annealing process for the seed layer and the electroplating auxiliary layer to form a eutectic system.

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