Electronic device and method of manufacturing an electronic device

Abstract

Electronic devices and methods of manufacturing electronic devices. In one example, an electronic component is coupled to a contact and a first passivation layer is disposed over the electronic component. The first passivation layer can define a first opening that partially passes through the first passivation layer and a second opening that exposes the contact from the first passivation layer. A first seed can be disposed over the first passivation layer and in the first and second openings. A first conductive material can be over the first seed in the first and second openings. A second seed can be disposed over an upper side of the first conductive material, and the first and second seeds can encircle the first conductive material in the first and second openings. Other examples and related methods are also disclosed herein.

Description

Technical Field

[0001] This disclosure generally relates to electronic devices, and more specifically, to electronic devices and methods of manufacturing electronic devices. Background Technology

[0002] Existing electronic packaging technologies and methods for forming electronic packages have shortcomings, leading to problems such as excessively high costs, reduced reliability, relatively low performance, or excessively large package sizes. By comparing these methods with this disclosure and referring to the accompanying drawings, those skilled in the art will understand other limitations and disadvantages of conventional and traditional methods. Summary of the Invention

[0003] Various embodiments of this disclosure provide an electronic device comprising: an electronic component coupled to a contact; a first passivation layer disposed above the electronic component, the first passivation layer defining a first opening partially extending through the first passivation layer and a second opening exposing the contact from the first passivation layer; a first seed crystal disposed above the first passivation layer and in the first and second openings; a first conductive material disposed above the first seed crystal in the first and second openings; and a second seed crystal disposed above an upper side of the first conductive material, wherein the first and second seed crystals surround the first conductive material in the first and second openings. The electronic device further includes: a second passivation layer disposed above the first passivation layer and defining a third opening exposing the second seed crystal; a third seed crystal coupled to the second seed crystal and disposed above the inner wall of the second passivation layer defining the third opening; a second conductive material disposed in the third opening, coupled to the third seed crystal, and coupled to the second seed crystal; and a fourth seed crystal disposed above the second conductive material and coupled to the third seed crystal, wherein the second seed crystal, the third seed crystal, and the fourth seed crystal surround the second conductive material in the third opening. The electronic device further includes: an external passivation layer disposed above the second passivation layer and defining a fourth opening exposing the fourth seed crystal from the external passivation layer; and an outward terminal disposed in the fourth opening and coupled to the fourth seed crystal. In the electronic device, a portion of the first seed crystal extends from the first opening and extends above the upper side of the first passivation layer surrounding the first opening. In the electronic device, the portion of the first seed crystal extending above the upper side of the first passivation layer has a width of 0.1 micrometers (μm) to 1.5 μm. In the electronic device, the second seed crystal completely covers the upper side of the first conductive material. In the electronic device, the second seed crystal extends from the upper side of the first conductive material to the upper side of the first seed crystal. In the electronic device, the first seed crystal and the second seed crystal comprise titanium. In the electronic device, the first seed crystal and the second seed crystal surround the first conductive material with four-sided side barriers, and wherein the first conductive material includes embedded traces disposed in the first passivation layer and covered by a second passivation layer.In the electronic device, the first seed crystal further includes: an internal seed crystal comprising titanium or titanium-tungsten, the internal seed crystal being coupled to the first passivation layer, coupled to an inner wall defining the first opening and the second opening, and coupled to the contact; and an external seed crystal comprising copper, aluminum, nickel, gold, or silver, the external seed crystal being coupled to the internal seed crystal and covering the internal seed crystal, wherein the first conductive material is coupled to the external seed crystal. In the electronic device, the upper side of the first conductive material is recessed from the upper side of the first passivation layer. In the electronic device, a second seed crystal above the upper side of the first conductive material is disposed in the first opening. The electronic device further includes a sealant coupled to the electronic component, the sealant including a side coplanar with the side of the first passivation layer. In the electronic device, the sidewall of the electronic component is coplanar with the sidewall of the first passivation layer. The electronic device further includes a bottom filler disposed between the electronic component and the first passivation layer. The electronic device further includes a thermal interface material coupled to the electronic component and a cap coupled to the thermal interface material.

[0004] This disclosure provides a method of manufacturing an electronic device, comprising: providing an electronic component coupled to a contact; providing a first passivation layer over the electronic component and the contact, the first passivation layer defining a first opening extending partially through the first passivation layer and a second opening exposing the contact from the first passivation layer; providing a first seed crystal over the first passivation layer and in the first and second openings; providing a first conductive material over the first seed crystal in the first and second openings; and providing a second seed crystal over the upper side of the first conductive material, wherein the first and second seed crystals surround the first conductive material in the first and second openings. The method further includes: providing a second passivation layer over the first passivation layer, the second passivation layer defining a third opening exposing the second seed crystal; providing a third seed crystal disposed over an inner wall of the second passivation layer and coupled to the second seed crystal; providing a second conductive material disposed in the third opening, coupled to the third seed crystal, and coupled to the second seed crystal; and providing a fourth seed crystal disposed over the second conductive material and coupled to the third seed crystal, wherein the second seed crystal, the third seed crystal, and the fourth seed crystal surround the second conductive material in the third opening. The method further includes: providing an external passivation layer over the second passivation layer and defining a fourth opening exposing the fourth seed crystal; and providing an outward terminal disposed in the fourth opening and coupled to the fourth seed crystal.

[0005] Various embodiments of this disclosure provide an electronic device, comprising: an electronic component; a first passivation layer disposed above the electronic component and defining an opening; a first seed crystal disposed above the first passivation layer and in the opening defined by the first passivation layer, wherein a portion of the first seed crystal is coupled to the first passivation layer around the periphery of the opening; a conductive material disposed above the first seed crystal in the opening; and a second seed crystal covering the upper side of the conductive material and coupled to the portion of the first seed crystal, wherein the first seed crystal and the second seed crystal surround the conductive material. Attached Figure Description

[0006] Figure 1 A cross-sectional view of an example electronic device is shown.

[0007] Figures 2A to 2K A cross-sectional diagram illustrates an example method for manufacturing electronic devices.

[0008] Figures 3A to 3F They are shown respectively Figures 2B to 2G An enlarged view of part A in the image.

[0009] Figure 4 A cross-sectional view of an example electronic device is shown.

[0010] Figure 5 A cross-sectional view of an example electronic device is shown.

[0011] Figure 6 A cross-sectional view of an example electronic device is shown.

[0012] Figures 7A to 7E A cross-sectional diagram illustrates an example method for manufacturing electronic devices.

[0013] Figure 8 A cross-sectional view of an example electronic device is shown.

[0014] The following discussion provides various examples of electronic devices and methods of manufacturing electronic devices. Such examples are non-limiting, and the scope of the appended claims should not be limited to the specific examples disclosed. In the following discussion, the terms "example" and "for example" are non-limiting.

[0015] The figures illustrate general construction methods, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessary confusion with this disclosure. Furthermore, the elements in the figures are not necessarily drawn to scale. For example, the dimensions of some elements in each figure may be enlarged relative to other elements to aid in understanding the examples discussed in this disclosure. The same reference numerals in different figures denote the same elements.

[0016] The term "or" refers to any one or more items in a list connected by "or". As an example, "x or y" means any element in the three-element set {(x), (y), (x, y)}. As another example, "x, y or z" means any element in the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}.

[0017] The terms “comprises”, “comprising”, “includes”, and “including” are “open” terms that specify the presence of the stated feature but do not exclude the presence or addition of one or more other features.

[0018] The terms “first,” “second,” etc., may be used herein as designations to describe various elements, and these elements should not be limited by these terms. These terms are used only to distinguish different elements. Thus, for example, a first element discussed in this disclosure may be referred to elsewhere as a second element without departing from the teachings of this disclosure. Similarly, terms disclosed as singular may be plural in some embodiments, and elements disclosed as plural may be singular in some embodiments.

[0019] Unless otherwise specified, the term "coupled" can be used to describe two elements in direct contact with each other, or to describe two elements indirectly coupled through one or more other elements. For example, if element A is coupled to element B, then element A can be in direct contact with element B or indirectly coupled to element B through intervening element C. Similarly, the terms "above" or "on" can be used to describe two elements in direct contact with each other, to describe two elements indirectly coupled through one or more other elements, or, as depicted, two elements vertically overlapping. Unless otherwise specified, the term "coupled" can refer to mechanical coupling or electrical coupling. Detailed Implementation

[0020] An example electronic device may include an electronic component coupled to a contact, with a first passivation layer disposed above the electronic component. The first passivation layer may define a first opening partially extending through the first passivation layer and a second opening exposing the contact from the first passivation layer. A first seed crystal may be disposed above the first passivation layer and within the first and second openings. A first conductive material may be disposed above the first seed crystal within the first and second openings. A second seed crystal may be disposed above the upper side of the first conductive material, and both the first and second seed crystals may surround the first conductive material within the first and second openings.

[0021] In various examples, the electronic device may include a second passivation layer disposed above the first passivation layer and defining a third opening exposing a second seed crystal. A third seed crystal may be coupled to the second seed crystal and disposed above the inner wall of the third opening defined by the second passivation layer. A second conductive material may be disposed in the third opening, coupled to the third seed crystal, and coupled to the second seed crystal. A fourth seed crystal may be disposed above the second conductive material and coupled to the third seed crystal. The second, third, and fourth seed crystals may surround the second conductive material in the third opening. In some examples, an outer passivation layer may be disposed above the second passivation layer and defining a fourth opening exposing the fourth seed crystal from the outer passivation layer. An outward terminal may be disposed in the fourth opening and coupled to the fourth seed crystal. A portion of the first seed crystal may extend from the first opening and extend above the upper side of the first passivation layer surrounding the first opening.

[0022] In some examples, the portion of the first seed crystal extending above the upper side of the first passivation layer may include a width of 0.1 micrometers (μm) to 1.5 μm. The second seed crystal completely covers the upper side of the first conductive material. The second seed crystal extends from the upper side of the first conductive material onto the upper side of the first seed crystal. The first and second seed crystals comprise titanium. The first and second seed crystals surrounding the first conductive material may include four-sided side barriers. The first conductive material may include embedded traces disposed in the first passivation layer and covered by the second passivation layer. The first seed crystal also includes an inner seed crystal comprising titanium or titanium-tungsten, which is coupled to the first passivation layer, coupled to the inner wall defining the first and second openings, and coupled to a contact. The outer seed crystal may comprise copper, aluminum, nickel, gold, or silver, which is coupled to the inner seed crystal and may cover the inner seed crystal. The first conductive material is coupled to the outer seed crystal. The upper side of the first conductive material may be recessed from the upper side of the first passivation layer. The second seed crystal above the upper side of the first conductive material is disposed in the first opening. A sealant can be coupled to the electronic component and can include a sidewall coplanar with the sidewall of the first passivation layer. The sidewall of the electronic component can be coplanar with the sidewall of the first passivation layer. An underfill can be disposed between the electronic component and the first passivation layer. A thermal interface material can be coupled to the electronic component, and a cap can be coupled to the thermal interface material.

[0023] An example method of manufacturing an electronic device may include the steps of: providing an electronic component coupled to contacts, and providing a first passivation layer over the electronic component and the contacts. The first passivation layer may define a first opening extending partially through the first passivation layer and a second opening exposing the contacts from the first passivation layer. The step may further include providing a first seed crystal over the first passivation layer and in the first and second openings, providing a first conductive material over the first seed crystal in the first and second openings, and providing a second seed crystal over the upper side of the first conductive material. The first and second seed crystals may surround the first conductive material in the first and second openings.

[0024] Another example electronic device may include an electronic component, a first passivation layer disposed above the electronic component and defining an opening, and a first seed crystal disposed above the first passivation layer and within the opening defined by the first passivation layer. A portion of the first seed crystal is coupled to the first passivation layer around the periphery of the opening. A conductive material may be disposed above the first seed crystal in the opening. A second seed crystal may cover the upper side of the conductive material and may be coupled to a portion of the first seed crystal. The first and second seed crystals may surround the conductive material.

[0025] Other examples are included in this disclosure. Such examples can be found in the drawings, claims, or description of this disclosure.

[0026] Electronic devices and related methods may include oxidation-resistant conductive elements. In some examples, conductive elements such as traces or pads may be surrounded by barriers. For example, a titanium barrier layer may completely surround the cross-section of a copper conductive element, thereby creating a four-sided or full-coverage metal barrier structure. Barriers may include two-piece or multi-piece barrier structures. For example, a barrier layer may be formed, and then a conductive element with exposed sides may be formed over the barrier layer, and then a second barrier layer may be formed over the exposed sides of the conductive element to surround the conductive element. In some examples, the barrier layers described herein may be applied to embedded traces (ETRs).

[0027] In some examples, a four-sided barrier (e.g., surrounding the conductive element) can reduce oxidation compared to a three-sided barrier (e.g., one side of the conductive element is exposed from the barrier). Some examples of four-sided barriers can reduce the oxidation area ratio (e.g., oxidation area / conductive element area × 100) of the conductive element by approximately 14 times, approximately 15 times, or approximately 16 times (e.g., 15.53 times in some examples), or approximately 17 times, approximately 18 times, or approximately 19 times (e.g., 18.92 times in some examples) compared to a conductive element without a barrier on one or three sides. Examples of four-sided barriers can also mitigate the increase in resistance over time that may be due to oxidation of the conductive element. For example, compared to a conductive element without a barrier on one or three sides, a four-sided barrier can limit the increase in resistance of the conductive element over time to approximately 23 times, approximately 24 times, or approximately 25 times (e.g., 23.78 times in some examples), or approximately 62 times, approximately 63 times, or approximately 64 times (e.g., 63.69 times in some examples). Therefore, the reliability of electronic devices can be improved by using four-sided side barriers.

[0028] Now for reference Figure 1 A cross-sectional view of an example electronic device 100 according to various examples is shown. Figure 1 In the example shown, electronic device 100 includes electronic components 110 and a substrate 12. The substrate 12 includes a dielectric structure 120 and a conductive structure 130. In some examples, electronic device 100 may also include interconnects 140.

[0029] According to various examples, dielectric structure 120 may include passivation layer 121, passivation layer 122, and external passivation layer 123. Conductive structure 130 may include conductive patterns 131 and 132. Conductive pattern 131 may include capped seed 131c, seed 131s, trace 131t, pad 131p, and via 131v. Conductive pattern 132 may include capped seed 132c, seed 132s, trace 132t, pad 132p, and via 132v. In some examples, seed 131s and capped seed 131c may include four-sided barriers. Conductive structure 130 may include inward terminal 130a and outward terminal 130b. Inward terminal 130a may be coupled to contact 111 of electronic component 110.

[0030] Figures 2A to 2K This illustrates the use of electronic devices (e.g., Figure 1 A cross-sectional view of an example method of an electronic device 100. Figures 3A to 3F They are shown respectively Figures 2B to 2G An enlarged view of part A in the image.

[0031] Figure 2AA cross-sectional view of an electronic device 100 in an early stage of manufacturing is shown. Figure 2A In the example shown, a passivation layer 121 may be provided on electronic component 110. Electronic component 110 may include, or be referred to as, a semiconductor die, a semiconductor chip, or a package. For example, electronic component 110 may include a digital signal processor, a network processor, a power management unit, an audio processor, radio frequency circuitry, a wireless baseband system-on-chip (SoC) processor, a sensor, or an application-specific integrated circuit (ASIC). In some examples, electronic component 110 may be configured to perform calculations, control processing, store data, or remove noise from electrical signals.

[0032] In some examples, electronic component 110 may include contact 111. Contact 111 may be disposed above the active side of electronic component 110. Contact 111 may include, or be referred to as, pad, contact surface, UBM (under-bump metal), stud, bump, or post.

[0033] According to various examples, electronic component 110 may be part of substrate 11. In some examples, substrate 11 may include, or be referred to as, a wafer, a reconstructed wafer, or a panel. For example, substrate 11 may be a semiconductor wafer containing electronic component 110, which is formed in rows and columns on the wafer and separated by sawtooths. In some examples, substrate 11 may be a reconstructed wafer containing qualified electronic components 110 arranged in rows and columns, with sealant located between adjacent qualified electronic components 110. In some examples, substrate 11 may be a panel containing one or more semiconductor wafers and / or reconstructed wafers located thereon. The thickness of substrate 11 may range from about 50 micrometers (μm) to about 2000 μm. The terms about, approximately, or similar terms used with numerical values ​​may mean + / -5%, + / -10%, + / -15%, + / -20%, or + / -25%. In some examples, substrate 11 may be a temporary carrier.

[0034] According to various examples, a passivation layer 121 may be provided to cover the upper side of the substrate 11. The passivation layer 121 may be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), spin coating, spray coating, dip coating, bar coating, or any other suitable deposition process.

[0035] The passivation layer 121 can be patterned to provide one or more openings 1211, trace recesses 1212, and pad recesses 1213. The openings 1211 can extend completely through the passivation layer 121 and expose the contacts 111. The trace recesses 1212 and pad recesses 1213 can be formed partially through the passivation layer 121, such that a portion of the passivation layer 121 remains above the electronic component 110 and includes the bottom of the trace recesses 1212 and pad recesses 1213. The layout and shape of the trace recesses 1212 and pad recesses 1213 are chosen to form a conductive pattern 131. Figure 2B The desired conductive structure (e.g., trace, pad, ground plane, etc.).

[0036] In some examples, the passivation layer 121 can be patterned by providing a patterned mask (e.g., a patterned photoresist) on the top side of the passivation layer 121. The portion of the passivation layer 121 exposed from the mask is then removed (i.e., the passivation layer 121 can be patterned) to form openings 1211, trace recesses 1212, and pad recesses 1213. After patterning the passivation layer 121, the mask is removed.

[0037] In some examples, passivation layer 121 may include, or be referred to as, a dielectric, dielectric layer, insulator, or insulating layer. For example, passivation layer 121 may include one or more layers of electrically insulating material, such as organic dielectrics (e.g., polymers, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BT)) or inorganic dielectrics (e.g., silicon nitride (Si3N4), silicon oxide (SiO2), or silicon oxynitride (SiON)). In some examples, the thickness of passivation layer 121 may range from about 2 μm to about 20 μm.

[0038] Figure 2B A cross-sectional view of the electronic device 100 in the late manufacturing stage is shown. Figure 3A It shows Figure 2B A magnified view of part A in the image. Figure 2B and 3A In the example shown, seed dies 131s can be provided above the passivation layer 121. Seed dies 131s can be located in the opening 1211, the trace groove 1212, and the pad groove 1213. For example, seed dies 131s can be provided above the upper surface of the passivation layer 1211, the sidewalls and bottom of the opening 1211, the trace groove 1212, the pad groove 1213, and along the exposed upper side of the contact 111. Seed dies 131s can be formed by electroless plating, electrolytic plating, sputtering, PVD, CVD, MOCVD, ALD, LPCVD, PECVD, or any other suitable deposition process.

[0039] Seed crystals 131s may include internal seed crystals 1311s and external seed crystals 1312s. In some examples, external seed crystals 1312s may be provided by forming internal seed crystals 1311s covering the upper side of passivation layer 121. For example, internal seed crystals 1311s may be provided on the upper surface of passivation layer 121, the sidewalls and bottom of opening 1211, above trace groove 1212, pad groove 1213, and along the exposed upper side of contact 111. External seed crystals 1312s may be provided to cover internal seed crystals 1311s. Internal seed crystals 1311s may include titanium (Ti) or titanium-tungsten (TiW). External seed crystals 1312s may include copper (Cu), aluminum (Al), nickel (Ni), gold (Au), or silver (Ag). In some examples, the thickness of seed crystals 131s may be in the range of about 0.01 μm to about 1 μm.

[0040] Figure 2C A cross-sectional view of the electronic device 100 in the late manufacturing stage is shown. Figure 3B It shows Figure 2C A magnified view of part A in the image. Figure 2C and 3C In the example shown, a conductive material 131A may be provided above the seed 131s. The conductive material 131A may be located in the opening 1211, the trace groove 1212, and the pad groove 1213, filling or partially filling them. In some examples, the conductive pattern 131 may be provided by forming a seed 131s covering the upper side of the passivation layer 121.

[0041] The conductive material 131A can be provided over the external seed crystals 1312s by electroless plating, electrolytic plating, sputtering, PVD, CVD, MOCVD, ALD, LPCVD, PECVD, or any other suitable deposition. The conductive material 131A can include metals (e.g., Cu, Al, Au, Ag, or Ni), alloys, compounds, or other conductive materials. The conductive material 131A can be part of the conductive pattern 131. The external seed crystals 1312s can include materials similar to or identical to those described for the conductive material 131A.

[0042] According to various examples, the portion of conductive material 131A located in opening 1211 may be coupled to contact 111 of electronic component 110 and may include, or be referred to as, via 131v. The portion of conductive material 131A located at the bottom of opening 1211 (i.e., at the bottom side of via 131v) may be referred to as substrate-inward terminal 130a. In some examples, one or more of trace recess 1212 and portions of conductive material 131A located in trace recess 1212 may include and / or form one or more ground planes.

[0043] Figure 2DA cross-sectional view of the electronic device 100 in the late manufacturing stage is shown. Figure 3C It shows Figure 2D A magnified view of part A in the image. Figure 2D and 3C In the example shown, the conductive material 131A disposed outside the opening 1211, the trace groove 1212 and the pad groove 1213 can be removed.

[0044] In some instances, chemical mechanical planarization (CMP) can be used to remove the conductive material 131A from above the uppermost surface of the external seed 1312s. The conductive material 131A can fill or partially fill the opening 1211, the trace groove 1212, and the pad groove 1213, respectively, and can expose the external seed 1312s. The conductive material 131A disposed in the opening 1211, the trace groove 1212, and the pad groove 1213 may include, or be referred to as, via 131v, trace 131t, and pad 131p.

[0045] In various examples, the external seed 1312s can be removed by etching (e.g., wet etching or dry etching) to expose the internal seed 1311s. When the external seed 1312s is removed, the upper sides of the via 131v, trace 131t, and pad 131p can also be partially removed. For example, the upper sides of the via 131v, trace 131t, and pad 131p can be recessed relative to the upper sides of the internal seed 1311s. The external seed 1312s can comprise a material similar to or the same as the via 131v, trace 131t, or pad 131p. The external seed 1312s located in the opening 1211, trace recess 1212, and pad recess 1213 can be considered as portions of the via 131v, trace 131t, and pad 131p, respectively. For simplicity, some figures depicting subsequent processing steps are omitted. Figure 3C External seed crystal 1312s (e.g., Figure 3D-3F However, it should be understood that even when not depicted, external seed crystals 1312s may exist in the examples of the following figures. Seed crystals 131s may include, or are referred to herein as, internal seed crystals 1311s. Conductive pattern 131 may include vias 131v, traces 131t, and pads 131p. The thickness of vias 131v, traces 131t, and pads 131p may range from about 1 μm to about 20 μm.

[0046] Figure 2E A cross-sectional view of the electronic device 100 in the late manufacturing stage is shown. Figure 3D It shows Figure 2E A magnified view of part A in the image. Figure 2E and 3DIn the example shown, a capping seed 131c can be provided above the seed 131s, via 131v, trace 131t, and pad 131p. The capping seed 131c can be provided to cover the upper side of the seed 131s, the upper side of the via 131v, the trace 131t, and the pad 131p. The capping seed 131c covering the upper side of the via 131v, the trace 131t, and the pad 131p can be positioned lower than the capping seed 131c covering the upper side of the seed 131s (e.g., recessed from the upper side of the capping seed 131s). The capping seed 131c can be formed by electroless plating, electroplating, sputtering, PVD, CVD, MOCVD, ALD, LPCVD, PECVD, or any other suitable deposition process. The capping seed 131c can be made of a material similar to the seed layer. For example, the capped seed crystal 131c may comprise titanium (Ti) or titanium tungsten (TiW). In some examples, the thickness of the capped seed crystal 131c may range from about 0.01 μm to about 1 μm.

[0047] Figure 2F A cross-sectional view of the electronic device 100 in the late manufacturing stage is shown. Figure 3E It shows Figure 2F A magnified view of part A in the image. Figure 2F and 3E In the example shown, a mask 1 is provided above the capping seed 131c. In other examples, the mask 1 may include a photoresist. The mask 1 can be patterned using various techniques such as exposure, development, etching, and curing to form a mask opening 1a. The mask opening 1a can expose a portion of the capping seed 131c. The mask opening 1a can expose a portion of the seed 131s located on the passivation layer 121. The mask 1 can cover portions of the capping seed 131c located on the via 131v, trace 131t, and pad 131p. In some examples, the width or diameter of the mask 1 may be greater than the width or diameter of the via 131v, trace 131t, and pad 131p, such that the mask 1 also covers portions of the capping seed 131c located on the upper side of the passivation layer 121.

[0048] Figure 2G A cross-sectional view of the electronic device 100 in the late manufacturing stage is shown. Figure 3F It shows Figure 2G A magnified view of part A in the image. Figure 2G and 3FIn the example shown, the capping seed 131c and seed 131s exposed through the mask opening 1a can be removed. For example, the capping seed 131c and seed 131s can be removed by etching (e.g., wet etching or dry etching) to a portion of the uppermost side of the passivation layer 121. The capping seed 131c and seed 131s may cover the uppermost portion of the passivation layer 121 and are adjacent to the via 131v, trace 131t, and pad 131p. The capping seed 131c and seed 131s may extend from the edges of the via 131v, trace 131t, and pad 131p toward the uppermost side of the passivation layer 121. The width (w) of the capping seed 131c and seed 131s extending above the passivation layer 121 around a peripheral opening or groove in the passivation layer 121 can range from about 0.1 μm to about 1.5 μm.

[0049] In some examples, via 131v, trace 131t, and pad 131p may include, or be referred to as, embedded trace RDL. Via 131v, trace 131t, and pad 131p may be surrounded or enclosed by capping seeds 131c and seed 131s. Each capping seed 131c or seed 131s may serve as a protective layer to protect via 131v, trace 131t, and pad 131p, thereby preventing moisture penetration into via 131v, trace 131t, and pad 131p. Capping seeds 131c and seed 131s include a barrier layer that prevents or inhibits oxidation of via 131v, trace 131t, and pad 131p. Therefore, the capping seed crystals 131c and 131s used as barriers can improve electrical performance by limiting the attenuation or shrinkage of the conductive pattern 131, which may otherwise be caused by oxidation or moisture penetration.

[0050] Figure 2H A cross-sectional view of an electronic device 100 in a late-stage manufacturing process is shown. Figure 2HIn the example shown, a passivation layer 122 may be provided on the conductive pattern 131 and the passivation layer 121. In some examples, a passivation layer 122 may be provided that covers the conductive pattern 131 and the passivation layer 121. A portion of the passivation layer 122 may be removed (i.e., the passivation layer 122 may be patterned) to form an opening 1221, a trace groove 1222, and a pad groove 1223. The trace groove 1222, the pad groove 1223, and the opening 1221 may be formed by etching (e.g., wet etching or dry etching), laser ablation, or any other suitable patterning process. According to various examples, the trace groove 1222 may extend partially through the passivation layer 122, and a portion of the passivation layer 122 may remain above the passivation layer 121 and the conductive pattern 131, forming the bottom of the trace groove 1222 and the pad groove 1223. The opening 1221 may extend completely through the passivation layer 122 and may expose a portion of the conductive pattern 131. In some examples, passivation layer 121 may include, or be referred to as, a dielectric, dielectric layer, insulator, or insulating layer. In some examples, passivation layer 122 may contain elements, features, materials, or manufacturing methods similar to or the same as those described for passivation layer 121.

[0051] Figure 2I A cross-sectional view of an electronic device 100 in a late-stage manufacturing process is shown. Figure 2I In the example shown, a conductive pattern 132 may be provided over the passivation layer 122 and the conductive pattern 131. The conductive pattern 132 may be disposed in the opening 1221, the trace groove 1222, and the pad groove 1223, filling or partially filling them. The conductive pattern 132 may include elements, features, materials, or manufacturing methods similar to or the same as those of the conductive pattern 131.

[0052] In various examples, the conductive pattern 132 disposed in the opening 1221, the trace groove 1222, and the pad groove 1223 may include, or be referred to as, a via 132v, a trace 132t, and a pad 132p. The via 132v may be contacted and electrically connected to expose a portion of the conductive pattern 131. For example, the exposed portion of the conductive pattern 131 may be the pad 131p of the conductive pattern 131.

[0053] In some examples, via 132v, trace 132t, and pad 132p may include, or be referred to as, embedded trace RDL. Via 132v, trace 132t, and pad 132p may be covered by capping seed dies 132c and 132s, respectively. Capping seed dies 132c or 132s can serve as a protective layer to protect via 132v, trace 132t, and pad 132p, thereby preventing moisture penetration into them. Capping seed dies 132c and 132s can prevent or inhibit oxidation of via 132v, trace 132t, and pad 132p.

[0054] Figure 2J A cross-sectional view of an electronic device 100 in a late-stage manufacturing process is shown. Figure 2J In the illustrated example, an external passivation layer 123 may be provided on the conductive pattern 132 and the passivation layer 122. In some examples, an external passivation layer 123 may be provided covering the conductive pattern 132 and the passivation layer 122. A portion of the external passivation layer 123 may be removed (i.e., the external passivation layer 123 may be patterned) to form an aperture 1231. The pads 132p of the conductive pattern 132 may expose the aperture 1231. The aperture 1231 may be formed by etching (e.g., wet etching or dry etching), laser ablation, or any other suitable patterning process. In some examples, the external passivation layer 123 may have elements, features, materials, or manufacturing methods similar to those of the passivation layer 121. In some examples, the external passivation layer 123 may include or be referred to as a dielectric, dielectric layer, insulator, or insulating layer. In some examples, the external passivation layer 123 may include or be referred to as a solder resist.

[0055] Figure 2K A cross-sectional view of an electronic device 100 in a late-stage manufacturing process is shown. Figure 2K In the example shown, an outward terminal 130b may be provided in the aperture 1231 of the outer passivation layer 123, and an interconnect 140 may be provided on the outward terminal 130b.

[0056] According to various examples, the outward terminal 130b may fill or partially fill the orifice 1231 of the external passivation layer 123. The outward terminal 130b is coupled to and may contact the pad 132p of the conductive pattern 132. According to various examples, the elements, features, materials, or manufacturing methods of the outward terminal 130b may be similar to or the same as the elements, features, materials, or manufacturing methods of the conductive pattern 131 or the conductive pattern 132. For example, the outward terminal 130b may be formed by electroless plating, electroplating, sputtering, PVD, CVD, MOCVD, ALD, LPCVD, PECVD, or any other suitable deposition process, and may include conductive materials such as Cu, Al, Au, Ag, or Ni. The outward terminal 130b may contain a seed crystal similar to or the same as the seed crystal 131s of the conductive pattern 131.

[0057] Interconnect 140 may be coupled to outgoing terminal 130b. In some examples, interconnect 140 may include tin (Sn), Ag, lead (Pb), Cu, Sn-Pb, Sn37-Pb, Sn95-Pb, Sn-Pb-Ag, Sn-Cu, Sn-Ag, Sn-Au, Sn-Bi, or Sn-Ag-Cu. For example, interconnect 140 may be provided by forming a solder-containing conductive material on outgoing terminal 130b using a drop ball and reflow process. In some examples, interconnect 140 may also include under-bump metal (UBM) formed between the bump and outgoing terminal 130b. Interconnect 140 may include, or be referred to as, conductive balls such as solder balls, conductive pillars such as copper pillars, or conductive posts with solder caps formed on copper pillars. In some examples, interconnect 140 may be referred to as an external input / output terminal of electronic device 100. In some examples, electronic device 100 may be a pad grid array (LGA), wherein component outgoing terminals 130b are used as external input / output terminals of electronic device 100 (i.e., electronic device 100 may not include interconnects 140).

[0058] According to various examples, dielectric structure 120 and conductive structure 130 can form substrate 12. In some examples, substrate 12 may be referred to as RDL substrate, multilayer substrate, multilayer RDL, or multilayer signal distribution structure. Although conductive structure 130 is shown as having a total of three layers including conductive pattern 131, conductive pattern 132, and outward terminal 130b, the number of conductive pattern layers may be less than or more than three, and any suitable number of conductive pattern layers may be included in electronic device 100.

[0059] According to various examples, after the interconnect 140 is provided, a separation process can be performed to separate the substrate 11 into individual electronic devices 100. The separation process may involve sawing through the substrate 12 and adjacent electronic components 110 (e.g., sawing through a saw path S). ​​The separation process can utilize a blade, a laser beam, or any other suitable cutting method. After separation, the lateral sides of the substrate 12 may be coplanar with the lateral sides of the electronic components 110.

[0060] In the electronic device 100, the conductive pattern 132 may be covered, surrounded, or otherwise enclosed by capping seed crystals 132c and 132s. Therefore, the capping seed crystals 132c and 132s can serve as four-sided barriers to prevent moisture from penetrating into and oxidizing the conductive pattern 132. Thus, the capping seed crystals 132c and 132s, acting as barriers, can improve electrical performance by limiting the decay or shrinkage of the conductive pattern 132 over time.

[0061] Figure 4 A cross-sectional view of example electronic device 100A is shown. Figure 4 In the example shown, electronic device 100A may include electronic component 110A, substrate 12, and interconnect 140. Electronic component 110A includes component interconnect 111A. Substrate 12 includes dielectric structure 120 and conductive structure 130. In some examples, electronic device 100A can use... Figures 2A to 2K It is manufactured using techniques and structures similar to or the same as those shown or described herein.

[0062] like Figure 4 As depicted in the examples, electronic device 100A may include a multilayer conductive structure 130 interleaved with a multilayer dielectric structure 120. In some examples, electronic device 100A may include, or be referred to as, a wafer-level package (WLP) or a wafer-level chip-level package (WLCSP).

[0063] Figure 5 A cross-sectional view of example electronic device 100B is shown. Figure 5 In the example shown, electronic device 100B includes electronic component 110B, substrate 12, interconnect 140, and sealant 160B. Substrate 12 includes dielectric structure 120 and conductive structure 130. Electronic component 110B may include component interconnect 111B. Figure 5 The electronic device 100B shown can be connected with Figure 4 The electronic device 100A shown is similar to or the same as that shown, wherein the sealant 160B is disposed around the electronic device 100B.

[0064] Electronic device 100B can be used with Figures 2A to 2K To manufacture using technologies, processes, and structures that are similar to or identical to those shown. For example, Figures 2A to 2K The substrate 11 may include a reconstructed wafer having a sealant 160B disposed between adjacent electronic components 110B. In some examples, such as Figure 2K As shown, the separation can be performed through the sealant 160B, and after separation, the sealant 160B is coplanar with the substrate 12.

[0065] In some examples, sealant 160B may include, or be referred to as, an encapsulation body, a sealing structure, a mold, an epoxy molding compound, a resin, a filler-reinforced polymer, a Class B compression film, or a gel. Sealant 160B may be provided by transfer molding, compression molding, liquid sealant molding, vacuum lamination, slurry printing, film-assisted molding, or other suitable processes. In some examples, sealant 160B may contact or cover the bottom or lateral side of electronic component 110B. In some examples, the bottom side of sealant 160B and the bottom side of electronic component 110B may be coplanar, and the bottom side of electronic component 110B may be exposed from the bottom side of sealant 160B. Sealant 160B may protect electronic component 110B from the effects of external environment or environmental exposure.

[0066] In some examples, substrate 12 may be provided on the top side of sealant 160B and on the top side of electronic component 110B. In some examples, the top side of electronic component 110B and the top side of sealant 160B may be coplanar. In some examples, electronic device 100B may include, or be referred to as wafer-level fan-out (WLFO).

[0067] Figure 6 A cross-sectional view of an example electronic device 100C is shown. Figure 6 In the example shown, electronic device 100C may include electronic components 110C, substrate 12, interconnects 140, and sealant 160C. In some examples, electronic device 100C may also include underfill 170C. Substrate 12 includes dielectric structure 120 and conductive structure 130. Figure 6 The electronic device 100C shown can be respectively connected with Figure 4 and 5 The electronic devices 100A and 100B shown are similar or identical, wherein the dielectric structure 120 and conductive structure 130 of the electronic device 100C are provided before the electronic component 110C is coupled to the substrate 12 and before the sealant 160C is provided.

[0068] refer to Figures 7A to 7E Example methods for manufacturing electronic device 100C are shown according to various examples. Figure 7A A cross-sectional view of an electronic device 100C in an early stage of manufacturing is shown. Figure 7AIn the example shown, a substrate 12 comprising a dielectric structure 120 and a conductive structure 130 may be provided on the carrier 210. According to various examples, a substrate 12 comprising a dielectric structure 120 and a conductive structure 130 may be used. Figures 2A to 2K The substrate 12 is provided on the carrier 210 using techniques and structures similar to or the same as those shown or described herein.

[0069] In some examples, carrier 210 may include, or be referred to as, a wafer, plate, panel, strip, substrate, or temporary carrier. Carrier 210 may include semiconductor materials (e.g., Si), glass, metal, ceramic, etc. In some examples, a temporary adhesive may be provided on the upper side of carrier 210 to facilitate separation of substrate 12 from carrier 210. The temporary adhesive may be, for example, a thermal release tape (or film) or an optical release tape (or film), configured to reduce its adhesive strength due to heat or light, respectively.

[0070] Figure 7B A cross-sectional view of the electronic device 100C in its late manufacturing stage is shown. Figure 7B In the example shown, the support carrier 220 is coupled to the upper side of the substrate 12, and the carrier 210 is removed from the opposite side of the substrate 12.

[0071] In various examples, the support carrier 220 may include, or be referred to as, a wafer, plate, panel, strip, substrate, or temporary carrier. The support carrier 220 may include semiconductor materials (e.g., Si), glass, metal, ceramic, etc. In some examples, a temporary adhesive 222 may be provided on the support carrier 220 to facilitate the separation of the substrate 12 from the support carrier 220. The temporary adhesive 222 may be, for example, a thermal release tape (or film) or an optical release tape (or film), configured to reduce its adhesive strength due to heat or light, respectively. In some examples, the external passivation layer 123 of the dielectric structure 120 and the outward terminals 130b of the conductive structure 130 may be coupled to the temporary adhesive 222.

[0072] Based on various examples, carrier 210 ( Figure 7A The carrier 210 can be removed from the substrate 12 by grinding, etching, laser ablation, physical force, application of heat or light, or another suitable removal method. Removal of the carrier 210 exposes the bottom side of the conductive via 131v and the passivation layer of the dielectric structure 120. In some examples, removal of the carrier 210 may expose the inward terminal 130a of the conductive structure 130. In other examples, the inward terminal 130a may be provided after removal of the carrier 210.

[0073] Figure 7C A cross-sectional view of the electronic device 100C in its late manufacturing stage is shown. Figure 7C In the example shown, substrate 12 can be relative to Figure 7BThe view shown is flipped, and electronic components 110C can be provided above substrate 12. Although substrate 12 is shown as coupled to a second carrier 220, and... Figure 7C In one example, the substrate 12 is flipped to couple the electronic component 112C to an earlier formed layer or structure on the substrate 12; however, in other examples, the substrate 12 may be held on the carrier 210 and / or in contact with... Figure 7A With the same orientation, and the electronic component 110C can be coupled to a later-formed layer or structure (e.g., it can be first formed in...). Figure 7A An outward terminal 130b to which the interconnect 140 is coupled is formed on the carrier 210, and an inward terminal 130a to which the electronic component 110C is coupled may be formed and / or formed on the far side of the carrier 210.

[0074] In various examples, electronic component 110C may include, or be referred to as, a die, a chip, a package (e.g., one or more dies encapsulated and / or coupled to a laminate or RDL substrate), or a passive element. In some examples, the thickness of electronic component 110C may range from about 20 μm to about 100 μm.

[0075] According to various examples, electronic component 110C may be coupled to conductive structure 130. Electronic component 110C may include contacts 111C and component interconnects 112C that contact the contacts 111C. For example, component interconnects 112C of electronic component 110C may be coupled to an inward terminal 130a of conductive structure 130. In electronic component 110C, contacts 111C may be electrically connected to inward terminal 130a via component interconnects 112C. Contacts 111C may include, or be referred to as bumps, pads, or pillars. In some examples, the thickness of contacts 111C may range from about 1 μm to about 10 μm. Component interconnects 112C may include, or be referred to as solder. In some examples, component interconnects 112C may be electrically coupled to inward terminal 130a via thermocompression bonding, ultrasonic bonding, laser-assisted bonding, or hybrid bonding (e.g., the interconnect between contacts 111C and inward terminal 130a may lack component interconnect 112C). In some examples, the elements, features, materials, or manufacturing methods of the inward terminal 130a may be consistent with... Figures 2A to 2E The elements, features, materials, or manufacturing methods of the conductive pattern 131 shown or described herein are similar or identical.

[0076] According to various examples, an underfill 170C may be provided between the substrate 12 and the electronic component 110C. In some examples, the underfill 170C may contact the substrate 12 (e.g., dielectric structure 120 or conductive structure 130), contact 111C, component interconnect 112C, and electronic component 110C. In some examples, the underfill 170C may include, or be referred to as, a capillary underfill, a non-conductive paste, or a non-conductive film. In some examples, the underfill 170C may be pushed into the gap between the electronic component 110C and the substrate 12 after the electronic component 110C is electrically coupled to the substrate 12. In some examples, the underfill 170C may be pre-coated onto the substrate 12 before the electronic component 110C is coupled to the substrate 12. In some examples, the underfill 170C may be pre-coated onto the electronic component 110C before the electronic component 110C is coupled to the substrate 12. In some examples, a curing process (e.g., thermosetting or photocuring) can be performed on the underfill 170C.

[0077] Figure 7D A cross-sectional view of the electronic device 100C in its late manufacturing stage is shown. Figure 7D In the example shown, a sealant 160C is provided over the electronic component 110C and the substrate 12. In some instances, the sealant 160C may cover or couple to the substrate 12, the electronic component 110C, and the underfill 170C. In some instances, the underfill 170C may be omitted, and the sealant 160C may be filled between the electronic component 110C and the substrate 12. In some instances, the sealant 160C may be removed from the back side of the electronic component 110C. For example, the back side of the electronic component 110C may be exposed from the sealant 160C. In some instances, the back side of the electronic component 110C and the sealant 160C may be coplanar. In some instances, the sealant 160C may cover the back side of the electronic component 110C. The elements, features, materials, or manufacturing methods of the sealant 160C may be similar to or the same as the elements, features, materials, or manufacturing methods of the sealant 160B.

[0078] Figure 7E A cross-sectional view of the electronic device 100C in its late manufacturing stage is shown. Figure 7E In the example shown, the support 230 can be coupled to the sealant 160C and the electronic component 110C, and the support carrier 220 can be removed from the substrate 12.

[0079] According to various examples, the support 230 may include, or be referred to as, a wafer, plate, panel, strip, substrate, tape, or temporary carrier. In some examples, a temporary adhesive may be provided on the upper side of the support 230 to facilitate separation of the support 230 from the electronic device 100C. The temporary adhesive may be, for example, a heat-release tape (or film) or an optical release tape (or film), configured to reduce its adhesive strength due to heat or light.

[0080] Based on various examples, support carrier 220 ( Figure 7D The support carrier 220 can be removed from the substrate 12 by grinding, etching, laser ablation, physical force, application of heat and / or light, or another suitable removal method. Removal of the support carrier 220 exposes the outer passivation layer of the outward terminal 130b and the dielectric structure 120. As described above, interconnects 140 can be provided on the outward terminal 130b.

[0081] According to various examples, after the interconnect 140 is provided, a separation process can be performed to separate the substrate 12, to which electronic components 110C are coupled, into individual electronic devices 100C. The separation process may involve sawing through the substrate 12 and the sealant 160C (e.g., sawing along saw line X). The separation process can utilize a blade, a laser beam, or any other suitable cutting method. After separation, the lateral sides of the substrate 12 may be coplanar with the lateral sides of the sealant 160C. In some examples, the separation process may remove the sealant 160C from the lateral sides of the electronic components 110C, such that after separation, the lateral sides of the substrate 12 are coplanar with the lateral sides of the electronic components 110C.

[0082] Figure 8 A cross-sectional view of an example electronic device 200 is shown. Figure 8 In the example shown, electronic device 200 may include electronic device 100D, underfill 175D, substrate 180D, external interconnect 199, and body 190D. Electronic device 100D may be coupled to substrate 180D and may include electronic component 110D, substrate 12, contact 111D, component interconnect 112D, interconnect 140, sealant 160D, and underfill 170D. Substrate 12 may include dielectric structure 120 and conductive structure 130. According to various examples, electronic device 100D may be similar to... Figure 6 The electronic device 100C in it, and can be like Figures 7A to 7E Provided as shown.

[0083] According to various examples, interconnects 140 of electronic device 100D are coupled to substrate 180D. Substrate 180D may include dielectric structures 181D and conductive structures 182D. In some examples, dielectric structure 181D may include a dielectric layer. The dielectric layer may include one or more dielectric material layers interleaved with the layers of the conductive structure. In some examples, the dielectric material may include PI, BCB, PBO, resin, or Ajinomoto multilayer film (ABF). In some examples, conductive structure 182D may include one or more conductive layers defining signal distribution elements (e.g., traces, vias, pads, conductive paths, or UBMs). Conductive structure 182D may include substrate-inward terminals 182D1 and substrate-outward terminals 182D2. In some examples, substrate-inward terminal 182D1 may include pads, contact surfaces, UBMs, or studs. In some examples, substrate-outward terminal 182D2 may include pads or contact surfaces. External interconnects 199 may include solder balls, bumps, pads, or pillars. In some examples, electronic device 200 may be (external interconnect 199 may be omitted).

[0084] In some examples, the substrate 180D may be a preformed substrate. The preformed substrate can be manufactured prior to attachment to an electronic device and may include a dielectric layer between corresponding conductive layers. The conductive layer may include copper and can be formed using an electroplating process. The dielectric layer may be a relatively thick, non-optically definable layer, may serve as a preformed film rather than a liquid attachment, and may contain a resin with fillers such as strands, fabrics, and / or other inorganic particles for rigid and / or structural support. Because the dielectric layer is non-optically definable, features such as vias or openings can be formed using a drill or laser. In some examples, the dielectric layer may include a prepreg material or ABF. The preformed substrate may include a permanent core structure or carrier, such as a dielectric material comprising bismaleimide triazine (BT) or FR4, and the dielectric and conductive layers may be formed on the permanent core structure. In other examples, the preformed substrate may be a coreless substrate and the permanent core structure may be omitted, and the dielectric and conductive layers may be formed on a sacrificial carrier, which is removed after the dielectric and conductive layers are formed and prior to attachment to an electronic device. Preformed substrates may be referred to as printed circuit boards (PCBs) or laminated substrates. Such preformed substrates can be formed by semi-additive or modified semi-additive processes. Other substrates described herein may also include preformed (or laminated) substrates.

[0085] In some examples, substrate 180D may be an RDL substrate. The RDL substrate may include one or more conductive redistribution layers and one or more dielectric layers, which (a) may be formed layer-by-layer over an electronic device electrically coupled to the RDL substrate, or (b) may be formed layer-by-layer over a carrier that may be completely or partially removed after the electronic device and the RDL are coupled together. The RDL substrate may be fabricated layer-by-layer on a circular wafer as a wafer-level substrate using wafer-level processes, and / or on a rectangular or square panel carrier as a panel-level substrate using panel-level processes. The RDL substrate may be formed in an additive stacking process and may include one or more dielectric layers stacked alternately with one or more conductive layers, these layers defining corresponding conductive redistribution patterns or traces configured to collectively (a) fan the traces out of the occupied area of ​​the electronic device, and / or (b) fan the traces into the occupied area of ​​the electronic device. The conductive pattern may be formed using a plating process, such as electroplating or electroless plating. The conductive pattern may include a conductive material, such as copper or other platingable metal. The location of conductive patterns can be created using photolithography, for example, photolithography and photoresist materials to form photomasks.

[0086] The dielectric layer of an RDL substrate can be patterned using a photo-patterning process and may include a photomask through which light is exposed to the desired features of the photo-pattern, such as vias in the dielectric layer. The dielectric layer can be made of a photo-definable organic dielectric material, such as polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO). Such a dielectric material can be spin-coated or otherwise coated in liquid form, rather than attached as a pre-formed film. To correctly form the desired photo-definable features, this photo-definable organic dielectric material may omit structural reinforcing agents or may be filler-free, free from strands, fabrics, or other particles that could interfere with light from the photo-patterning process. In some examples, this filler-free characteristic of filler-free dielectric materials can reduce the thickness of the resulting dielectric layer. Although the photo-definable dielectric materials described above can be organic materials, in some examples, the dielectric material of the RDL substrate may include one or more inorganic dielectric layers. Examples of inorganic dielectric layers may include silicon nitride (Si3N4), silicon oxide (SiO2), and / or SiON. Inorganic dielectric layers can be formed by growing them using oxidation or nitridation processes instead of photodefined organic dielectric materials. Such inorganic dielectric layers may be filler-free, without strands, fabrics, or other distinct inorganic particles. In some instances, the RDL substrate may omit the permanent core or carrier structure typically associated with laminated substrates (e.g., the RDL substrate may be free of dielectric / core materials including bismaleimide triazine (BT) or FR4). These types of RDL substrates may be referred to as coreless substrates. Other substrates described herein may also include RDL substrates.

[0087] Interconnect 140 of electronic device 100D can be electrically coupled to substrate-in-place terminal 182D1 of substrate substrate 180D. In some examples, interconnect 140 can be electrically coupled to substrate-in-place terminal 182D1 by thermoforming, ultrasonic bonding, laser-assisted bonding, or hybrid bonding. In some examples, solder can be inserted between interconnect 140 and substrate-in-place terminal 182D1. In some examples, underfill 175D can be inserted between substrate 12 and substrate substrate 180D. The components, features, materials, or manufacturing methods of underfill 175D can be similar to or the same as those of underfill 170C.

[0088] In some examples, the body 190D can be coupled to the substrate 180D via an adhesive material 191D and to the electronic component 110D via an interface material 192D. In some examples, the interface material 192D may also be inserted between the sealant 160D and the body 190D. The interface material 192D may include, or be referred to as, a thermal interface material (TIM) (e.g., a metallic TIM or a polymeric TIM), an adhesive, or a back-side metallization layer. The body 190D may include, or be referred to as, a heat sink, a cover, a shroud, a housing, a shield, or a shell. In some examples, the body 190D may include a metal or a metal alloy (e.g., Cu, Al, Ni, Ag, etc.). In some examples, the thickness of the body 190D may range from about 10 μm to about 100 μm. The body 190D can dissipate heat from the electronic component 110D, shield the electronic component 110D from electromagnetic interference, and / or protect the substrate 12 and the electronic component 110D from external environmental influences.

[0089] Electronic devices and related methods may include a barrier layer or barrier surrounding conductive elements. For example, a seed layer forming a barrier may surround or enclose traces, pads, vias, or other conductive elements. The barrier can inhibit or prevent oxidation or moisture penetration, which would otherwise degrade or damage the conductive elements over time. Compared to three-sided barriers or other less protective barrier examples for conductive elements, the seed layer of this disclosure forming a four-sided barrier can improve the electrical performance of the conductive elements over time.

[0090] This disclosure includes references to certain examples; however, those skilled in the art will understand that various changes can be made and equivalents can be substituted without departing from the scope of this disclosure. Furthermore, modifications can be made to the disclosed examples without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the disclosed examples, but rather to include all examples falling within the scope of the appended claims.

Claims

1. An electronic device comprising: Electronic components, said electronic components being coupled to contacts; A first passivation layer is disposed above the electronic component, the first passivation layer defining a first opening partially extending through the first passivation layer and a second opening exposing the contact from the first passivation layer; The first seed crystal is disposed above the first passivation layer and in the first opening and the second opening; A first conductive material is disposed above the first seed crystal in the first opening and the second opening; as well as A second seed crystal is disposed above the upper side of the first conductive material, wherein the first seed crystal and the second seed crystal surround the first conductive material in the first opening and the second opening.

2. The electronic device according to claim 1, further comprising: A second passivation layer is disposed above the first passivation layer and defines a third opening that exposes the second seed crystal; A third seed crystal is coupled to the second seed crystal and disposed above the inner wall of the second passivation layer defining the third opening; A second conductive material is disposed in the third opening, coupled to the third seed crystal, and coupled to the second seed crystal; as well as A fourth seed crystal is disposed above the second conductive material and coupled to the third seed crystal, wherein the second seed crystal, the third seed crystal, and the fourth seed crystal surround the second conductive material in the third opening.

3. The electronic device according to claim 2, further comprising: An external passivation layer is disposed above the second passivation layer and defines a fourth opening from which the fourth seed crystal is exposed; as well as An outward terminal is disposed in the fourth opening and coupled to the fourth seed crystal.

4. The electronic device of claim 1, wherein a portion of the first seed extends from the first opening and extends above the upper side of the first passivation layer surrounding the first opening.

5. The electronic device of claim 4, wherein the portion of the first seed crystal extending above the upper side of the first passivation layer has a width of 0.1 μm to 1.5 μm.

6. The electronic device of claim 1, wherein the second seed crystal completely covers the upper side of the first conductive material.

7. The electronic device of claim 1, wherein the second seed extends from the upper side of the first conductive material to the upper side of the first seed.

8. The electronic device of claim 1, wherein the first seed crystal and the second seed crystal comprise titanium.

9. The electronic device of claim 1, wherein the first seed crystal and the second seed crystal surrounding the first conductive material include four-sided barriers, and wherein the first conductive material includes embedded traces disposed in the first passivation layer and covered by a second passivation layer.

10. The electronic device of claim 1, wherein the first seed crystal further comprises: An internal seed crystal, comprising titanium or titanium-tungsten, is coupled to the first passivation layer, to the inner wall defining the first opening and the second opening, and to the contact element; as well as An external seed crystal, comprising copper, aluminum, nickel, gold, or silver, is coupled to and covers the internal seed crystal, wherein the first conductive material is coupled to the external seed crystal.

11. The electronic device of claim 1, wherein the upper side of the first conductive material is recessed from the upper side of the first passivation layer.

12. The electronic device of claim 1, wherein the second seed crystal above the upper side of the first conductive material is disposed in the first opening.

13. The electronic device of claim 1, further comprising a sealant coupled to the electronic component, the sealant comprising a side coplanar with the side of the first passivation layer.

14. The electronic device of claim 1, wherein the sidewall of the electronic component is coplanar with the sidewall of the first passivation layer.

15. The electronic device of claim 1, further comprising a bottom filler disposed between the electronic component and the first passivation layer.

16. The electronic device of claim 1, further comprising a thermal interface material coupled to the electronic component and a cover coupled to the thermal interface material.

17. A method of manufacturing an electronic device, comprising: Provides electronic components coupled to the contacts; A first passivation layer is provided over the electronic component and the contact, the first passivation layer defining a first opening extending partially through the first passivation layer and a second opening exposing the contact from the first passivation layer; A first seed crystal is provided above the first passivation layer and in the first opening and the second opening; A first conductive material is provided above the first seed crystal in the first opening and the second opening; as well as A second seed crystal is provided above the upper side of the first conductive material, wherein the first seed crystal and the second seed crystal surround the first conductive material in the first opening and the second opening.

18. The method of claim 17, further comprising: A second passivation layer is provided above the first passivation layer, the second passivation layer defining a third opening that exposes the second seed crystal; A third seed crystal is provided, which is disposed above the inner wall of the second passivation layer and coupled to the second seed crystal. A second conductive material is provided, which is disposed in the third opening, coupled to the third seed crystal, and coupled to the second seed crystal; as well as A fourth seed crystal is provided, which is disposed above the second conductive material and coupled to the third seed crystal, wherein the second seed crystal, the third seed crystal, and the fourth seed crystal surround the second conductive material in the third opening.

19. The method of claim 18, further comprising: An external passivation layer is provided, which is located above the second passivation layer and defines a fourth opening that exposes the fourth seed crystal; as well as An outward terminal is provided, which is located in the fourth opening and coupled to the fourth seed crystal.

20. An electronic device comprising: Electronic components; A first passivation layer is disposed above the electronic component and defines an opening; A first seed crystal is disposed above the first passivation layer and in the opening defined by the first passivation layer, wherein a portion of the first seed crystal is coupled to the first passivation layer around the periphery of the opening; A conductive material is disposed above the first seed crystal in the opening; as well as A second seed crystal covers the upper side of the conductive material and is coupled to the portion of the first seed crystal, wherein the first seed crystal and the second seed crystal surround the conductive material.

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