A method of multiplying binary strings and a multiplier circuit implementing the method

Abstract

A multiplier circuit for multiplying two numbers, at least one of which is represented by two binary strings, referred to as "substrings". The sum of the substrings is the number represented. This allows many combinations of pairs of different substrings to represent the same value. The multiplier circuit expands each number into partial products, each of which is in the form of two binary strings. After processing to select a pair of binary strings to represent each partial product, the partial products are added without any carry. Thus, there is no propagation delay and the multiplication product can be computed quickly.

Description

[0001] Cross-references

[0002] This application claims priority and benefit to PCT / CN2024 / 085517, filed April 2, 2024, and PCT / CN2024 / 119240, filed September 16, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This invention relates to logic circuits for manipulating bits in an input binary string to generate arithmetic outputs. In particular, this invention relates to multiplication circuits. Background Technology

[0004] A processor includes logic circuits for performing arithmetic operations on numbers in binary string form, namely addition, subtraction, multiplication, and division. One of the most basic logic circuits is the binary adder.

[0005] Figure 1 A general-purpose half-adder circuit consisting of AND and XOR gates is shown. This half-adder has two input leads for single bits and two output leads: one for outputting the sum in single-bit form, and the other for generating a carry when both inputs are binary 1 signals—in which case the result is binary 10. bin It must be accommodated in a higher bit position.

[0006] When the two half-adders are pressed Figure 2 When connected as shown, a full adder is generated. The output of the full adder is the sum, plus the carry-out from the carry input of the full adder to be connected to the next significant position. The truth table of the full adder contains additional inputs to receive the carry bit passed from the immediately preceding lower position. A series of full adders connected in this way can perform addition on two binary strings, where the carry bit is passed to a higher significant position; this process is called the "ripple effect". Figure 3 A schematic diagram of four full adders connected in series to provide a 4-bit adder.

[0007] Each full adder must wait for a carry signal to obtain all the inputs needed to generate the output. The total wait time of a series of full adders causes an overall propagation delay. The propagation delay worsens as the number of cascaded full adders increases or as longer binary strings are added.

[0008] To mitigate the propagation delay, an improved circuit of a serially arranged full adder has been proposed, called a carry-look-ahead binary adder, such as... Figure 4As shown, the inputs of the full adder are copied to a logic component called carry-lookahead, which detects the input combination as a prediction of the carry and sends a carry signal to the downstream full adder even before the upstream full adder has completed its calculation. For example, when the upstream full adder generates a carry or propagates a received carry, it sends a signal to the downstream full adder in the form of a logic combination of "carry generation" and "carry propagation".

[0009] In adders used for longer binary strings, the time savings from carry-lookahead increases almost exponentially, but the associated cost and circuit complexity also increase exponentially, consistent with Moore's Law regarding the relationship between cost and complexity. Constrained by high costs and excessive complexity, the incentive to develop larger-capacity adders has gradually diminished.

[0010] Currently, there is no way to get rid of the ripple effect, because binary addition is essentially a serial addition process from the least significant bit to the most significant bit.

[0011] The effects of propagation delay are even more pronounced in multiplication. Multiplying two integers means repeatedly adding one number (the multiplicand) to the value of the other number (the multiplier) a corresponding number of times. Therefore, a multiplier circuit used to calculate the product of two binary strings contains multiple adders to perform the addition operation. The multiplicand and multiplier can also be called factors.

[0012] To perform multiplication on two binary strings, the first step is to obtain the partial product of the two binary strings. Each partial product is the product of the multiplicand and a specific bit in the multiplier, and this product is shifted according to the bit positions of the multiplier.

[0013] The partial products can be accumulated one by one into the sum. However, this means that each addition of a partial product introduces an update propagation delay.

[0014] Current methods for reducing propagation delay in multiplier circuits are mostly efficiency strategies. These include performing addition on different parts of the partial product separately, deferring all carries to a single summation in a dedicated final stage within a dedicated circuit called the carry-saving multiplier, identifying recurring patterns in the partial product addition, or performing multiple steps simultaneously. However, none of these methods eliminate or reduce the root cause of waiting for carries, nor do they eliminate the need for waiting for carries.

[0015] Therefore, it is desirable to propose a method and related circuitry that can alleviate the waiting requirements for carry bit signals. Summary of the Invention

[0016] In a first aspect, the present invention proposes a substitution method for replacing non-zero bits at multiple bit positions in two of four binary strings, the four binary strings being included in two generalized numbers to be added; the substitution includes the following steps: replacing one or more non-zero bits at the bit position containing the bit position with: a zero bit at the bit position, and one or more non-zero bits at other bit positions in two of the four binary strings, representing the same value.

[0017] The above aspects provide the possibility of freeing up space at one of the multiple bit positions in the binary string for the carry to be stored, thus eliminating the need for carry propagation. This can be seen in the steps of SEP, rSEPx, rSEPy, transformation A, and transformation B.

[0018] In a second aspect, the present invention proposes a method for multiplying a multiplicand and a multiplier, comprising the following steps: 2a) expanding the multiplicand and the multiplier to obtain a partial product in the form of a generalized number; 2b) performing multiple addition operations to accumulate the partial products and generate a multiplicative product; wherein the steps of claim 1 are performed before each addition operation.

[0019] Optionally, the multiplicand in step 2a) is a generalized number represented by two binary strings, and the multiplier is a number represented by at least one binary string.

[0020] Optionally, the multiplier in step 2a) is a generalized number. Preferably, the method further includes the following step before step 2a): replacing the non-zero bits in a four-bit block that includes two bits at the same adjacent positions in each binary string and represents a value with a four-bit block at the same position that has at least three zero bits and one non-zero bit and represents the same value as the four-bit block.

[0021] To avoid ambiguity, this technical feature relates to the execution of the two steps described in the embodiments: the first step is to perform semi-optimization on the generalized multiplier, which uses SEP to replace adjacent non-zero bits in any substring; the second step is to use rSEP to replace adjacent non-zero bits in the reversed sign substring.

[0022] Optionally, step 2a) includes: performing an expansion on the multiplicand for each consecutive block in the multiplier.

[0023] On the other hand: the multiplicand is a substring and generalized numbers And the multiplier provides the numbers; at least one binary string Step 2a) includes the following steps:

[0024] 7a) According to the following truth table, by multiplier Each bit in For the multiplicand Perform the expansion to obtain a partial product. , , ……, ,in

[0025]

[0026]

[0027] in and , , for The position pair; , for The position pairs, and so on;

[0028] 7b) Each iteration includes a partial product of at least two parts. , , Perform preprocessing and addition, repeating the process multiple times until all partial accumulations are added together to form the final product. The preprocessing includes the following steps:

[0029] 7c) Position The non-zero bit at that position is replaced with a zero bit, and the non-zero bit at that position represents the numerical value; and

[0030] At least one non-zero bit is provided at different bit positions in the same or another partial product of at least two partial products; such that

[0031] Position It can store the carry during the addition process.

[0032] Optionally, the multiplier includes generalized numbers. Another binary string ;in

[0033] Step 2a) includes:

[0034] According to the following truth table, by multiplier Each pair , For the multiplicand Perform the expansion to obtain a partial product. , , ……;in ,

[0035]

[0036]

[0037] in and , , for The position pair; , for The position pairs, and so on.

[0038] Optionally, step 7c) includes the following steps:

[0039] Transformation A According to the truth table, by and Generate the third pair of substrings and , and by and Generate the fourth pair of substrings and Where i is the bit position:

[0040]

[0041] Simplification and Transformation For each bit position By =1 and The non-zero value of =1 is replaced with zero bits, by and Generate substring and ;as well as

[0042] For each bit position By =1 and The non-zero value of =1 is replaced with and The zero position in the middle is... and Generate substring and ;

[0043] Transformation B According to the truth table, for , The values ​​are combined to generate a pair of substrings. and and further , The values ​​are combined to generate a pair of substrings. and :

[0044]

[0045] Summation operation Perform addition based on the truth table to generate the sum of two substrings X and Y:

[0046]

[0047] And, will and Add them together to generate a single binary string that is the sum of the two numbers.

[0048] Optionally, step 7c) includes the following steps:

[0049] The zero and non-zero bits in the binary substring are rearranged, including the following steps 1), 2), and 3) performed in a specific order:

[0050] Step 1) Apply the following formula to eliminate binary substrings. Any directly adjacent non-zero bits in the middle:

[0051]

[0052] as well as

[0053]

[0054] Step 2) Apply the following formula to eliminate binary substrings. and Any consecutive non-zero pairs arranged in the following specific order, i.e., changing x=1, y=0 followed by x=0, y=1 to x=0, y=0 followed by x=1, y=0:

[0055]

[0056] Step 3) Apply the following formula to eliminate binary substrings. Any directly adjacent non-zero bits in the middle:

[0057]

[0058] Or simplified to (5b)

[0059] in and Represents formatted binary substring pairs and Middle position The numerical value at the specified position; and the addition of the positive and negative components by applying the following formulas respectively:

[0060]

[0061] Optionally, the method includes the following steps prior to step 7a):

[0062] Process the multiplier as follows: :

[0063] i) Apply the following formula to eliminate binary substrings. Any directly adjacent non-zero bits in the middle:

[0064]

[0065] as well as

[0066]

[0067] Similar to formulas (3a) and (3b) above.

[0068] ii) Apply the following formula to eliminate binary substrings and Any consecutive non-zero pairs arranged in the following specific order, i.e., changing x=1, y=0 followed by x=0, y=1 to x=0, y=0 followed by x=1, y=0:

[0069]

[0070] Similar to formulas (4a) and (4b) above.

[0071] iii) Apply the following formula to eliminate binary substrings Any directly adjacent non-zero bits in the middle:

[0072]

[0073] Or simplified to

[0074] Similar to formulas (5a) and (5b) above, where and Represents formatted binary substring pairs and Middle position The numerical value of the digit at the location;

[0075] iv) Optimize the multiplier by splitting consecutive two-digit blocks according to the following formula. Execution reduction:

[0076]

[0077] in …, making , , , There is at most one non-zero digit in the multiplier, and the reduced multiplier... The resulting substring and express;

[0078] v) Determine Each pair of consecutive digits of the positive and negative strings of the reduced multiplier and The partial product, to obtain the partial product , , ……,in …;and

[0079] This makes step (a) become:

[0080] According to the following truth table, by multiplier Each pair , For the multiplicand Perform the expansion to obtain a partial product. , , ,……;in …,

[0081]

[0082]

[0083] in, and , , for The position pair; , for The position pairs, and so on.

[0084] In another aspect, the present invention proposes a unit multiplier for expanding a circuit, used to obtain a partial product between a generalized number and a binary string according to step 2a), including:

[0085] .

[0086] In another aspect, the present invention proposes a unit multiplier for expanding a circuit, used to obtain a partial product between two generalized numbers according to step 2a) of claim 4, comprising:

[0087] .

[0088] In another aspect, the present invention proposes a unit multiplier for expanding a circuit, used to obtain a partial product between two generalized numbers according to step 2a) of claim 6, comprising:

[0089] . Attached Figure Description

[0090] To facilitate further explanation of the present invention, possible embodiments will be described in conjunction with the accompanying drawings, wherein similar reference numerals denote similar components. The present invention may also have other embodiments; therefore, the specificity of the drawings should not be construed as replacing the foregoing general description of the invention.

[0091] Figure 1 This illustrates a half-adder used in the prior art;

[0092] Figure 2 This illustrates a full adder used in the prior art;

[0093] Figure 3 This illustrates a 4-bit ripple carry adder used in the prior art;

[0094] Figure 4 This illustrates a carry-lookahead binary adder used in the prior art;

[0095] Figure 5 A flowchart illustrating the steps of one embodiment of the present invention;

[0096] Figure 6 This is a sub-circuit used to convert binary strings of numbers into a generalized format, applied to... Figure 5 In the embodiments;

[0097] Figure 7 for Figure 6 The circuit diagram shows the internal structure of the sub-circuit.

[0098] Figure 8 It shows Figure 6 and Figure 7 The circuit diagram performs a generalization process on the binary string;

[0099] Figure 9 A logic circuit used to apply a specific equivalence principle transformation to the substring x;

[0100] Figure 10 A logic circuit used to apply a specific equivalence principle transformation to the y substring;

[0101] Figure 11 for Figure 9 and Figure 10Truth tables for transformations based on specific equivalence principles;

[0102] Figure 12 Show corresponding Figure 5 A schematic diagram of stages 3 and 4 in the flowchart;

[0103] Figure 13 For execution Figure 5 The dual-unit circuit module of transformation A in stage 3 of the flowchart;

[0104] Figure 14 for Figure 13 A single unit of logic circuitry;

[0105] Figure 15 for Figure 13 The truth table upon which the circuit module shown is based;

[0106] Figure 16 For execution Figure 5 The logic circuit for the simplification transformation in stage 3 of the flowchart;

[0107] Figure 17 for Figure 16 The truth table upon which the logic circuit shown is based;

[0108] Figure 18 It is a 2-unit circuit used for processing Figure 19 A pair of units to perform Figure 5 Transformation B in stage 3 of the flowchart;

[0109] Figure 19 for Figure 18 A single unit of a circuit;

[0110] Figure 20 for Figure 18 The corresponding truth table;

[0111] Figure 21 For use Figure 5 The bit addition circuit for the summation operation in stage 4 of the flowchart;

[0112] Figure 22 for Figure 21 The corresponding truth table;

[0113] Figure 23 for Figure 22 The equivalent truth table;

[0114] Figure 24 For adding two 8-bit generalized binary numbers;

[0115] Figure 25 It shows Figure 24 The sub-circuit in, where sub-circuit A4-2XY11 is as follows Figure 13As shown, sub-circuit 2SCV-21 is as follows Figure 16 As shown, sub-circuit A4-2XY12 is as follows Figure 18 As shown, sub-circuit A4-2XY13 is as follows: Figure 21 As shown;

[0116] Figure 26 A sub-circuit is shown for determining Figure 24 The sum calculated, propagated, and generated by the adder are converted from the generalized format to the two's complement binary string format.

[0117] Figure 27 for Figure 26 Logic circuits in sub-circuits;

[0118] Figure 28 for Figure 27 The truth table of the logic circuit;

[0119] Figure 29 for Figure 27 The truth table;

[0120] Figure 30 This demonstrates how to convert a 4-bit generalized binary number to a 5-bit classical binary format.

[0121] Figure 31 It is a type of "look-ahead carry" circuit with modified generation, propagation, and carry and sum outputs;

[0122] Figure 32 Truth table of stage 3 median depositional transformation for alternative methods;

[0123] Figure 33 For the corresponding Figure 32 Logic circuits;

[0124] Figure 34 For the corresponding Figure 32 Logic circuits;

[0125] Figure 35 For the truth table corresponding to transformation AB in the alternative method;

[0126] Figure 36 For the corresponding Figure 35 Logic circuits;

[0127] Figure 37 For the corresponding Figure 35 Logic circuits;

[0128] Figure 38 This is the truth table for bit addition in the alternative method;

[0129] Figure 39 For the corresponding Figure 38 Logic circuits;

[0130] Figure 40 For the corresponding Figure 38 Logic circuits;

[0131] Figure 41 A circuit for adding two 8-bit generalized binary numbers using an alternative method;

[0132] Figure 42 It shows Figure 41 The various sub-circuits in the diagram, including sub-circuit A4-2XY41 as follows: Figure 34 As shown, sub-circuit A4-2XY42 is as follows: Figure 37 As shown, sub-circuit A4-2XY43 is as follows Figure 40 As shown, sub-circuit 2SCV-21 is as follows Figure 16 As shown;

[0133] Figure 43 Here is the truth table for an embodiment that uses only transformation A;

[0134] Figure 44 for Figure 43 Feasible logic circuits;

[0135] Figure 45 for Figure 43 Another logic circuit;

[0136] Figure 46 As a substitute Figure 21 The logic circuit of the adder used in the middle adder;

[0137] Figure 47 This is a higher-level sub-circuit used to perform addition on two generalized numbers that have undergone semi-optimization in the second embodiment of the multiplier circuit;

[0138] Figure 48 It shows Figure 47 The three sub-circuits represented by the sub-circuit and their arrangement;

[0139] Figure 49 for Figure 48 A schematic diagram of the internal sub-circuit of one of the three sub-circuits;

[0140] Figure 50 It shows Figure 49 The logic circuits within each of the nine sub-circuits in the circuit diagram;

[0141] Figure 51 for Figure 50 Truth tables for logic circuits;

[0142] Figure 52 for Figure 48 A schematic diagram of the internal sub-circuit of one of the three sub-circuits;

[0143] Figure 53 It shows Figure 52 The logic circuits inside each sub-circuit shown in the circuit diagram;

[0144] Figure 54 for Figure 52 Truth tables for logic circuits;

[0145] Figure 55 for Figure 48 A schematic diagram of the internal sub-circuit of one of the three sub-circuits;

[0146] Figure 56 It shows Figure 55 The logic circuits inside each sub-circuit shown in the circuit diagram;

[0147] Figure 57 for Figure 55 Truth tables for logic circuits;

[0148] Figure 58 For the upper-level sub-circuit, it provides Figure 5 The adder used in one of the steps of the flowchart;

[0149] Figure 59 for Figure 58 A schematic diagram of the sub-circuit inside the sub-circuit shown;

[0150] Figure 60 It shows Figure 59 The adder sub-circuit inside each sub-circuit unit is shown in the sub-circuit diagram;

[0151] Figure 61 It shows the construction Figure 60 The circuit logic of the sub-adder in the adder sub-circuit;

[0152] Figure 62 for Figure 61 Truth tables for logic circuits;

[0153] Figure 63 This is a truth table for multiplying a generalized number by another generalized number;

[0154] Figure 64 Implementation shown Figure 63 The circuit block diagram with the truth table shown;

[0155] Figure 65 It shows Figure 64 Sub-circuits within a circuit module;

[0156] Figure 66 To achieve Figure 65 and Figure 64 The circuit shown is a multiplier circuit that multiplies a generalized number by another generalized number.

[0157] Figure 67 It shows Figure 66 Internal sub-circuits of the multiplier circuit;

[0158] Figure 68 It shows Figure 66 The circuit used to obtain a partial product in a multiplier circuit;

[0159] Figure 69 It shows Figure 68 A multiplication sub-circuit used to obtain a partial product in a circuit;

[0160] Figure 70 For simplification;

[0161] Figure 71 To achieve Figure 70 Circuit block diagram of truth table;

[0162] Figure 72 for Figure 71 The logic circuit inside the circuit module shown;

[0163] Figure 73 To utilize the truth table corresponding to the expansion of a generalized number from a regular single binary string;

[0164] Figure 74 To achieve Figure 73 Functional circuit module block diagram;

[0165] Figure 75 It shows Figure 74 The logic circuits inside the circuit module block diagram;

[0166] Figure 76 The block diagram of the multiplier circuit module is shown, where the multiplicand is an 8-bit generalized number and the multiplier is a 4-bit conventional binary string;

[0167] Figure 77 It shows Figure 76 Sub-circuits within the multiplier circuit module;

[0168] Figure 78 It shows Figure 77 One of the sub-circuits used to obtain the partial product;

[0169] Figure 79 for Figure 78 The sub-circuits inside the circuit module block diagram shown;

[0170] Figure 80 for Figure 83 The truth table corresponding to step (a) of a variant of the process;

[0171] Figure 81 for Figure 80The truth table corresponding to step (b) after step (a) in the truth table shown;

[0172] Figure 82 for Figure 83 Truth table corresponding to the sub-circuit schematic;

[0173] Figure 83 For use in Figure 6 The zero and non-zero bits in the binary string output by the sub-circuit are rearranged, added, or removed to create a semi-optimized sub-circuit, which is then applied to another sub-circuit. Figure 5 In the embodiments shown;

[0174] Figure 84 for Figure 83 The logic circuit in the sub-circuit diagram;

[0175] Figure 85 For use in Figure 6 Another sub-circuit, which rearranges, adds, or removes zero and non-zero bits in the binary string output by the sub-circuit, is used for semi-optimization. Figure 5 In the embodiments shown;

[0176] Figure 86 for Figure 85 The logic circuit inside the sub-circuit diagram;

[0177] Figure 87 for Figure 85 Truth table corresponding to the sub-circuit schematic;

[0178] Figure 88 For processing Figure 85 The sub-circuit outputting the sub-circuit;

[0179] Figure 89 for Figure 88 The logic circuit within the sub-circuit diagram;

[0180] Figure 90 for Figure 88 Truth table corresponding to the sub-circuit schematic;

[0181] Figure 91 Tables (a) and (b) are shown corresponding to the multiplier strategy called Lim Tree.

[0182] Formula List

[0183] The formulas are provided as alternative descriptions of some features of the embodiments described below. A list of formulas is provided according to their application for the convenience of the reader. This list is not exhaustive, as there may be embodiments that do not conform to the listed formulas but do not depart from the inventive concept. Furthermore, the specificity of the formulas should not be construed as a limitation or substitution of the generality of the invention.

[0184] Formula 1 involves an n-bit binary string. The generalization is that the string contains pairs of substrings. , and , .

[0185] Formula 2 involves An expression where the weight of each bit in the binary string is a positive integer power of 2 or 1, and the domain covers... to The range.

[0186] Formula 3 (a, b) relates to SEP for a substring of m (m≥1) 1s.

[0187] Formula 4(a, b) applies to m (m≥1) SEP of the substring

[0188] Formulas 5(a, b) relate to the generalized addend. With generalized addends Transformation A of the positive component.

[0189] Formula 6(a, b) relates to the generalized addend. With generalized addends Transformation A of the negative component.

[0190] Formula 7(a, b) involves the transformation of A. Simplification.

[0191] Formula 8(a, b) involves the transformation of A. Simplification.

[0192] Formula 9 involves the abbreviation z, which represents an n-bit generalized binary number. A pair of substrings x and y.

[0193] Formula 10 defines the set of values ​​for an n-bit generalized binary number z.

[0194] Formula 11 involves the definition of z and its to The range.

[0195] Formula 12(a, b) involves transformation A and subsequent transformation B of the simplified positive component substring x.

[0196] Formula 13(a, b) involves transformation A and the subsequent transformation B of the simplified negative component y substring.

[0197] Formula 14(a, b) involves the parallel summation of the positive and negative substrings of two generalized numbers after being processed by transformation A, simplification, and transformation B in sequence.

[0198] Formulas 15(a, b) relate to the generation of generalized numbers that perform inverse transformations containing positive and negative substrings. and dissemination A new definition.

[0199] Formula 16(a, b) involves the "final summation" logic of the inverse transformation.

[0200] Formula 17(a, b) relates to the generalized addend. With generalized addends The positive component of bit deposition.

[0201] Formula 18(a, b) relates to the generalized addend. With generalized addends The negative component of the deposition.

[0202] Formula 19(ac) involves the transformation of A. and Transformation AB of the positive substring.

[0203] Formula 20(ac) involves the transformation of A. and Transformation AB of the negative substring.

[0204] Formula 21(a, b) involves the parallel summation of positive and negative substrings of two generalized numbers that have been successively processed by the deposition transformation and the transformation AB.

[0205] Formula 22(a, b) involves parallel summation of positive and negative substrings after transformation A and simplification, without performing transformation B.

[0206] Formula 23(a, b) involves the multiplicand substring , Where i = 0, 1, 2..., according to the multiplier Each pair of substrings , Expand, where j = 0, 1, 2, ..., to obtain the partial product. , , ...

[0207] Formula 24(a, b) involves ySEP, which is used to eliminate all directly adjacent non-zero bits in the binary substring y.

[0208] Formula 25(a, b) involves the reverse rSEPx, which is used to eliminate adjacent non-zero pairs in binary substrings x and y arranged in a specific order. That is, the case of x=1, y=0 followed by x=0, y=1 is modified to x=0, y=0 followed by x=1, y=0.

[0209] Formula 26(a, b) involves xSEP, which is used to eliminate all directly adjacent non-zero bits in the binary substring x.

[0210] Formulas 27(a, b) involve independent parallel addition of the positive and negative components of a semi-optimized generalized binary number.

[0211] Formula 28(ad) involves simultaneously applying rSEPx and rSEPy to halve the multiplier using consecutive two bits in a block. Reduce, so that , , , There is at most one non-zero digit in the multiplier, and the reduced multiplier... The resulting substring and express.

[0212] Formula 29(a, b) involves the multiplicand substring , Where i = 0, 1, 2..., according to each multiplier digit Expand, where j = 0, 1, 2, ..., to obtain the partial product. , , ...

[0213] Formula 30 involves generalized numbers One of the two steps to perform semi-optimization: ... Subtract from its copy after shifting it one significant bit to the left, i.e. .

[0214] Formula 31(a, b) involves targeting Parallel logic operations, where it is assumed .

[0215] Formula 32(a, b) involves parallel logical operations that complement Formula 31(a, b) and are used to obtain semi-optimized generalized numbers.

[0216] Formula 33(a, b) involves the combination of Formula 31(a, b) and Formula 32(a, b) to enable semi-optimization of generalized binary numbers in parallel in a single step.

[0217] Formula 34(a, b) involves taking any substring... and Transform into and .

[0218] Formula 35(a, b) is an application Parallel logical operations.

[0219] Formulas 36(a, b) involve determining the bit string at the i-th level for both the Lim Tree and the Wallace Tree. The number of , where i = 0, 1, 2...

[0220] Formulas 37(a, b) relate to the number of bit strings for two 64-bit binary strings in a regular single-string format (rather than a generalized number of strings each containing a pair of x and y substrings) by applying a Lim tree and a Wallace tree, respectively. Detailed Implementation

[0221] The embodiments described in the following paragraphs are all based on the proposed General Equivalence Principle and Generalized Binary Number Format. Before elaborating on any embodiment, a binary string transformation called the "Specific Equivalence Principle" needs to be introduced first.

[0222] The principle of equivalence (generalized)

[0223] Any positive integer other than zero (i.e., a natural number), as long as its value is not 1, can be represented as the sum of two smaller positive integer components. However, if the component numbers can be both positive and negative integers, then any positive integer can be represented as multiple different pairs of integer components—the two component numbers can be both positive, both negative, or one positive and one negative. The sum of two integers can be represented as multiple sets of four component numbers with the same summation result.

[0224] Correspondingly, for a pair of binary strings to be summed, the zero and non-zero bits in the pair can be adjusted to obtain another pair of binary strings with the same sum. The principle of selecting multiple groups (not just one pair) of components, and that the sum of the components in each group is a constant, is the proposed generalized equivalence principle.

[0225] Generalized binary number format and generalization process

[0226] The proposed "generalization" process is used to re-express or reconstruct a regular binary string representing a certain value into a set or pair of binary strings whose sum equals the same value. For ease of distinction, the paired binary strings are called substrings, specifically labeled with the notations x and y in this specification. The value of each substring can be read in the same way as a regular binary string.

[0227] By employing various transformations designed according to the principle of equivalence, substrings x and y can be transformed into another pair of substrings x and y with different values ​​but the same sum.

[0228] Although in some embodiments, both the x and y substrings of a pair of substrings can be positive, it is preferable that the x substring represents a positive value and the y substring represents a negative value. This configuration provides a wider range of values ​​and allows for more flexible adjustments. Therefore, x substring - y substring = the value of the original binary string. However, it is also preferable that the value of the y substring is an absolute value, which needs to be subtracted from the x substring, rather than the y substring being negative. This is because negative numbers in the binary system and processor environment are represented using two's complement, which often contains many non-zero bits, a potential cause of carry values. Although this embodiment can handle a large number of non-zero bits, it is not conducive to the explanation and error checking of the embodiment when there are a large number of non-zero bits to be processed.

[0229] Therefore, a more accurate statement is: the substring y is the subtrahend, corresponding to the substring x as the minuend. However, repeatedly using the terms "minuend" and "subtrahend" can make the instruction manual slightly obscure. Therefore, in the following paragraphs, although the substring y takes its absolute value, it can be called a "negative" binary substring or a "negative component" substring, and its value is "negative"; the non-zero bits in the y substring can be called "negative bits," which is more intuitive for most readers. Conversely, the substring x can be called a positive component substring, and its value is positive; the non-zero bits in the x substring can be called positive bits.

[0230] When describing binary-related content in this manual, the terms "string" and "number" can be used interchangeably.

[0231] Provide the binary numbers of the addend and the augend, and convert each of them into a generalized binary number, i.e. and Each generalized binary number contains a pair of substrings, namely... and n-bit binary string The generalization of can be expressed by the following mathematical formula:

[0232]

[0233] in

[0234] and ,in ;and

[0235] <,> represents the set of possible values ​​for a variable.

[0236] It is a shorthand for the non-zero digits in the substring y, including the horizontal line above the digit 1.

[0237] The weight of each bit in a binary string is a positive power of 2 or 1.

[0238] therefore, It can be represented as:

[0239]

[0240] The domain coverage is to .

[0241] The algorithm based on the above content can be used... Figure 6 The circuit module shown is implemented by receiving an 8-bit binary string input and outputting a pair of 8-bit substrings, x and y. Figure 6 The internal structure of the circuit module is Figure 7 The logic circuit shown. When a number in binary string form is fed in... Figure 7 When configuring the logic circuit, a copy of the binary string is generated as the x substring, and a binary string of the same length, consisting entirely of zeros, is assigned to the y substring. This pairing completes the generalization process. However, if the sign bit of the binary string is non-zero, the binary string copy of the x substring does not contain that sign bit. The non-zero sign bit is placed at the same position (most significant bit) as the original all-zero y substring.

[0242] Therefore, the binary string 1000 0011 (decimal value -125), after generalization, yields the substring x 0000 0011 (decimal value 3) and the substring y 1000 0000 (absolute value 128 in decimal). As mentioned before, the substring y is the subtrahend and the substring x is the minuend, i.e., xy = 3 - 128 = -125.

[0243] By pairing, the original binary string is "generalized" because, according to the principle of generalized equivalence, the value of the string is no longer represented by a single binary string, but by any pair of possible x substrings and y substrings as subtrahends, and the summation of all substring pairs is exactly the same.

[0244] Preferably, the length of each substring in the x and y substrings is one bit longer than the original binary string. This extra bit increases the maximum value of the x substring by one binary order of magnitude, allowing the value of the original binary string to easily fall within the range of a larger minuend value. Subtracting the value of the y substring from this range yields the value of the original binary string.

[0245] "Specific" equivalence principle transformation

[0246] Box 1 details a highly practical conversion based on the equivalence principle. By understanding the Specific Equivalence Principle (SEP) conversion as described in this specification, the usage of generalized binary number formats can be more easily grasped.

[0247]

[0248] The purpose of SEP conversion is to eliminate all adjacent non-zero bits in a substring, and it can be performed independently and in parallel for each bit position.

[0249] Using positive strings as Negative strings are For a substring of m (≥1) ones, the specific equivalence principle can be expressed by formulas (3a) and (3b). The specific equivalence principle for a substring can be expressed by formulas (4a) and (4b).

[0250]

[0251] Figure 9 The left side shows the corresponding circuit block diagram 901, and the right side shows the underlying logic circuit unit 903 used for the SEP conversion of the x substring. Similarly, Figure 10 The left side shows the corresponding circuit block diagram, and the right side shows the underlying logic circuit unit used for the SEP conversion of the y substring. The corresponding truth table is as follows: Figure 11 As shown, the left half of the truth table involves the conversion of non-zero bits in the positive component x substring, and the right half of the truth table involves the conversion of the negative component y substring.

[0252] Box 2 below illustrates the SEP conversion, which is based on the possibility of re-representing a positive bit with a positive non-zero value of 1 as a larger number compensated by a smaller negative number, for example... At the same time, it follows the principle of equivalence. To ensure completeness, Box 2 shows that if the value of this bit is 0, then the output of the next higher bit is 0. In fact, this is passively determined by the active relocation of non-zero bits in the output.

[0253]

[0254] The following paragraph provides an example of applying the SEP transformation in Box 2 to a binary string. Taking the number 31 as an example, its 8-bit binary format is 0001 1111; after generalization, 0001 1111 is re-represented as the substring x = 0001 1111, and the substring y with all zeros = 0000 0000, because the value has no sign bit. Box 3 below shows the result of applying the SEP transformation shown in Box 2 to this substring x. The substring x is converted to 0010 0000 (decimal 32), and the substring y is converted to 0000 0001 (decimal 1). Therefore, in decimal... for The summation result remains unchanged, which conforms to the generalized equivalence principle. For ease of use, the above substring can be written as the recommended abbreviation described in formula (1), written as 0010 000. .

[0255]

[0256] As mentioned in the preceding paragraphs, the overall effect of the SEP transformation is to eliminate all directly adjacent non-zero bits in the substring x, but without changing the summation result 31 (i.e., 32-1). The SEP transformation must be applied uniformly to every bit position in the substring x.

[0257] Use abbreviation When representing non-zero bits in the substring y, a pair of substrings x=0001 0000 and y=0000 0001 can be written as 0001 000 on a single line. A 1 and a 2 cannot coexist at the same position. The two will cancel each other out and become zero.

[0258] The SEP transformation also needs to be applied to every bit position of the y substring, although no transformation effect can be shown in the example of an all-zero y substring. Box 4 below shows the SEP transformation described in Box 2 adapted to the y substring.

[0259]

[0260] The example in Box 4 includes a final step to simplify the SEP conversion output, which is not desirable because it adds an extra step to the entire embodiment.

[0261] Box 5 below discusses variations of the SEP conversion, which are based on Figure 11 The truth table in the code generates the output from the input, and no simplification step is required after the SEP transformation. The corresponding logic circuit is as follows: Figure 9 and Figure 10 As shown.

[0262] The SEP conversions in boxes 2 and 4 read a single bit as input and output two bits, while the SEP conversion in box 5 reads two bits as input, one from the current position i=1 and the other from the lower position i=0. If position i=0 does not exist because i=1 is already the least significant bit at the beginning of the binary string, then the non-existent bit at position i=0 is defined as having a value of zero. Furthermore, although the SEP conversion result in box 5 may contain bits from multiple positions, only the bit at position i=1 is included in the truth table. To facilitate reader attention to this, the SEP conversion output bit at position i=1 is shown without shading, while adjacent bits not included in the truth table are shown with shading.

[0263]

[0264] Examples i through iv in Box 5 show the SEP transformations for all four possible combinations of two digits (i.e., 00, 01, 10, 11) in the positive component x substring. These two digits are adjacent to each other in the same substring. Conversely, examples v through viiii in Box 5 show the SEP transformations for all four possible combinations of two digits (i.e., 00, 01, 10, 11) in the negative component y substring.

[0265] An example of applying the SEP conversion in box 5 to binary strings is shown in box 6. Taking the number 23 as an example, its 8-bit binary format is 0001 0111. After generalization, we get substring x = 0001 0111 and substring y = 0000 0000.

[0266] After performing SEP transformation on each bit based on the transformation in box 6, the substring x becomes 0010 1000 (decimal 40), and the substring y becomes 0001 0001 (decimal 17). The difference between x and y in decimal is 40-17=23 (consistent with the generalized equivalence principle). The above substrings can be written as the recommended abbreviation 001. 100 .

[0267] To give another example, consider the negative number -23, whose 8-bit two's complement format is 1110 1001. In all processors, the most significant bit is always designated as the sign bit; this is an industry standard. According to... Figure 7 and Figure 8 After generalizing the negative value 1110 1001, we get the substring x = 0110 1001 (decimal 105), which is a copy of the original binary string after removing the sign bit; at the same time, we get the substring y = 1000 0000 (decimal 128), which is a binary string with all bits except the sign bit being zero.

[0268]

[0269]

[0270] When using the recommended abbreviation, the above substring can be written as 110 1001. The difference between x and y in decimal is 105 - 128 = -23.

[0271] As described in Box 7 and the following paragraphs, it is usually necessary to perform substring simplification to remove non-zero bits in substring x that occupy the same positions as non-zero bits in substring y. Therefore, it is important to use the SEP transformation in Box 5 instead of the SEP transformations in Boxes 2 and 4 to minimize the number of simplification steps.

[0272] Therefore, the above content explains how to convert a number from a regular binary number to a generalized binary number, and how to process each component substring through SEP conversion to make it a form that can be used in subsequent stages.

[0273] First Adder Embodiment

[0274] Based on the information provided in the preceding paragraphs, embodiments involving related methods and logic circuits will now be described. These methods and logic circuits transform binary strings into a specific format such that the transformed binary strings can be summed by independent addition operations on each bit position (also called bit order). The embodiments include multi-bit adders, each comprising multiple independent adder units. Each adder unit can be used to perform summation on bits of the same bit order, independently of adder units that operate on bits at adjacent bit positions. No carry-out or carry-in leads are connected between the adder units.

[0275] Figure 5 This is a flowchart illustrating the stages according to one embodiment. Each stage can be executed by one or more logic circuits. A corresponding logic circuit diagram is shown next to each stage. Before a detailed explanation in subsequent paragraphs, each stage is briefly described below.

[0276] Phase 1: Provide the addend and augend in binary string form.

[0277] Phase 2: Based on the generalized binary number format, each binary string is converted into a "generalized binary number," where each generalized binary number consists of a group or a pair of binary strings. To distinguish them from regular binary strings, these strings will be called "substrings."

[0278] Phase 3: Connect two generalized binary numbers and These are converted into another generalized binary number with the same total value. However, the converted generalized numbers can be summed using parallel addition operations at each bit position in stage 4. The conversion itself comprises three independent transformations: Transformation A, Simplification Transformation, and Transformation B, each of which alters one of the two generalized binary numbers. and In a certain aspect.

[0279] Specifically, Transformation A performs a transformation on the generalized binary number based on the addition principle. During this process, before the actual summation is performed by independent adder units that perform parallel operations on different bit positions in stage 4, the carry value is pre-displayed and accommodated. This avoids the need to set up carry output and input leads between the independent adder units.

[0280] A simplification transformation is then applied to remove redundant bits from the generalized binary number generated by transformation A. Typically, but not always, a simplification transformation is performed after each transformation.

[0281] Subsequently, Transformation B performs a further transformation on the generalized binary number generated after Transformation A and the simplification transformation. Transformation B is also based on the addition principle, and therefore, similar to Transformation A, it pre-defines and accommodates any potential carry values ​​before the actual summation in stage 4.

[0282] However, transformation A and transformation B are different transformations, which will be explained in more detail in the following paragraphs.

[0283] • Stage 4: Perform a summation operation on the transformed generalized numbers generated in Stage 3. This operation sums the generalized binary numbers preprocessed by Transformation A (and subsequent simplification transformations) and Transformation B.

[0284] The summation is accomplished through multiple independent addition operations, each operating only on bits at the same position. As mentioned earlier, these independent addition operations can run in parallel because the transformation in stage 3 has preprocessed or accommodated all necessary carry-overs, thus preventing carry-overs from arbitrary lower to higher positions. However, the summation result is still a generalized binary number.

[0285] • Stage 5: Determine whether to add another number to the sum generated in Stage 4. If so, proceed directly to Stage 7, where the same simplification process as in Stage 4 is used to simplify the sum generated in Stage 4. Then, in Stage 1a, the new addend in binary form is provided. In Stage 2a, this new addend is generalized by converting it to a generalized number format. Then, Stage 3 is repeated, adding the new addend in generalized binary number format to the sum of the previous addition loop.

[0286] If stage 5 determines that no other numbers should be added, then in stage 6 the sum can be converted from a generalized binary number to a regular binary string. Therefore, the basic implementation may only include stages 1 to 6.

[0287] The following paragraph explains that, according to Figure 5 The flowchart illustrates the process of adding the numbers 13 and 14. Stage 1 is simple; selecting 13 as the addend and 14 as the sum completes this stage.

[0288] In Phase 2, the binary strings of the addend and augend are converted or "generalized" into generalized binary numbers. Each generalized binary number contains a set or pair of binary strings representing the digits or values ​​of that binary string. Since both 13 and 14 are non-negative, the sign bit is 0. Therefore, by providing a copy of the binary string of 13 as... The substring is generalized to a binary string of 13 and then compared with a string of all zeros of the same length. Substring pairing. Similarly, by providing a copy of the 14-bit binary string as... The substring is generalized to a 14-bit binary string and then compared with a string of all zeros of the same length. Substring pairing. Related content is shown in box 8 below.

[0289]

[0290] The next stage in the flowchart is stage 3, which involves transformations performed on two generalized binary numbers: transformation A and subsequent simplification, and transformation B.

[0291] Transformation A and subsequent simplification, as well as transformation B, preprocess carry-overs. These carry-overs would trigger a ripple effect in existing addition methods. The following paragraphs describe the transformations or preprocessing performed on the generalized binary strings 13 and 14.

[0292] Transformation A

[0293] Transformation A applies to the generalized addend according to the following formula. With generalized addends Execution process:

[0294]

[0295] For processing and The positive components; and

[0296]

[0297] For processing and The negative component.

[0298] Figure 13 (Sub-circuit A4-2XY11) is the attached diagram for the corresponding sub-circuit, which consists of... Figure 14 The unit logic circuit shown is composed of (sub-circuit A4-2X11). Figure 15 Transform the truth table corresponding to A.

[0299] Figure 15 The derivation of the truth table is shown in Box 9. As mentioned in the previous paragraphs, there are only four possible combinations of two bits: 00, 10, 01, and 11. Box 9 shows the relationship between the two positive substrings. , The derivation of related instances i, ii, iii, and iv outputs a new pair. and Substrings. Conversely, instances v, vi, vii, viiii and two negative component substrings. , Related, output a new pair and Substring.

[0300]

[0301] Column (a) shows the numerical values ​​of the two input bits, which come from substrings with the same sign component. Column (b) shows the sum of the two input bits. Column (c) is the output based on the sum in column (b). Column (d) shows that the transformation conforms to the equivalence principle.

[0302] Transformation A ensures that, in every instance, the bit is "shifted up" by one bit level, following the equivalence principle. This shift makes room for any carry from a lower position without changing the original total value.

[0303] Only instance IV outputs a larger value due to the sum of two non-zero input bits, which requires output... A carry is generated at position i+1 of the higher bit of the substring, i.e., 1+1=10. This gives position i of the original bit a value of zero, so that any similar carry from the value of the lower bit can be received and accommodated without further propagating the carry.

[0304] Instance i occurs when both input bits are zero, resulting in a zero output bit. This transformation simply shifts the zero output bit one bit higher in the substring with the same sign component. Thus, the original bit position i takes the value of zero, allowing it to receive and accommodate any similar carry from the lower bit position without further propagating the carry.

[0305] Examples ii and iii occur when there is only one non-zero bit at position i in each x substring. The sum of the bits at that position is actually the value of that single non-zero bit, and a SEP transformation is applied. The SEP transformation generates a non-zero bit at the higher bit position i+1, and simultaneously generates a non-zero bit with the opposite sign at the original position i as compensation. This has been explained in Box 2, i.e. In this way, the original bit position i takes the value of zero.

[0306] Instances ii, iii, and iv will shift any occupied non-zero bit position to the next higher bit position, thereby freeing up the position to accommodate the carry when instance iv appears at a lower bit position, eliminating any further propagation of the carry.

[0307] A carry is generated whenever two non-zero bits of the same sign component are added together, for example... ,or .

[0308] Since the substring y represents the value to be subtracted from the corresponding substring x, it represents a negative value. or Only smaller values ​​are obtained, without triggering any carry. Therefore, transformation A is only applied to substrings with the same sign component to reveal potential carry.

[0309] supply Figure 12 As a visual guide, this helps readers understand which substrings are used in each transformation of this embodiment. Figure 12 As shown, transformation A is applied to the substring and To generate and Additionally, if needed or in practical work scenarios, transformation A can also be applied to substrings. and to generate and .

[0310] Box 10 contains similar content to Box 9, provided for completeness, to illustrate how transformation A is applied to substrings of opposite component symbols.

[0311]

[0312] against and The derivation of the substring instances v, vi, vii, and viii, and the derivation of the substring instances in box 9. and The derivation for substring instances i, ii, iii, and iv is similar, and instances v, vi, vii, and viiii output a new pair. and Substring.

[0313] Only instance viiii outputs a larger value due to the sum of two (negative) non-zero input bits, which requires output... A carry is generated at position i+1 of the higher bit of the substring, i.e., 1+1=10. This gives position i of the original bit a value of zero, which can be used to receive carry values ​​from lower bit positions, preventing carry propagation.

[0314] Instance v occurs when both input bits are zero. Transform A shifts the output bit with the zero value one position in the output substring with the same sign component. This makes the original bit position i have a zero value, thus allowing any carry from the lower bit position to be received and accommodated, preventing the need for further carry propagation.

[0315] Instances vii and viiii are instances of the opposite sign components corresponding to instances ii and iii, appearing when there is only one non-zero bit at position i in each y substring. Their sum should be the output. Output a single non-zero value at the same position in the substring. The SEP transformation for a single non-zero bit is as follows: the non-zero bit of the same sign component at position i+1 in the next higher order is compensated by the non-zero bit of the opposite sign component at the same position i. This transformation conforms to the generalized equivalence principle, i.e. .

[0316] Therefore, all instances in boxes 9 and 10 include a method for making bit position i in one of two binary strings available for storing carry values, the method comprising the steps of: replacing a non-zero value at bit position i with zero, the non-zero value at bit position representing a numerical value; and providing at least one non-zero value at different bit positions in the two binary strings to represent equal numerical values.

[0317] Although transformation A is based on the addition of relevant bits and may even reveal potential carry-over values, it is not actually an addition process. This is because, through transformation A, two input values ​​become two output values, and no terms are lost. In a true addition process, two input values ​​become one output value.

[0318] Continuing with the example of 13 plus 14, box 11 shows the transformation A applied to the output of box 8.

[0319]

[0320] As shown in box 11, for each position i, transformation A can be applied bit by bit. The outputs of transformation A can be concatenated to generate multiple pairs of output substrings.

[0321] Simplification and Transformation

[0322] The previous paragraphs mentioned simplification transformations, or simply simplification, which are also applied to the output of transformation A. In fact, simplification transformations are applied after most transformations if deemed necessary. Their purpose is to remove unnecessary non-zero bits.

[0323] In simplification, if a pair of substrings x and y have non-zero bits at the same positions, these non-zero bits will cancel each other out and can be replaced by zero. This simplification process only applies to paired substrings x and y to conform to the generalized equivalence principle. In other words, if all bits at the same positions in a pair of substrings are non-zero, then... and Then the values ​​represented by these bits can be replaced with and And it will not substantially change the value represented by the substring.

[0324] The following formula describes the simplification process:

[0325]

[0326] and

[0327]

[0328] The corresponding truth table is as follows Figure 17 As shown. The digital circuit corresponding to this truth table is as follows: Figure 16 As shown (sub-circuit 2SCV-21).

[0329] Abbreviation Z

[0330] The abbreviation Z is used to represent an n-bit generalized binary number. A pair of substrings x and y, in the form of:

[0331]

[0332] in , and ,and Here

[0333]

[0334] The weight of each bit is a positive integer power of 1 or 2. Therefore, It can also be expressed as:

[0335]

[0336] The domain coverage is to This generalized binary abbreviation also applies to negative values ​​in two's complement form.

[0337] Continuing with example 13+14, box 12 shows the output after applying the simplification transformation to each bit position. (At position i=1) and The two non-zero values ​​in the value are replaced with zero.

[0338]

[0339] Box 12 shows that the simplification transformation is an operation between any pair of x substrings and y substrings.

[0340] Transformation B

[0341] Transformation B is applied to the two pairs of simplified substrings in box 12, i.e. , and , Similar to transform A, transform B is based on the summation of two bit values, but the output of transform B is different.

[0342] In summary, the function of transformation B includes: obtaining the sum of two bits and assigning the existing non-zero bits to only one of the two outputs. Transformation B uses the following formula:

[0343]

[0344] Applicable to positive components x substrings; and

[0345]

[0346] Applicable to substrings with negative y components.

[0347] Figure 19 (Sub-circuit A4-2X12) is the underlying logic circuit unit corresponding to formulas (12a), (12b) and (13a), (13b). Figure 20 for Figure 19 Truth table of a logic circuit. Figure 18 (Sub-circuit A4-2XY12) is included Figure 19 The attached diagram shows the sub-circuits of the logic circuit.

[0348] Figure 20 The derivation of the truth table is shown in Box 13. Any two-bit input has only four possible permutations: 00, 10, 01, and 11. Including the negative y substring, there are a total of eight transformation instances: instances 1, 2, 3, and 4 correspond to the following inputs: and In the case of substrings, the output is and Substring; Examples 5, 6, 7, and 8 correspond to the following inputs: and In the case of substrings, the output is and Substring.

[0349]

[0350] Transformation B performs the following operations: it adds the bits at the same positions in the substrings of the same sign component. Furthermore, Transformation B concentrates all non-zero values ​​into one of the substrings of the same sign component, thus making the other substring of the same sign component contain only zero bits and can be used to receive any carry value from lower positions.

[0351] In box 13, example 4 is the only instance that generates a carry because the non-zero values ​​in the two x substrings at position i are added together. After adding the two non-zero values, the carry is generated in the output substring. The higher-order bit position i+1 becomes a single non-zero value. Thus, the original bit position i is zero, allowing any similar carry from the lower-order bit position to be received and accommodated without further propagating the carry.

[0352] Examples 2 and 3 occur when there is only one non-zero bit at position i in the substring x. Regardless of which input substring x the non-zero bit is located in, it will be assigned to the same output substring. The output bits are in the same position because the values ​​have not changed. This makes another output substring... The middle position i can be used to store the carry value from the lower bit position i-1, without further propagating the carry. This directs the output to another substring. The output of Example 4 will not encounter any already occupied bits.

[0353] However, to be precise, only Example 2 involves the actual transformation of repositioning non-zero bits to another substring of x. Example 3 simply shifts the non-zero bits to the same position.

[0354] Example 1 occurs when both positions i in two identical substrings contain only zero bits. The pointer to the zero-valued bit is only stored in the output substring. Move one position.

[0355]

[0356] In box 14, each instance corresponds to a mirror image of the instances in box 13. Instance 8 is the only one that will move to the substring. The instance of the carry value is passed to position i+1 because it is the sum of two non-zero bits from two different substrings of y, both located at position i. This frees up the original bit position, making it zero, so that it can receive any carry from the lower bit position i-1.

[0357] Examples 6 and 7 occur when there is only one non-zero position at position i between two input substrings y. This non-zero position is included in the output substring. At the same position i in one of the substrings, ensure that the other substring is output. It is not occupied by any non-zero value, so it can receive any carry value without having to propagate the carry to a higher bit position.

[0358] Example 5: When both positions i in the two y substrings contain only zero bits, the storage pointer for the zero-value position is in the output substring. Move one position from the middle to a higher position.

[0359] Therefore, transformation B includes a method for making bit position i in one of two binary strings available for storing carry values, the method comprising the steps of: replacing a non-zero value at bit position i with zero, the non-zero value at bit position representing a numerical value; and providing at least one non-zero value at different bit positions in the two binary strings, representing equal numerical values.

[0360] Figure 12 As shown, transformation B is applied only to substrings with the same sign, that is, only between substrings x or only between substrings y, and also returns two substrings with the same sign.

[0361] By applying transformation A and subsequent simplification, as well as transformation B, all carry-overs have been revealed and pre-accommodated.

[0362] Continuing with the example of 13 plus 14, the substring at the top of box 15 below is the simplified output from box 12. The transformation B applied to each bit is shown in box 15.

[0363]

[0364] Parallel summation operation

[0365] Stage 4 involves a summation operation, where a multi-bit adder is used to sum the substring generated in Stage 3. The sum bits X and Y are generated from the same positive and negative components, respectively, as shown below:

[0366]

[0367] Stage 4 is not a transformation, but an actual addition operation, because the two input numbers (including the substring) are different. , and , This generates only one output number (including the substrings X and Y). The adder will... , and , The input bits are recalculated to generate the summation output bits X and Y.

[0368] The logic circuit of the adder is as follows: Figure 21 As shown in the figure (sub-circuit A4-2XY13), the corresponding truth table is as follows: Figure 22 As shown (see equivalent truth table) Figure 23 ).Notice, Figure 22 Using abbreviated notation, the summed substrings x and y are represented as Z. Note that this is different from the notation used to represent non-zero bits in the substring y as "". The abbreviation of "" is not the same as the abbreviation of "".

[0369] Figure 21As shown, the adder (sub-circuit A4-2XY13) in this example is simply an OR gate for inputs with the same sign component. There is no need to consider carry-overs from lower-order bits or propagate carry-overs to higher-order bits because transform A, the simplification transform, and the subsequent transform B have already avoided the situation where both substrings of the same sign component have non-zero bits. For substrings of the same sign component, only the following input cases will occur: 0+0, 1+0, or 0+1. Since 1+1 will not occur, the summation can be completed simply by summing the non-zero bits of each substring of the same sign component.

[0370] In this way, this embodiment can perform independent parallel summation at each bit position to obtain the final pair of X and Y substrings, without waiting for carry propagation from lower-order bits. The corresponding truth table is as follows: Figure 22 As shown.

[0371] However, if the summation results X and Y need to be used for further addition operations, a simplification transformation is applied to remove redundant non-zero bits. The equivalent truth table is as follows: Figure 23 As shown.

[0372] Figure 12 This shows all four substrings after complete transformation. , and , Both are used to generate substrings X and Y.

[0373] Continuing with the example of adding 13 to 14, the substring at the bottom of box 15 is copied into box 16 below. The adder in stage 4 generates the output, as shown in box 16.

[0374]

[0375] However, it is preferable to apply simplification transformations to X and Y, especially when X and Y will be used cyclically to perform further addition with another number.

[0376] Overview of the First Adder Embodiment

[0377] Figure 24 This is a sub-circuit module used to perform addition on two 8-bit generalized binary numbers, assembled from the logic circuits described in the preceding paragraphs. Figure 25 It shows Figure 24 The underlying layout of the adder logic circuit within the sub-circuit module. Figure 25 The different sub-circuits can be viewed in enlarged versions in the corresponding attached diagrams: Figure 13 Used in sub-circuit A4-2XY11, Figure 16 For use in sub-circuit 2SCV-21, Figure 18 Used in sub-circuit A4-2XY12, Figure 21 Used for sub-circuit A4-2XY13.

[0378] Box 17 shows another example, in which the use of Figure 24 Adder =10 1 101 (representing the generalized binary number 109 in decimal) and =0100 10 (The generalized binary number representing the decimal number 59) The steps for performing the summation will be explained in this embodiment. The sum is... 1 1 01000 (represents the generalized binary number 168 in decimal).

[0379]

[0380] More addition loops

[0381] If there are more numbers to be added, then stage 5 will still be in the generalized form of summation, directly leading to stage 7 for performing simplification first (e.g., ...). Figure 5 (As shown), and then repeated in the next addition loop. The new number to be added is provided in stage 1a, processed into a generalized number format in stage 2a, and then fed into stage 3. If there are no more numbers to be added, stage 5 will lead to stage 6 (as shown). Figure 5 As shown in the figure, in this stage, the final generalized number containing the substrings x and y is inversely converted by using a "carry-lookahead" inverse conversion circuit.

[0382] inverse conversion

[0383] In stage 6, the sum obtained in stage 4 is converted from a generalized binary number represented as two substrings back into a regular single binary string, such as... Figure 5 As shown. However, before starting the inverse conversion, a simplification transformation is applied again to replace all redundant non-zero bits in the X and Y substrings. The simplified substrings are then combined into a single binary string using the inverse conversion sub-circuit. Mathematically, this can be expressed as converting (n-1) bits... Convert the substring to an n-bit two's complement binary string. .

[0384] The inverse conversion can only be performed serially by summing the substrings X and Y, starting from the least significant bit. This is because each bit position can only be inverted by combining carry values ​​from lower-order positions. In other words, this embodiment postpones this serial operation until all addends have been summed in generalized number format, so even for millions of addends, there is only one serial addition process.

[0385] However, to improve the addition speed of the X and Y substrings, any conventional method that can speed up serial addition can be used. For example, by generating a signal... With propagation signal The carry-lookahead clause can be modified by making the following replacements:

[0386]

[0387] The final summation can be expressed by the following formula:

[0388]

[0389] When the "carry" of each bit has already taken precedence, among which The carry is the result of the modified "look-ahead carry circuit".

[0390] The above logic is as follows Figure 26 As shown, the underlying logic circuit is as follows Figure 27 As shown, the corresponding truth tables are as follows: Figure 28 and Figure 29 As shown. Figure 27 It also involves the logic of "final summation". This is used to convert the inverse of a binary substring of and into a regular two's complement binary format, which combines Figure 29 The predictive input of the truth table. Figures 26 to 29 Similar to the classic carry-lookahead circuit, but the generation and propagation follow formulas (15a) and (15b). Therefore, this logic describes a type of "carry-lookahead" circuit.

[0391] Specifically:

[0392] In classic carry-lookahead, if both inputs are "1", there is generation (gi=1); if either input is "1", there is propagation (pi=1). In a carry-lookahead inverse converter circuit, the opposite is true: if bit y is "1", there is generation (gi=1); if both inputs are "0" (xi=yi=0), there is propagation (pi=1).

[0393] In classic carry-lookahead, the presence of a carry in the lower bit and its propagation in the adjacent higher bit (as well as cascaded group generation and propagation) ensures that the carry continues to propagate. Similarly, but differently, in a carry-lookahead-like inverse converter circuit, the presence of a carry in the lower bit and its propagation in the adjacent higher bit (as well as cascaded group generation and propagation) does not serve to propagate the carry, but rather to ensure that the non-zero y-bit continuously "moves" to higher bits.

[0394] In classic carry-lookahead, if (i) any one of the three inputs is "1"; or (ii) all three inputs are "1", then a sum bit exists (Si=1). However, in a carry-lookahead-like inverse conversion circuit, if (i) the positive bit originally existed at that position and is retained there, and is not canceled by the incoming y bit propagated from the lower significant bit; (ii) it is generated by the presence of a y bit at a specific position; or (iii) it is generated by a combination of generation (relatively lower bit) and propagation (relatively higher bit), then the equivalent positive x bit of the sum bit exists (Si=1). i=1).

[0395] Figure 30 A sub-circuit module is shown for converting a 4-bit generalized binary number to a 5-bit classic two's complement number, with the added bit being the sign bit. After conversion, the summation result will be displayed to determine if it is actually negative.

[0396] Figure 30 The internal sub-circuit is Figure 31 The modified carry-lookahead circuit 2101 is shown. Subcircuit 2101 is completely consistent with any standard "carry-lookahead logic algorithm" provided in undergraduate textbooks on digital logic electronics. It takes a pair of 4-bit substrings x and y as input to generate the modified generate and propagate bits; each bit in both substrings is fed as an input. Figure 28 The logic circuits at the corresponding positions in the sub-circuit array shown.

[0397] Figure 31 The output of the array is a single 5-bit two's complement number string, where the leftmost bit represents the sign of the binary number. If the sum is positive, the leftmost bit is "0"; if the binary number is negative, the leftmost bit is "1". This is the concept of a classic two's complement number. The inverse conversion of a generalized binary number will generate a classic two's complement number with one more bit, the extra bit representing the sign of the binary number.

[0398] therefore, Figure 31 The logic circuits in the system can also restore the sign of the sum to the binary output string when the sum is negative, thus converting the binary string into a true two's complement representation.

[0399] Continuing with the example of 13 plus 14, the substring at the bottom of box 16 can be converted to a classic two's complement number using a "carry-lookahead" inverse conversion circuit. The final output is shown in box 18.

[0400]

[0401] It can be seen that the final sum is X=27, while the original sum of the addend and addend is 13+14=27.

[0402] Subtraction

[0403] Subtracting the subtrahend from the minuend can be easily achieved by immediately reversing the x and y substrings of the subtrahend after generalization. Subsequently, the minuend and the "reversed subtrahend" can be regarded as the addend and addend, and the two generalized numbers can be summed by using the addition method in the above embodiment.

[0404] Alternatively, the binary string of the negative subtrahend can be provided to the processing system in classic two's complement format before generalization.

[0405] Second Adder Example

[0406] Another embodiment employs a different set of transformations to allow bit addition at each identical bit position to be performed simultaneously as a parallel process. This different set of transformations offers various advantages, such as fewer transformation stages, but its underlying principle is the same as that discussed in the first embodiment. Overall, the transformed substrings do not generate carry values ​​when added, thus allowing for addition without ripple effects.

[0407] This embodiment adopts and Figure 5 The flowchart shown is the same process, but different transformations are used in stage 3 and different summers are used in stage 4.

[0408] Site deposition transformation

[0409] In stage 3 of the second embodiment, a bit deposition transformation is used to integrate two substrings with the same sign component. If a bit in the first x substring has a zero value, and a bit at the same position in the second x substring has a non-zero value, then the non-zero value is transferred from the second x substring to the same position in the first x substring. If the first substring has a non-zero value at that position, then the non-zero value in the second x substring is not transferred. In short, the bit deposition transformation fills as many "empty" or zero bits as possible in one of the x substrings by transferring all non-zero bits at the same position in the second x substring, thereby clearing the second x substring as much as possible. Visually, this process resembles deposition, hence the name of this stage. The above rules also apply to the y substring with the opposite sign component.

[0410] This depositional transformation can be expressed mathematically as follows:

[0411]

[0412] and

[0413]

[0414] The logical truth table of the bit deposition transformation is as follows: Figure 32 As shown. Figure 33The corresponding Figure 32 The logic circuit unit of the truth table. Figure 34 Two circuit modules are shown, each containing Figure 33 The logic circuit units shown are used, one for the x substring and the other for the y substring.

[0415] For example, the deposition of the generalized substrings of the digits 13 and 14 is shown in box 19 below, where the non-zero bits are from... Transfer to Since the two substrings have the same sign and the same bit position, the non-zero bits after the transfer have the same value, and the four substrings... , , , The total value remains unchanged.

[0416]

[0417] Transformation AB

[0418] Transform AB performs a transformation on the input bits of the same sign component substring, accommodating potential carry, i.e., only when... and Between, and only and The transformation is performed between these values. This is because a carry-over is only possible when the value increases. The mathematical expression for this transformation is as follows:

[0419]

[0420] and

[0421]

[0422] Figure 35 To transform the truth table of AB. The asterisks in the truth table are related to... ,as well as Instances of these are excluded from the table because the bit deposition transformation has prevented the occurrence of such instances.

[0423] Figure 36 The logic circuit unit for the transformation AB of the positive x substring is shown. If the leads are connected to the corresponding input data from the "negative" y substring, then... Figure 36 The same logic circuit unit in the code can also be used for this y substring. For example... Figure 37 As shown, the top sub-circuit module 4001 is used for the x substring, and the bottom sub-circuit 4003 is used for the y substring. Box 20 shows... Figure 35 Derivation of the truth table. For the substring x, the input to transformation AB is the bit position. Transformation AB is a single-step execution of transformations A and B.

[0424] More specifically, , Transformation B should be performed, and , Transformation A should be performed. However... It should not be transformed twice. Therefore, in box 20, there is only one bit. Perform transformation B, and the two bits , Perform transformation A. Note that for instance 7 in box 20, further bit simplification should be performed on the output at i=1 to... , Updated to , .

[0425]

[0426] Box 21 is the same as Box 20, except that Box 21 involves the y substring. Note instance 7 in Box 21, which is similar to instance 7 in Box 20; this instance should also undergo further bit reduction.

[0427]

[0428] Box 22 shows Figure 35 The derivation of the substitution of the truth table for positive components. , In this situation, to avoid Transformed twice, for two bits Perform transformation B, while applying it to a single bit. Perform transformation A.

[0429]

[0430] The advantages of the deposition step can be seen in boxes 20 and 21, where instances 3 and 4 are marked as impossible instances. This reduces the number of instances that need to be processed. Furthermore, grouping non-zero values ​​into only a substring is faster and simpler than processing instances 3 and 4. Boxes 23 and 22 are identical, but focus on the negative sign component. , , .

[0431]

[0432] Summation of AB outputs

[0433] For the three substrings generated by applying transform AB to the substring x as shown in box 20 or to the substring y as shown in box 21, each permutation of the three different input bit values ​​gives three output bit values. Due to the influence of the SEP transformation, one of the three output bits belongs to the opposite sign component.

[0434] By observation, a specific combination of bits in a binary substring with the same symbol component yields the sum of the output bits at position i. Figure 38 Some instances in the truth table shown are included due to experimental observations.

[0435] On the other hand, some instances or permutations of the input bits are not shown in the table because these permutations have been avoided or eliminated by applying transformation AB. All available permutations are shown in the table.

[0436] The following are the corresponding mathematical formulas for this truth table:

[0437]

[0438] As can be seen from the table or formula, the sum of each bit position can be obtained from the bits in the three substrings of the same sign component, as well as the bits at the current position i and the lower position i-1.

[0439] Figure 39 For the corresponding Figure 38 The logic circuit unit of the truth table shown clearly shows five input leads and one output lead. Figure 40 The top is based on Figure 39 The block diagram of the sub-circuit 4301 for the logic circuit unit of the x substring. Figure 40 The bottom is the corresponding block diagram of sub-circuit 4303 for the y substring, which is the same as sub-circuit 4301 for the x substring, but its input leads are connected to obtain input from the y substring.

[0440] Figure 41 This is a block diagram of the subcircuit module for adding two 8-bit generalized binary numbers in this embodiment. Figure 42 It shows Figure 41 The details of the sub-circuits have been described separately in Figure 34 (Sub-circuit A4-2XY41) Figure 37 (Sub-circuit A4-2XY42) Figure 40 (Sub-circuit A4-2XY43) and Figure 16 (Sub-circuit 2SCV-21) is shown.

[0441] Box 24 shows another example illustrating the four steps described above. Figure 41 The adder in the middle can calculate =10 1 101 (representing the generalized binary number 109 in decimal) and =0100 10 The sum of (the generalized binary representation of the decimal number 59). The sum is =1 1 01000 (represents the generalized binary number of the decimal number 168). The details of each step are shown below.

[0442]

[0443] After obtaining the sum, convert the sum back to a regular binary string.

[0444] Various embodiments of bare adders

[0445] Because the entire process from the generalization of the addend and augend to the summation of the transformed generalized binary strings involves multiple distinct stages, each of which can be implemented as an independent circuit module and interconnected, the various embodiments include these distinct stages. For example, transformation A can be licensed, sold, used, or supplied as part of algorithm software, physical logic circuitry, or a processor chip, without being tied to the simplification transformation and transformation B. Similarly, transformation B can also be licensed, sold, used, or supplied as part of algorithm software, physical logic circuitry, or a processor chip, without being tied to the simplification transformation and transformation A. In finite cases, for adders performing parallel addition, binary strings transformed only by transformation B and without transformation A can also be summed, as shown in box 25: adding 7 to 7, i.e., 111 + 111 = 1110 (decimal 14), because the carry has been pre-processed.

[0446]

[0447] For the numbers 23 and 39, transformation B can also be used to preprocess the carry, as shown in box 26, so that the processed binary strings can be added together by parallel addition.

[0448]

[0449] However, as shown in box 27, an attempt to preprocess the carry of 31 plus 47 using Transformation B demonstrates that applying Transformation B alone may be insufficient to pre-eliminate all carries in some scenarios. Therefore, it is suggested to further employ Transformation A to perform the processing, as shown below. However, there may be other solutions or transformations that are neither Transformation A nor within the scope of this patent application, which can be used to address this deficiency of Transformation B. Therefore, the use within this context does not preclude Transformation B from being independently promoted, sold, and licensed, nor does it preclude its use in conjunction with other binary string processing procedures.

[0450]

[0451] Box 28 is a continuation of Box 27, showing that after applying transformation A, two binary strings are generated, which can be summed using parallel addition operations without the risk of triggering a carry.

[0452]

[0453] As shown above, in some cases, the transformation of transformation B can be applied independently without the need for the simplification transformation and transformation A. This paper does not provide an adder for performing the parallel addition operations described above, because once the reader grasps the concepts discussed, various different multi-bit adder designs can be conceived.

[0454] An example of an adder using only transformation A.

[0455] In another embodiment, the steps are the same as in the first embodiment except that transformation B is not applied; that is, the simplification transformation is performed after transformation A and then the process stops. The following step (c) can be used to sum the two pairs of substrings generated.

[0456] (a) Transformation A

[0457] (b) Simplification

[0458] (c) Add the positive and negative strings respectively by applying the following formula;

[0459]

[0460] The logical truth value is as follows: Figure 43 As shown, the logic circuit is as follows Figure 44 and Figure 45 As shown.

[0461] In this embodiment, the effect of transformation B in preventing carry has been integrated into the logic circuit, as shown in the truth table.

[0462] Although preferred embodiments of the invention have been described above, those skilled in the art will understand that various variations or modifications may be made in design, construction or operational details without departing from the scope of the invention as defined by the appended claims.

[0463] For example, for any combinational logic circuit, there are many other logically equivalent circuits that conform to the relevant truth table and have the same input / output. These circuits are also embodiments of the present invention and are within the protection scope of this application.

[0464] Figure 46 An alternative is shown Figure 21 The adder used in the middle is a safety measure in case of unexpected carry, to prevent system crash.

[0465] In many written works relating to the same or similar technical fields, the output is often described as a physically different entity from the input, as this makes it easier for the reader to understand. For example, one could say that an input substring is transformed into an output, and that the output is the modified substring. However, this physical imagery and corresponding terminology should not be a limitation of the patent scope. For example, it should not be required that the output be recorded in a register or memory in a different part than the input, or even that the output must overwrite the input.

[0466] First embodiment of multiplier circuit

[0467] In multiplication, the multiplicand is added to itself the number of times indicated by the multiplier. For example, 123 (multiplicand) × 48 (multiplier) means adding 123 48 times.

[0468] In existing technology, both the multiplicand and multiplier are input to the multiplier circuit as conventional single binary strings, and the product is calculated using a two-stage process. In the first stage, the multiplicand is expanded bit by bit of the multiplier to provide several binary strings called partial products. If the multiplier bit is 1, each partial product is a copy of the multiplicand; if the multiplier bit is 0, the partial product is a string of all zeros; and all partial products are shifted so that the least significant bit of each partial product is in the same position as the corresponding multiplier bit. In the corresponding array-type logic circuit, this expansion is hardwired and can be performed simultaneously on all permutations of multiplying the multiplicand and multiplier bits. The multiplication operator for two single bits can be simply an AND gate. The two single-bit inputs have only four possible input combinations, as shown in the formula on the left side of box 29a, and the corresponding product is a single-bit output of the value shown on the right side.

[0469]

[0470] In the second stage, all partial products are added together, and the sum is the multiplicative product. If the partial products are added one by one, a set of 8 partial products requires 7 addition operations to sum, with each addition being one iteration in the sequential process. If a parallel approach is used, a total of 3 iterations are needed to complete the 7 addition operations. This is because the first iteration reduces the 8 partial products to 4 new partial products, the second iteration reduces the 4 partial products to 2 new partial products, and finally, the third iteration reduces the 2 partial products to the final product.

[0471] This embodiment uses a multiplier circuit with similar two-stage operation, but the multiplicand, multiplier, and their partial product are all generalized binary numbers, and the addition can be completed using the adder embodiments described in the previous sections.

[0472] For ease of explanation, the generalized binary number will be referred to as "generalized number" in the following text.

[0473] In other words, each pair of partial products to be added is preprocessed: first, transform A is performed, then simplification is performed, and then transform B is performed. Transformation A has been described in the relevant paragraphs of boxes 9 and 10, and transform B has been described in the relevant paragraphs of boxes 13 and 14. Transformations A and B involve making the bit at each position i of one of the two binary strings available to receive a carry value without propagating the carry to the next higher bit position; it includes the following steps: replacing the non-zero value at bit position i with zero, where the non-zero value at bit position i represents a certain value; and providing at least one non-zero value at different bit positions in the two binary strings to represent equal values. Variations or combinations of transforms A and B can also be used as alternatives. For ease of description, these methods will be referred to as the AB method below, and the relevant adders will be referred to as AB adders. The following describes the operation of 13×13×13 in a multiplier circuit that uses an AB adder to accumulate partial products. First, 13×13 is performed, and then the resulting product is multiplied by 13.

[0474]

[0475] The standard binary string representation of 13 is 1101. The simplest way to generalize a standard binary string is to assign it as a substring x and pair it with a newly generated substring y that has a value of zero; that is, x = 1101 is paired with y = 0000. Expanding two such generalized numbers produces a partial product, which is also a generalized number, as shown in box 30a. Each bit position in each partial product is a pair of x and y bits obtained by multiplying two pairs of x and y bits, one pair from the multiplicand and one pair from the multiplier.

[0476] Box 30b shows all four meaningful possible combinations of this type of two-bit input; it is unnecessary to show combinations containing a pair of zero x and y bits, since their product is necessarily also a pair of zero x and y bits. Furthermore, any pair of non-zero x and y bits will automatically cancel out to zero, since the y bit represents the value to be taken from the x bit.

[0477]

[0478] The partial products in box 30a are shown as four partial products summarized in the left side of box 31, which are derived from the four-digit length of the multiplier.

[0479] The right side of box 31 shows the result of the partial product on the left after processing: transformation A is performed first, followed by simplification. Transformation A is applied to the two generalized numbers that are about to be added. At this point in this example, one addition operation processes the top two pairs of x,y substrings, and another addition operation processes the bottom two pairs of x,y substrings. Preferably, the two addition operations are performed simultaneously; however, in less efficient embodiments, these addition operations can also be performed sequentially.

[0480] As mentioned in the previous paragraph, simplification refers to the transformation that replaces the non-zero bits at the same position in the substrings x and y with zero bits because they cancel each other out. If the substring y is represented as a negative value in two's complement form, this transformation is not convenient to apply because it requires filling the leading position with non-zero values, which is different from absolute values.

[0481]

[0482] Transformation B is then performed on the simplified data on the left side of box 31 to generate the data shown on the left side of box 32. The processed generalized numbers are then summed to obtain the data on the right side of box 32.

[0483]

[0484] If an iteration involves simultaneously adding every two partial products, the number of partial products is halved after each iteration. This strategy is described elsewhere in this specification as the Limtree method.

[0485] In array-type multiplier circuits, the number of iterations required to sum a certain number of partial products into a generalized number, based on a predetermined multiplier string length, is hardwired into the circuit. For a circuit with an 8-bit multiplicand and a 4-bit multiplier, four partial products need to be accumulated in two iterations. In a 64-bit processor embodiment, the 64-bit multiplier generates 64 partial products, each a pair of x and y substrings, requiring six iterations to complete the summation.

[0486] Therefore, a second iteration is required to add the two new partial products shown on the right side of box 32. After applying transformation A to the new partial products and performing simplification, the data shown on the left side of box 33 is obtained.

[0487]

[0488] Then, transformation B is applied to the data on the left side of box 33, resulting in the data on the right side of box 33. Next, the data on the right side of box 33 are added together to obtain the generalized number in box 34, which is the product of 13 × 13 = 169.

[0489]

[0490] Multiplying this product again by the same value 13, the partial product generated in the first stage is shown in box 35. The details of the expansion process are similar to those shown in box 30a, and will not be repeated here.

[0491]

[0492] The partial products in box 35 are summarized and shown on the left side of box 36, containing four generalized numbers. In the first iteration, transformation A is applied to every two partial products, followed immediately by simplification, resulting in the data on the right side of box 36.

[0493]

[0494] Transformation B is then applied to the data on the right side of box 36, and the result is shown on the left side of box 37. Next, every two processed partial products are added together to obtain the new partial product shown on the right side of box 37.

[0495]

[0496] The second iteration begins by applying Transformation A to the remaining two partial products on the right side of box 37, followed by simplification to generate the data on the left side of box 38. Then, Transformation B is applied to generate the data on the right side of box 38.

[0497]

[0498] Box 39a shows the sum of the data on the right side of Box 38, which is a generalized number with the value 2197, corresponding to the result of the operation 13×13×13.

[0499]

[0500] Subsequently, it can be combined Figure 30 The inverse conversion process converts the generalized number in box 39a into a regular single binary string.

[0501] The above steps can be performed Figure 66 The array-type multiplier circuit 6601, shown in block diagram form, is implemented in this circuit. This multiplier circuit 6601 includes components for an 8-bit multiplicand. with 4-digit multiplier The input leads are 6603, and the output leads are for products up to 12 bits in length.

[0502] Both the multiplicand and the multiplier are generalized numbers. Therefore, there are two 8-bit input leads for the x and y substrings of the multiplicand. Similarly, there are two 4-bit input leads for the multiplier and two 12-bit output leads for the product.

[0503] Figure 67 The diagram shows a sub-circuit in multiplier circuit 6601, including: an expansion circuit 6701 for generating a partial product, a processing sub-circuit 6705 for performing a transformation on the partial product, and the transformed partial product is suitable for addition by adder sub-circuit 6707 without carry propagation.

[0504] The unfolded circuit 6701 is directly connected to Figure 66 The input lead 6603 on the middle circuit module distributes the input data to four expanded sub-circuits 6701a. Details of each sub-circuit can be found in [reference needed]. Figure 68 .

[0505] Each expansion sub-circuit 6701a receives the complete multiplicand as input, but only receives the corresponding pair of multiplier bits x and y 6803, and outputs the partial product obtained by expanding the multiplicand with the pair of multiplier bits x and y. Although not shown in the figure, it should be understood that the partial product is shifted according to the multiplier bits x and y, and all bits at the shifted positions are set to zero. The logic circuit of the expansion sub-circuit 6701a is as follows: Figure 69 As shown, it contains eight multiplication sub-circuits 6901.

[0506] Each multiplier subcircuit 6901 has two input leads, each for a pair of x, y bits. One of the two input leads is connected to the input lead 6603 on the multiplier circuit 6601 corresponding to the pair of multiplier x, y bits, making that pair of multiplier x, y bits a common factor for all multiplier subcircuits 6901. The other input lead of the multiplier subcircuit 6901 is also connected to the input lead 6603 on the multiplier circuit 6601, but to the pair of multiplicand x, y bits, according to their bit positions. This input allows each multiplier subcircuit 6901 to output a pair of individual bits at corresponding bit positions in the x, y substring of the partial product.

[0507] Figure 64 The block diagram of the multiplier circuit 6901 is shown. Figure 65 The internal logic circuit is shown, which is based on Figure 63 The truth table and the following formulas are executed, involving the multiplicand. With multiplier Multiplying the x and y bits in pairs.

[0508] Expressed mathematically, the multiplicand of a generalized binary number with generalized binary number multiplier The method of multiplication includes the following steps:

[0509] Multiplier substring , Where i = 0, 1, 2..., according to the multiplier Each pair of substrings , Expand, where j = 0, 1, 2, ..., to obtain the partial product. , , ;in

[0510]

[0511] For i = 0, 1, 2… and j = 0, 1, 2…; where

[0512] , for The position pair;

[0513] , for The position pairs, and so on.

[0514] Subsequently, each pair of partial products is fed into the processing subcircuit 6705 for processing, and then fed into the adder subcircuit 6707 to perform parallel addition operations on each bit position. The sum output by the adder subcircuit 6707 is a new partial product, which is also a generalized number.

[0515] In turn, every two new partial products are fed into another processing subcircuit 6705 and adder subcircuit 6707 until the final product of the multiplications is obtained. Each round of addition using processing subcircuit 6705 and adder subcircuit 6707 represents one iteration. Therefore, Figure 67 The processing sub-circuit 6705 and the adder sub-circuit provide two iterations.

[0516] The processing sub-circuit 6705 and adder sub-circuit 6707 in each iteration have the following features: Figure 25 The aggregate logic circuit shown includes sub-circuits A42XY11, 2CV-21, A4-XY12, and A4-2XY13 for transformation A, simplification transformation, transformation B, and addition. These sub-circuits have been combined in the preceding paragraphs. Figures 13 to 21 Discussions have been held.

[0517] A second embodiment of the multiplier circuit (semi-optimization method)

[0518] Before describing the second embodiment of the multiplier circuit, we will introduce a different preprocessing method for generalized numbers to be added without introducing carry propagation. This type of preprocessing is called optimization, and the adder used to perform addition on optimized generalized numbers is referred to below as the optimized adder. Optimization can be further divided into semi-optimization and full optimization, but only semi-optimization will be described below.

[0519] It should be noted beforehand that regardless of the type of adder used in different multiplier circuit embodiments, the logic circuits used for operations not directly related to the preprocessing or addition of generalized numbers can be applied equally to all embodiments. For example, pre-addition operations that generalize a regular binary string into a generalized number format, or post-addition operations that convert a generalized number back into a regular binary string, can be used in all multiplier circuit embodiments. Therefore, there is no need to describe these circuits and their operations again.

[0520] Semi-optimized generalized binary strings It has the following characteristics:

[0521] 1. In each substring, there must be at least one zero space between any two non-zero bits;

[0522] 2. If two non-zero bits are located in two different substrings, then they can be directly adjacent;

[0523] 3. Two substrings cannot have non-zero positions at the same position at the same time, because this would cause corresponding positions in the two substrings to cancel each other out and become zero;

[0524] 4. There is no limit to the number of zeros.

[0525] The following are generalized numbers with a semi-optimal arrangement of non-zero values.

[0526]

[0527] Semi-optimization can be described by (2n-n), where n is the complete generalized number that contains both x and y substrings.

[0528] The generalized number shown on the left below contains the substrings x=3 and y=0, representing a total value of 3. However, this generalized number has not undergone semi-optimization. This is because the first and second positions of the x substring contain two consecutive non-zero values. Semi-optimization of this generalized number generates the generalized number shown on the right, where the x and y substrings represent 4–1=3, which can be written in the recommended abbreviation 0000010. The total value remains unchanged, which conforms to the principle of equivalence. Recalling the previous text, the 1 in the y substring can also be interchangeably written as -1 in other parts of this specification.

[0529]

[0530] The substrings x and y on the left below represent 7-0, indicating a total value of 7. Therefore, the generalized number n was not semi-optimized because of the three consecutive non-zero values ​​in the x substring. The semi-optimized substrings x and y on the right represent 8–1, abbreviated as 0000100. .

[0531]

[0532] The generalized number on the left below represents 15 - 0 = 15, and after semi-optimization, the generalized number on the right below is represented as 16 - 1 = 15, which can be written in abbreviated form as 0001000. .

[0533]

[0534] Reverse SEP

[0535] Before demonstrating how semi-optimization can be implemented in logic circuits, we will first introduce the concept of inverse SEP.

[0536] The reverse SEP (rSEP) reduces two directly adjacent non-zero bits located at positions i and i+1 in a pair of x and y substrings by replacing these four bits with a single non-zero bit located at the lower position of the adjacent non-zero bits, but in the opposite substring, as shown in box 39b. This is numerically equivalent to subtracting the value of the directly adjacent y substring from the value of the x substring bits, reducing the number of non-zero bits without changing the total value.

[0537]

[0538] The rSEP operation can be viewed as a combination of two sub-operations. In the sub-operation called rSEPx, if the higher-positioned of adjacent non-zero values ​​is in the x substring and the lower-positioned one is in the y substring, then the adjacent non-zero value is replaced with a non-zero value in the x substring that is located at the same bit position as the lower non-zero bit being replaced.

[0539] In the complementary suboperation called rSEPy, if the higher-positioned of two adjacent non-zero values ​​is in the y substring and the lower-positioned one is in the x substring, then the adjacent non-zero value is replaced with a non-zero value in the y substring at the same position as the lower-positioned non-zero value being replaced. In some scenarios, only one of rSEPx and rSEPy is used. In other scenarios, rSEP is used in a single step (i.e., both rSEPx and rSEPy are used).

[0540] rSEP should not be confused with the SEP transformation described in boxes 1 and 3. The following shows a generalized number representing 59-0 containing substrings x and y, which is semi-optimized by applying the SEP transformation (abbreviated as SEPx) only to the substring x.

[0541]

[0542] The truth table of rSEPx is as follows: Figure 15 As shown, its logic circuit is as follows Figure 14 As shown. The logic circuit of rSEPy is the same as the truth table except for the opposite sign, and does not need to be provided separately. The generalized numbers transformed above are then processed by rSEPx, as shown from left to right.

[0543]

[0544] Both rSEP and SEP transformations reduce the number of non-zero bits in generalized numbers, but they are implemented differently.

[0545] In a preferred embodiment, the logic circuitry for performing semi-optimization on generalized numbers may include performing the following three steps:

[0546] • Step 1: Apply SEP to the y substring of the generalized number instead of the x substring. The combined effect is similar to the example in Box 3, but it operates on the substring with the opposite sign. The result is that a series of adjacent non-zero bits in the y substring are replaced with zero bits, the non-zero bits at positions one order higher than the highest non-zero bit in the sequence, and the non-zero bits with the opposite sign at the same positions as the lowest non-zero bit in the sequence.

[0547] Step 2: Apply rSEPx to the output of Step 1.

[0548] Step 3: Apply SEP to the x substring output from Step 2.

[0549] Step 1 applies to the y substring only when the selection is arbitrary. Its reverse operation is also included within the scope of the embodiment: that is, step 1 applies SEP to the x substring, step 2 applies rSEPy, and step 3 applies SEP to the y substring output by step 2.

[0550] Figure 47 A sub-circuit is shown for half-optimizing an 8-bit generalized number to a 9-bit half-optimized generalized number. Figure 47 Includes such as Figure 48 The three sub-circuit modules shown are labeled Vin8o08-31, Vin8o08-32, and Vin8o08-33, respectively. Figure 47 The digital module circuit performs operations on the substring in parallel according to each bit position.

[0551] Details of VinSo08-31, such as Figure 49 As shown, it contains multiple Figure 50 The basic sub-circuit shown is used to perform step 1: according to the following formula and elimination Strings such as Figure 51 The truth table shown eliminates adjacent strings by applying the SEP transformation to the y substring. Any string.

[0552]

[0553] Details of VinSo08-32, such as Figure 52 As shown, it contains multiple Figure 53 The basic sub-circuit shown is used to perform step 2, according to the following formula and Figure 54 The truth table shown applies rSEPx to the output of step 1.

[0554]

[0555] Details of VinSo08-33, such as Figure 55 As shown, it contains multiple Figure 56 The basic sub-circuit shown is used to perform step 3: according to the following formula and as... Figure 57The truth table shown shows that by applying SEP transformation to the x substring output in step 2, all strings with adjacent 1s are eliminated.

[0556]

[0557]

[0558] in and A semi-optimized generalized binary string representing the addend.

[0559] Figure 58 This is a block diagram of a circuit module for a "semi-optimized" adder that can process two 9-bit semi-optimized generalized binary substrings. , , , Perform the summation. The output is a 10-digit generalized number. Figure 59 It shows Figure 58 The circuit module contains ten sub-circuits, each of which is... Figure 60 The adder shown. Figure 59 The sub-circuits in the circuit operate in parallel and simultaneously, responding only to their respective inputs. Figure 61 For the logic circuit of an adder unit, two such adder units are combined to provide Figure 60 The adder shown outputs a result in a generalized number format.

[0560] For each bit position i, the addition algorithm considers the substring for positive values. and The algorithm takes the adjacent bits at position i and i-1 to generate the output bit X at position i. Similarly, for each bit position i, the addition algorithm considers the substring for the numerical value. and The adjacent bits at position i and i-1 are used to generate the output bit Y at position i. The addition algorithm in each adder is independent of other adders and only calculates the output at the corresponding bit position.

[0561] The semi-optimization ensures that one of every two bits is zero, i.e., interleaved zeros, which can receive any carry without propagating the carry forward. The output string, formed by concatenating bits X and Y, represents the sum in generalized number format.

[0562] The addition algorithm can be described in the following two steps, where the sum is denoted as... The semi-optimized addend and augend are denoted as follows: and .

[0563] (a) Add the positive and negative components separately by applying the following formula;

[0564]

[0565] Its logical truth value and logic circuit are as follows: Figure 62 Table 12 and Figure 61 As shown.

[0566] The following is an example of a 13×13×13 operation in a multiplier circuit implemented using a semi-optimized adder. The method for obtaining the partial product is the same as described in box 30a and need not be repeated. This multiplier circuit applies a semi-optimized transformation to each partial product through the above three steps.

[0567] The left side of box 40 shows the partial product obtained in box 30a, which is the data on the right after performing semi-optimization on the y substring. Incidentally, since the y substring has no non-zero bits, the output remains unchanged.

[0568]

[0569] Then, rSEPx is applied to the data on the right side of box 40. Incidentally, since the y substring contains no non-zero bits, rSEPx does not change the output. It appears as if it is completely identical to the data on the right side of box 40.

[0570]

[0571] Subsequently, SEP is applied to the x-substring of the data on the right side of box 40 to generate the data on the left side of box 41. If both the x-substring and y-substring in the result contain non-zero bits at the same positions, the SEP logic circuit automatically cancels them out to zero during a simplification-like operation. Next, the partially optimized products are added pairwise, with x-substrings added to x-substrings and y-substrings added to y-substrings, and the results are simplified before being output. This semi-optimized adder follows... Figure 62 The logic in Table 12 and Figure 60 and Figure 61 The circuit structure is as follows. Therefore, the output has half the number of partial products, as shown on the right side of box 41. This completes one iteration of adding pairwise partial products. To obtain the final sum, further iterations are required: first, perform semi-optimization on the y-substring of the data on the right side of box 41 to obtain the output on the left side of box 42, and the result has been simplified before output.

[0572]

[0573] The right side of box 42 shows the result of processing the data on the left side of box 42 with rSEPx. Subsequently, SEP is applied to the x substring on the right side of box 42 to obtain the data on the left side of box 43.

[0574]

[0575] Add the substrings x and y separately to obtain the data on the right side of box 43, which is the multiplication product. This completes the second iteration. This product is now used as the multiplicand for the next multiplication, in which case there is no need to convert the product back to regular binary format. The multiplier is still the number 13, and its partial product with the multiplicand is shown in box 44.

[0576]

[0577] The product of each part is summed and displayed on the left side of box 45. After performing semi-optimization on the y substring and then simplifying, the data on the right side of box 45 is obtained.

[0578]

[0579] Applying rSEPx to the data on the right side of box 45 yields the data on the left side of box 46. Incidentally, since the y substring contains no non-zero bits, it remains unchanged. Subsequently, semi-optimization and simplification are performed on the x substring to obtain the data on the right side of box 46.

[0580]

[0581] Add the substrings x and y separately to get the data on the left side of box 47.

[0582]

[0583] However, to obtain the final sum, further iterations are needed: First, perform semi-optimization on the y substring to the left of box 47, and simplify the result before output to obtain the data shown on the right of box 47.

[0584] Next, rSEPx is applied to the data on the right side of box 47. Incidentally, only one position needs transformation, located in the lower x, y substring pair. The transformation result is shown on the left side of box 48.

[0585]

[0586] Perform semi-optimization on the data to the left of box 48 using the x substring, and then simplify it to obtain the data to the right.

[0587]

[0588] After adding the data on the right side of box 48, the second iteration ends, resulting in the product in box 49.

[0589] This product can be used for any subsequent data processing. However, if obtaining this product is the end point of a series of processes, the inverse conversion steps discussed in the previous sections of the adder examples are used to convert the product from generalized number format to regular binary format.

[0590] The multiplier circuit in this embodiment and Figure 66 The structures shown are the same. For example... Figure 67 , Figure 68 and Figure 69 The arrangement and schematic sub-circuits shown are applicable to both the first embodiment and this embodiment. There is no need to repeat the same description of the expanded circuit and expanded sub-circuits.

[0591] The main difference between the multiplier circuits in the first and second embodiments lies in the internal structure of the processing sub-circuit 6705 and the adder sub-circuit 6707. However, from the outside, the arrangement of the processing sub-circuit 6705 and the adder sub-circuit 6707, as well as their connection to the same expanded circuit 6701 and the output leads, are all different from those in the second embodiment. Figure 67 Consistent with the above.

[0592] Unlike the first multiplier circuit embodiment, each processing sub-circuit 6705 includes two Figure 48 The sub-circuit shown is (sub-circuit VinSo08-3). Figure 48 Each sub-circuit shown is used to perform semi-optimization on an 8-bit generalized number. Thus, two generalized numbers are fed into each processing sub-circuit 6705, which outputs two semi-optimized generalized numbers to the adder sub-circuit 6707.

[0593] The structure of adder sub-circuit 6707 and Figure 58 The adder shown, VinSoXY33, cannot be a simple AND gate like in the first embodiment. This is because there may be carry-overs from non-zero positions at the same bit location in two substrings of the same symbol. Since there is at least a zero bit between the non-zero bits in the two substrings of the same symbol, the carry-over does not propagate; and each adder must consider adjacent bits to determine the output value at the relevant bit location. The two partial products, after being added by the adder, are reduced to a single partial product. For completeness, it should be noted that transform B in the first multiplier circuit embodiment has already processed all carry-overs before the adder, which allows the adder for generalized numbers processed by the AB method to be simply an AND gate.

[0594] For the two iterations, two sets of processing sub-circuits and adder sub-circuits 6707 are set up, consistent with the first embodiment.

[0595] The third embodiment of the multiplier circuit (semi-optimization method)

[0596] In the third embodiment, the multiplier is a generalized number, and semi-optimization is performed before expanding it into a partial product with the multiplicand. This reduces the total number of partial products. Generalization can be achieved through the same three steps: SEPy, rSEPx, and SEPx, which "spread" all adjacent non-zero bits in the same substring.

[0597] Now, apply rSEP (using both rSEPx and rSEPy) to the two adjacent bits (a total of 4 bits) of each next block of the two substrings. The resulting multiplier will generate at least 3 zero bits in the 4 bits at the two positions. There will be four zero bits, or three zero bits plus one non-zero bit. This makes it easy to copy the multiplicand during the expansion process. If there are no non-zero bits in the four bits, each partial product is all zero; if there is one non-zero bit, each partial product is the same as the multiplicand but shifted; if the non-zero bit is in the y substring, the partial product is the same as the multiplicand, with the sign swapped and the position shifted.

[0598] Therefore, by multiplying the x and y bits of the multiplicand by the adjacent two bits of each consecutive block of the multiplier, the multiplicand and the processed multiplier are expanded, and the output is shifted accordingly. The number of partial products can be half the number obtained by expanding the multiplicand by each bit position of the multiplier. Thus, in the previous example, the 4-bit multiplier is expanded into two partial products instead of four. This reduces the complexity of the multiplier circuitry by halving the number of partial products.

[0599] Before the partial products are added using a symmetrical adder, the steps and logic circuits described above are still required to perform semi-optimization or AB transformation. Therefore, when the multiplier is a four-digit generalized number, the final sum can be obtained in just one iteration.

[0600] Expressed mathematically, these two semi-optimized binary numbers and The multiplication method includes the following steps:

[0601] (a) Provide two generalized numbers for the multiplicand and multiplier, respectively. and .

[0602] (b) Using the three steps described above, for and Perform semi-optimization to generate a semi-optimized multiplicand. With semi-optimized multipliers .

[0603] (c) Simultaneously apply rSEPx and rSEPy to reduce the semi-optimized multiplier by using consecutive two bits in blocks. .

[0604]

[0605] Where i = 0, 2, 4, ..., such that There is at most one non-zero digit in the multiplier, and the reduced multiplier... The resulting string and It should be emphasized that the reduced multiplier... It is no longer a semi-optimized binary number.

[0606] The truth table for the rSEP transformation (applying both rSEPx and rSEPy) is as follows: Figure 70 As shown, the relevant circuit module block diagram is as follows: Figure 71 As shown, the underlying logic circuit is as follows Figure 72 As shown.

[0607] (d) Determine every two consecutive digit pairs of the positive and negative strings of the reduced multiplier. and The partial product, where i = 0, 2, 4..., is obtained to obtain the partial product. , , ...;

[0608] Multiplier 10 1. Applying rSEP yields a reduced multiplier of 100. Here are some examples:

[0609]

[0610] An example of expanding the multiplicand by every 2 bits of the multiplier is shown in box 50.

[0611]

[0612] (e) The partial product is then summed using the semi-optimized adder subcircuit described above, with no carry propagation; or the summation is performed using the AB method with a symmetrical adder, also with no carry propagation.

[0613] use Figure 66 The adder sub-circuit 6707 and the processing sub-circuit 6705 perform semi-optimization and addition on the two partial products.

[0614] The fourth embodiment of the multiplier circuit (semi-optimization method)

[0615] In the fourth embodiment, only one of the multiplicand and multiplier is a generalized number, and the other is a regular single binary string. The partial product generated by multiplying the generalized number and the regular binary string is still a generalized number, which can be accumulated using any of the aforementioned pre-processing addition methods.

[0616] Take -3 × 3 = -9 as an example. A generalized binary format of -3 includes the substrings x = 0010 and y = 0101, corresponding to 2-5. The regular binary format of the multiplier m is 0011, which is 3 in decimal. The partial product obtained by expanding the multiplicand and multiplier is shown in box 51.

[0617]

[0618] Box 52 shows the expansion of the x, y bit pairs used in Box 51 with individual bits. Not all instances of m=0 are listed, as the output x and y bits of such instances are both zero; nor are all instances of input x and y bits being non-zero, as such instances cancel each other out to zero.

[0619]

[0620] The output values ​​at each bit position are concatenated to obtain the corresponding partial products on the left side of box 53. The four partial products contain a total of eight substrings. The final sum of the substrings x and y will have a product equal to 3 × -3 = -9, represented as x' = 0000 and y' = 1001. The processing of each pair of partial products and subsequent addition can be implemented using any of the methods described. The product output is a generalized number, which can be multiplied again by a binary number in normal format in the next multiplication.

[0621]

[0622] Used for 8-bit generalized binary numbers (Multiplicand) and 4-bit classic single binary number The M84 multiplication circuit, which multiplies (multipliers), has the following circuit modules: Figure 76 As shown; corresponding Figure 77 It shows Figure 76 The sub-circuits of each major step in the multiplier circuit. Except for the expanded circuit 7701 and its internal expanded sub-circuits, the structure of this multiplier circuit is similar to... Figure 66 , Figure 67 , Figure 68 , Figure 69 Consistent with the above.

[0623] The expansion circuit 7701 requires only a number of multiplier input leads equal to the length of the multiplier string, as shown on the far right. The expansion circuit 7701 distributes the input data to four expansion sub-circuits 7701a, as follows: Figure 78 As shown. Each expansion sub-circuit 7701a receives the complete multiplicand, but only receives one multiplier bit 7803, and outputs a pair of x, y bits at 7801, which is the product of the multiplicand x and y bits at the same bit position and the multiplier bit. Each output also performs a position shift, so that the shifted positions are all assigned zeros. In this way, each of the four expansion sub-circuits 7701a outputs a partial product, but performs a position shift according to the bit order of the relevant multiplier bit.

[0624] Figure 79 The internal details of the expanded sub-circuit 7701a are shown, which contains eight multiplication sub-circuit units MZX for processing single bit and single x, y bit inputs 7901. Figure 74 This is a circuit block diagram of one such unit 7901. Figure 75The internal logic circuit of the unit is shown, which is based on... Figure 73 Run the truth table and the following formulas.

[0625] Expressed mathematically, this generalized binary number As the multiplicand, and a single classical binary number As a method of multiplying factors, the steps include:

[0626] (a) The multiplier substring , Where i = 0, 1, 2..., according to the multiplier Each bit Expand, where j = 0, 1, 2, ..., to obtain the partial product. , , ...where i = 0, 1, 2... and j = 0, 1, 2...; where

[0627]

[0628] in for The position pair; , for The above expansion follows the same principle. Figure 73 The truth table is composed of Figure 74 The module circuit shown is implemented. Figure 75 It shows Figure 74 Sub-circuits in the circuit.

[0629] (b) For partial product , , ...perform summation to obtain the final product. This step is consistent with other embodiments.

[0630] The fifth embodiment of the multiplier circuit (semi-optimization method)

[0631] Only the partial product needs to be in generalized number format so that it can be processed through transformation and achieve carry-free addition. In less efficient embodiments, the partial product, multiplicand, and multiplier can all be in conventional single binary string format.

[0632] Generalization and generalized number preprocessing are performed only on any two partial products to be added. Alternatively, the sum can be immediately converted back to its normal format, and the generalization and preprocessing can be re-performed only when the next addition with another partial product or a new partial product is required. Therefore, the two numbers to be multiplied can be provided by a prior art processor to an external multiplication circuit implementing this embodiment, which returns its product to the prior art processor in normal binary format.

[0633] Semi-optimal alternatives

[0634] The following example illustrates a semi-optimization of the number 7 using the formula (2n-n) introduced earlier. In practical applications, this is equivalent to applying SEP to both substrings x and y simultaneously, or applying SEP to one substring immediately following the other.

[0635]

[0636] However, the example below illustrates a situation where using only this formula cannot avoid adjacent non-zero bits in the output, thus making it impossible to semi-optimize the input.

[0637]

[0638] When a generalized number contains one of the following problematic non-zero arrangements, namely 10 or 01. The problem occurred:

[0639]

[0640] The three-step semi-optimized method described above handles these two arrangements by applying rSEPx between applying SEP to the y substring and applying SEP to the x substring, but not applying rSEPy at all. This asymmetric transformation generates staggered zeros, accommodating carry-overs from immediately lower positions, thus eliminating the need to propagate carry-overs to immediately higher positions. However, other methods exist for handling these two problematic non-zero arrangements.

[0641] A first alternative to performing semi-optimization on generalized numbers includes the following steps:

[0642] (a) Apply the following formula to generalized numbers Perform the transformation:

[0643]

[0644] The corresponding truth table is as follows Figure 80 As shown; the transformation is: subtracting the substring from its copy after shifting it one effective bit to the left. The logic of formula (30) can be expressed by the following logical formula:

[0645]

[0646] Where the assumption .

[0647] But if you input Contains 10 and Any problem arrangement in 01 will have an output. The risk of not being able to achieve semi-optimization.

[0648] (b) Subsequently according to Figure 81 The truth table 6c and below formulas in the text are eliminated beforehand. All adjacent non-zero bits 11 or Provide semi-optimized numbers Certainty, or in short :

[0649]

[0650] Assumption Then formulas (31a) and (31b) and formulas (32a) and (32b) can be combined as follows:

[0651]

[0652] in The positive and negative bits can be semi-optimized in parallel operations.

[0653] Semi-optimized output and Only depends on of , , and . Figure 82 The truth table after combining steps a) and b) is shown, i.e., formulas (33a) and (33b). The corresponding logic circuit is as follows. Figure 83 and Figure 84 As shown.

[0654] A second alternative to semi-optimization for generalized numbers:

[0655] (a) According to formulas (34a) and (34b) Figure 87 The truth table in and Figure 85 and Figure 86 The logic circuits, respectively, convert any substring 10 and 01 converted to 1 1 and 1 :

[0656]

[0657] (b) Applying formula (30), the following formula can be derived, and the corresponding truth table is as follows: Figure 90 As shown, the logic circuit is as follows Figure 88 and Figure 89 As shown:

[0658]

[0659] Finally, a semi-optimized digit is obtained. and .

[0660] The difference between the first and second alternative methods lies in the reverse order of the application of the bit manipulation algorithm and the transformation of formula (30). In addition, the bit manipulation formulas (34a) and (34b) and (32a) and (32b) eliminate the different non-semi-optimized arrangements of non-zero bits between the two alternative methods.

[0661] Limtree: A Novel Multiplication Algorithm

[0662] In some embodiments, partial products can be processed in a Wallace tree-like manner; that is, instead of conventionally using carry-preserving adders to iteratively add specific rows of classic single binary two's complement numbers into the cumulative sum, this circuit is designed to simultaneously add every two partial products in any iteration, each partial product comprising a pair of generalized binary numbers. Note that the term "partial product" also includes the sum of any two or more partial products—provided that at least one further iteration is performed during the generation of the multiplicative product.

[0663] The multiplier circuit is designed with the required number of iterations to perform the summation of all partial products using the 4-2 general-purpose adder described in the circuit; this is similar in principle to Wallace trees but has differences. The circuit employs a novel logic algorithm called a Lim tree. Compared to Wallace trees, using a Lim tree eliminates a significant number of logical operations and substantially reduces propagation delay.

[0664] definition Here, Mod(n, m) is the integer division function, and Mod(n, m) is the modulo function with respect to the independent variables n and m. Let be the initial number of bit strings, then the number of bit strings at level i of the Lim tree is... It is given by the following formula:

[0665]

[0666] in And requires A 4-2 general-purpose adder; and in the Wallace tree, the number of bit strings at the i-th level is:

[0667]

[0668] in And requires A 3-2 adder.

[0669] Both LIM trees and Wallace trees require a carry-lookahead adder or other arbitrary serial adder to convert a pair of x, y substrings (or a pair of two's complement numbers in the case of a Wallace tree) into a classic single binary string representing the sum of partial products. However, LIM trees have significant advantages over Wallace trees in the following aspects:

[0670] The gate-level computation of the single-stage 4-2 adder used in the Lim tree is far less than that of the two-stage 3-2 adder (full adder) used in the Wallace tree.

[0671] • Due to the significant reduction in gate levels and iteration count, propagation delay is significantly improved;

[0672] • The Limtree logic algorithm has a much higher degree of structure at the logical operation level.

[0673] For the multiplication of two regular single-string 64-bit binary strings (not generalized numbers each containing a pair of x and y substrings), applying formula (36a) to a Lim tree yields:

[0674]

[0675] This requires five levels of 4-2 logic operations plus one level of carry-lookahead adder.

[0676] Please note that the product is the sum of 64 individual binary strings of partial products, which are expanded by shifting and multiplying the 64-bit multiplicands by the weights of each bit in the 64-bit multiplier. This result can be converted into 32 pairs of 64-bit x, y substrings, each pair being a 64-bit generalized number. Therefore... For the final level This yields a generalized number consisting of a pair of substrings x and y. On the other hand, applying formula (36b) to the multiplication of two 64-bit classical binary numbers using a Wallace tree yields:

[0677]

[0678] This requires ten levels of 3-2 logic operations plus one level of carry-lookahead adder.

[0679] The following is an example of multiplying two generalized binary numbers using a Lim tree. The 8-bit × 8 multiplication algorithm is explained below: Figure 91Table (a) shows the standard Lim tree, and Table (b) shows the inverted Lim tree. The inverted Lim tree is simply a graphical rearrangement of partial products in a pyramid format. This rearrangement allows circuit designers to easily track design progress by marking the positions of the bits with the most rows in the partial products. If the string length is short, inversion is unnecessary.

[0680] All methods disclosed in this document can be implemented using logic circuits. The logic circuits described in this document (which may be understood herein as "fixed logic circuits") can be part of a larger-scale logic circuit. This larger-scale logic circuit can be configured to perform computational tasks on a set of input data to generate a corresponding set of output data. The elements of the logic circuit (e.g., gate circuits) can be implemented as corresponding regions of one or more integrated circuits, or as corresponding physical devices.

[0681] For example, the input data can be image data. The corresponding computational task can be one or more of the following: image processing, image classification, object classification, pose estimation, scene recognition, image segmentation, object localization or detection, depth estimation, image keypoint detection, image similarity determination, or image data encoding.

[0682] For example, the input data could be video data consisting of a sequence of multiple images. The corresponding computational task could be one or more of the following: video processing, action recognition, action detection, or video data encoding.

[0683] For example, the input data can be audio data. The corresponding computational task can be one or more of the following: audio processing, speech recognition, speaker recognition, scoring tasks, tasks to recognize or translate any spoken language in the audio data, or audio data encoding.

[0684] For example, the input data can be sensor data, i.e., data representing the environmental state, and may include one or more of the following: video data, image data, temperature data, pressure data, distance data, or location data. The corresponding computational task can be generating data corresponding to the action to be performed by the intelligent agent. The intelligent agent can be, for example: a mechanical intelligent agent that moves and interacts with the real environment; a system for controlling networked system settings; or a system for controlling industrial facilities.

[0685] Although preferred embodiments of the invention have been described in the foregoing description, those skilled in the art will understand that many variations or modifications may be made in the details of design, construction or operation without departing from the scope of the invention as defined by the appended claims.

Claims

1. A method implemented using fixed logic circuits for replacing non-zero bits at multiple bit positions in two of four binary strings, the four binary strings being included in two generalized numbers to be added; The replacement includes the following steps: Replace one or more non-zero bits at the bit position containing that bit position with: The zero bit at this position, and one or more non-zero bits at other bit positions in two of the four binary strings, represent the same value.

2. A method for multiplying a multiplicand and a multiplier, comprising the following steps: 2a) Expand the multiplicand and multiplier to obtain the partial product in generalized form; 2b) Perform multiple addition operations to accumulate the partial products and generate a multiplicative product; in The steps described in claim 1 are performed before each addition operation.

3. The method for multiplying a multiplicand and a multiplier according to claim 2, wherein... The multiplicand in step 2a) is a generalized number represented by two binary strings, and the multiplier is a number represented by at least one binary string.

4. The method for multiplying a multiplicand and a multiplier according to claim 3, wherein the multiplier in step 2a) is a generalized number.

5. The method for multiplying a multiplicand and a multiplier according to claim 4, comprising the following steps prior to step 2a): The non-zero bits in a four-bit block that includes two bits at the same adjacent position in each binary string and represents a value are replaced with a four-bit block at the same position that has at least three zero bits and one non-zero bit and represents the same value as the four-bit block.

6. The method for multiplying a multiplicand and a multiplier according to claim 5, wherein step 2a) comprises: The multiplicand is expanded for each consecutive block of the multiplier.

7. The method for multiplying the multiplicand and multiplier according to claim 3, The multiplicand is a substring and generalized numbers ;and The multiplier provides numbers. at least one binary string ; Step 2a) includes the following steps: 7a) According to the following truth table, by the multiplier Each bit in For the multiplicand Perform the expansion to obtain a partial product. , , ……, ,in in and , , for The position pair; , for The position pairs, and so on; 7b) Each iteration includes a partial product of at least two parts. , , Perform preprocessing and addition, repeating the process iteratively until all partial accumulations are added together to form the final product. ; in The preprocessing includes the following steps: 7c) Position The non-zero bit at that position is replaced with a zero bit, and the non-zero bit at that position represents the numerical value; and At least one non-zero bit is provided at different bit positions in the same or other partial product of the at least two partial products; such that The bit position It can store the carry during the addition process.

8. The method for multiplying the multiplicand and multiplier according to claim 4, The multiplier includes generalized numbers. Another binary string ;in Step 2a) includes: According to the following truth table, by the multiplier Each pair , For the multiplicand Perform the expansion to obtain a partial product. , , ……;in , in and , , for The position pair; , for The position pairs, and so on.

9. The method for multiplying a multiplicand and a multiplier according to claim 7, wherein... Step 7c) includes the following steps: Transformation A According to the truth table, by and Generate the third pair of substrings and , and by and Generate the fourth pair of substrings and Where i is the bit position: Simplification and Transformation For each bit position By =1 and Non-zero values ​​of 1 are replaced with zero bits, by and Generate substring and ; as well as For each bit position By =1 and The non-zero value of =1 is replaced with and The zero position in the middle is... and Generate substring and ; Transformation B According to the truth table, for , The values ​​are combined to generate a pair of substrings. and and further , The values ​​are combined to generate a pair of substrings. and : Summation operation Perform addition based on the truth table to generate the sum of two substrings X and Y: i. will and Add them together to generate a single binary string that is the sum of the two numbers.

10. The method for multiplying a multiplicand and a multiplier according to claim 7, wherein... Step 7c) includes the following steps: The zero and non-zero bits in the binary substring are rearranged, including the following steps 10-1), 10-2), and 10-3) performed in a specific order: Step 1) Apply the following formula to eliminate binary substrings. Any directly adjacent non-zero bits in the middle: as well as Step 2) Apply the following formula to eliminate binary substrings. and Any consecutive non-zero pairs arranged in the following specific order, i.e., changing x=1, y=0 followed by x=0, y=1 to x=0, y=0 followed by x=1, y=0: Step 3) Apply the following formula to eliminate binary substrings. Any directly adjacent non-zero bits in the middle: Or simplified to (5b) in and Represents formatted binary substring pairs and Middle position The value of the digit at the location; and The positive and negative components are added together using the following formula: 。 11. The method for multiplying a multiplicand and a multiplier according to claim 7, comprising the following steps prior to step 7a): The multiplier is processed as follows: : i) Apply the following formula to eliminate binary substrings. Any directly adjacent non-zero bits in the middle: as well as Similar to formulas (3a) and (3b) above; ii) Apply the following formula to eliminate binary substrings and Any consecutive non-zero pairs arranged in the following specific order, i.e., changing x=1, y=0 followed by x=0, y=1 to x=0, y=0 followed by x=1, y=0: Similar to formulas (4a) and (4b) above; iii) Apply the following formula to eliminate binary substrings Any directly adjacent non-zero bits in the middle: Or simplified to Similar to formulas (5a) and (5b) above, where and Represents formatted binary substring pairs and Middle position The numerical value of the digit at the location; iv) Optimize the multiplier by splitting consecutive two-digit blocks according to the following formula. Execution reduction: in …, making , , , There is at most one non-zero digit in the multiplier, and the reduced multiplier... The resulting substring and express; v) Determine Each pair of consecutive digits of the positive and negative strings of the reduced multiplier and The partial product, to obtain the partial product , , ……,in …;and This makes step (a) become: According to the following truth table, by the multiplier Each pair , For the multiplicand Perform the expansion to obtain a partial product. , ,……;in …, in, and , , for The position pair; , for The position pairs, and so on.

12. A unit multiplier provided as a fixed logic circuit, for expanding the circuit, for obtaining a partial product between a generalized number and a binary string according to step 2a) of claim 3, comprising: 。 13. A unit multiplier provided as a fixed logic circuit, for expanding the circuit, for obtaining a partial product between two generalized numbers according to step 2a) of claim 4, comprising: 。 14. A unit multiplier provided as a fixed logic circuit, for expanding the circuit, for obtaining a partial product between two generalized numbers according to step 2a) of claim 6, comprising: 。 15. An apparatus comprising a fixed logic circuit configured to perform the method of any one of claims 1-11.

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