Light emitting diode chip

Abstract

The utility model provides a light-emitting diode chip, which comprises a substrate, a first light-emitting unit and a second light-emitting unit, the first light-emitting unit comprises an epitaxial laminated layer, a transparent conducting layer and a passivation layer, the epitaxial laminated layer is provided with a step structure which comprises a first step surface and a second step surface, the first step surface is provided with the transparent conducting layer, and the second step surface is provided with the passivation layer. The area of the second step surface does not exceed 15% of the effective light-emitting area of the first light-emitting unit; a first conductive electrode and an insulating layer are arranged on the second step surface, the first conductive electrode penetrates through the insulating layer to be in contact with the second step surface, and the insulating layer covers part of the surface of the transparent conductive layer and part of the first step surface. According to the utility model, the ratio of the effective light-emitting area of the second step surface to the effective light-emitting area of the first light-emitting unit is reduced, and the insulating layer is arranged on the second step surface, so that the aim of reducing the probability of ESD explosion points of the first light-emitting unit is fulfilled.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor devices, in particular to a light emitting diode chip. Background Art

[0002] Light-emitting diodes have the advantages of low cost, high luminous efficiency, energy saving and environmental protection, and are widely used in lighting, visible light communication, and luminous display scenarios.

[0003] Conventional light-emitting diode chips are usually divided into multiple light-emitting units in a horizontal and vertical manner. An N-type pad is usually provided on one of the light-emitting units on the outside of the chip. However, the existing packaging wire bonding technology leads to a lower limit on the size of the pad. When the size of the entire chip is smaller, the number of light-emitting units is greater, and the pad size remains unchanged, the light-emitting unit where the N-type pad is located will have a small effective carrier recombination area due to the large proportion of the N-type pad area, which in turn causes the light-emitting unit where the N-type pad is located to be prone to ESD explosion points. Utility Model Content

[0004] Based on this, the purpose of the utility model is to provide a light-emitting diode chip, aiming to solve the problem in the prior art that the light-emitting unit where the N-type pad is located is prone to ESD explosion points due to the large area of ​​the N-type pad, which makes the effective carrier recombination area of ​​the unit small.

[0005] The utility model aims to provide a light-emitting diode chip, comprising a substrate, a first light-emitting unit and a second light-emitting unit respectively arranged on the substrate, the first light-emitting unit and the second light-emitting unit being electrically connected, the first light-emitting unit comprising an epitaxial stack, a transparent conductive layer and a passivation layer, a step structure being arranged on the epitaxial stack, the step structure comprising a first step surface and a second step surface, the transparent conductive layer being arranged on the first step surface, and the area of ​​the second step surface not exceeding 15% of the effective light-emitting area of ​​the first light-emitting unit;

[0006] A first conductive electrode and an insulating layer are provided on the second step surface, the first conductive electrode penetrates the insulating layer and contacts the second step surface, and the insulating layer covers a portion of the surface of the transparent conductive layer and a portion of the first step surface;

[0007] The passivation layer covers a portion of the surface of the transparent conductive layer, a portion of the surface of the insulating layer, and a portion of the surface of the first conductive electrode.

[0008] Compared with the prior art, the beneficial effect of the light-emitting diode chip of the present invention is that by reducing the ratio of the second step surface in the first light-emitting unit to the effective light-emitting area of ​​the first light-emitting unit and providing an insulating layer on the second step surface, the effective carrier recombination area in the first light-emitting unit is increased, thereby reducing the probability of explosion points in the first light-emitting unit, improving the ESD capability of the light-emitting diode chip, and improving the reliability of the chip.

[0009] Optionally, the transparent conductive layer is disposed on a side of the first step surface away from the second step surface, and the surface of the transparent conductive layer at an end close to the second step surface is covered with the insulating layer.

[0010] Optionally, the insulating layer includes one or more combinations of SiNx, Al2O3, and TiOX, and the thickness of the insulating layer is

[0011] Optionally, the epitaxial stack includes a second semiconductor layer, an active layer and a first semiconductor layer stacked in sequence, the second semiconductor layer is provided with the second step surface on a portion of its surface on the side away from the substrate, the second semiconductor layer is provided with the active layer and the first semiconductor layer stacked in sequence on another portion of its surface on the side away from the substrate, and the first semiconductor layer is provided with the first step surface on a surface on the side away from the substrate.

[0012] Optionally, the first semiconductor layer is a P-type semiconductor layer, the second semiconductor layer is an N-type semiconductor layer, the second semiconductor layer is connected to the substrate, or a buffer layer is sandwiched between the second semiconductor layer and the substrate.

[0013] Optionally, the first conductive electrode is an N-type electrode, and the first conductive electrode penetrates the insulating layer and is electrically connected to the second semiconductor layer.

[0014] Optionally, the transparent conductive layer includes any one of ITO and IZO, and the thickness of the transparent conductive layer is

[0015] Optionally, the passivation layer comprises one or more combinations of SiO2, Al2O3, and TiOX, and the thickness of the passivation layer is

[0016] Optionally, a second conductive electrode is disposed on the second light-emitting unit, the second conductive electrode is a P-type electrode, and the second conductive electrode is electrically connected to the second light-emitting unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A top view of the light emitting diode chip of the present invention;

[0018] Figure 2 It is a schematic cross-sectional view of the structure of the first light-emitting unit 1 in the light-emitting diode chip of the present invention.

[0019] Among them, the above-mentioned drawings include the following figure marks: 1-first light-emitting unit; 2-second light-emitting unit; 10-substrate; 20-epitaxial stack; 21-second semiconductor layer; 22-active layer; 23-first semiconductor layer; 201-first step surface; 202-second step surface; 30-transparent conductive layer; 40-insulating layer; 50-passivation layer; 61-first conductive electrode; 62-second conductive electrode; 70-isolation groove; 80-electrode interconnection line.

[0020] The following specific implementation manner will further illustrate the present utility model in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0021] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Several embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0022] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the technical field of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0024] Please refer to the attached Figure 1 and 2 The light-emitting diode chip of the utility model is a positive structure, which includes a substrate 10, a first light-emitting unit 1 and a second light-emitting unit 2 arranged on the substrate 10, the first light-emitting unit 1 is electrically connected to the second light-emitting unit 2. In this embodiment, the first light-emitting unit 1 is electrically connected to the second light-emitting unit 2 through a plurality of LED light-emitting units, and an N-type pad (not shown) is provided on the first light-emitting unit 1.

[0025] Specifically, Figure 2 As shown, the figure is a schematic diagram of the structural cross-section of the first light-emitting unit 1, the first light-emitting unit 1 includes an epitaxial stack 20, a transparent conductive layer 30 and a passivation layer 40, and a step structure is provided on the epitaxial stack 20, the step structure includes a first step surface 201 and a second step surface 202 connected to the first step surface 201, wherein the area of ​​the second step surface 201 does not exceed 15% of the effective light-emitting area of ​​the first light-emitting unit 1. Compared with the light-emitting diode chip in the prior art, the area occupied by the second step surface 202 on the first light-emitting unit 1 is reduced to a certain extent, so that the area of ​​the effective carrier recombination region in the first light-emitting unit 1, namely the active layer 22, is increased, and the probability of ESD explosion point occurring in the first light-emitting unit 1 is reduced.

[0026] like Figure 2 As shown, the epitaxial stack 20 includes a second semiconductor layer 21, an active layer 22 and a first semiconductor layer 23 which are stacked in sequence. In the present embodiment, the second semiconductor layer 21 is an N-type semiconductor layer, the first semiconductor layer 23 is a P-type semiconductor layer, and a portion of the surface of the second semiconductor layer 21 on the side away from the substrate 10 is provided with the second step surface 202, and another portion of the surface of the second semiconductor layer 21 on the side away from the substrate 10 is stacked with the active layer 22 and the first semiconductor layer 23 in sequence. It should be noted that the second semiconductor layer 21 is connected to the substrate 10, or a buffer layer (not shown) is sandwiched between the second semiconductor layer 21 and the substrate 10.

[0027] Furthermore, a first step surface 201 is provided on a surface of the first semiconductor layer 23 on a side away from the substrate 10, and a side of the first step surface 201 away from the second step surface 202, that is, a part of the surface of the first semiconductor layer 23 on an end away from the second step surface 202 is covered with the transparent conductive layer 30, which is used to increase the lateral expansion capability of the current and form a good ohmic contact. The material of the transparent conductive layer 30 may include transparent conductive materials such as indium tin oxide (ITO) and indium zinc oxide (IZO), and its thickness is Preferably, the material of the transparent conductive layer 30 is indium tin oxide (ITO), which has good light transmittance, is the most widely used, and has low cost. It should be noted that a current blocking layer (not shown) can be further provided between the first semiconductor layer 23 and the transparent conductive layer 30. The current blocking layer is made of an insulating material and is used to prevent the current from being directly injected into the first semiconductor layer 23, i.e., the P-type semiconductor layer, which is beneficial to the uniform distribution of the current and improves the luminous brightness of the chip.

[0028] Furthermore, in order to avoid the occurrence of undesirable phenomena such as leakage caused by the reduction of the area of ​​the second step surface 202 in the first light-emitting unit 1, an insulating layer 40 is provided on the second step surface 201. Figure 2As shown, the insulating layer 40 sequentially covers part of the first step surface 201 and part of the surface of the transparent electrode layer 30 along the length direction of the substrate 10, and a conductive hole 401 is opened on the insulating layer 40 disposed on the second step surface 201. It should be further explained that in the specific implementation of this embodiment, the thickness of the insulating layer 40 is In order to better prevent leakage from occurring inside the LED chip, the insulating layer 40 may include SiN x 、Al2O3、TiO X A combination of one or more non-conductive materials.

[0029] A first conductive electrode 61 is provided on the first light-emitting unit 1. In the present embodiment, the first conductive electrode 61 is an N-type conductive electrode, and the first conductive electrode 61 contacts the second step surface 201 through a conductive hole 401 on the insulating layer 40. In other words, the first conductive electrode 61 penetrates the insulating layer 40 and contacts the surface of the second semiconductor layer 21 to achieve electrical connection between the first conductive electrode 61 and the second semiconductor layer 21.

[0030] At the same time, a passivation layer 50 is provided on the first light-emitting unit 1 to protect the light-emitting diode chip and prevent it from reverse leakage. In this embodiment, Figure 2 As shown, the passivation layer 50 covers the side of the epitaxial stack 20, the surface of the portion of the insulating layer 40 not covered by the first conductive electrode 61, the surface of the portion of the first conductive electrode 61, the surface of the portion of the transparent conductive layer 30 not covered by the insulating layer 40, and the portion of the first step surface 201. It should be further explained that the material of the passivation layer 40 may include SiO2, Al2O3, TiO X The thickness of the passivation layer 40 is

[0031] In a specific embodiment, Figure 1 As shown, the light emitting diode chip of the utility model includes 6 LED light emitting units, specifically including Figure 1 The first light emitting unit 1 on the upper left side of the middle chip is located Figure 1 The second light-emitting unit 2 on the lower right side of the middle chip and the four LED light-emitting units used to connect the first light-emitting unit 1 and the second light-emitting unit 2, the six light-emitting units are arranged in two rows and three columns, and the individual light-emitting units are isolated from each other by the isolation groove 70 on the substrate 10, and are connected in series through the electrode interconnection line 80 spanning the isolation groove 70, and the electrode interconnection line 80 can be made of ITO or metal.

[0032] Furthermore, a second conductive electrode 62 is disposed on the second light emitting unit 2 . In this embodiment, the second conductive electrode 62 is a P-type conductive electrode, and the P-type conductive electrode is electrically connected to the second light emitting unit 2 .

[0033] In summary, the light-emitting diode chip in the above-mentioned embodiments of the present invention increases the effective carrier recombination area of ​​the first light-emitting unit in the first light-emitting unit by reducing the ratio of the second step surface in the first light-emitting unit to the effective light-emitting area of ​​the first light-emitting unit, and arranging an insulating layer on the second step surface, thereby reducing the probability of ESD explosion point occurring in the first light-emitting unit, thereby improving the ESD capability of the light-emitting diode chip and improving the reliability of the chip.

[0034] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the utility model. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0035] The above-mentioned embodiments only express several implementation methods of the utility model, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent of the utility model. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the utility model, and these all belong to the protection scope of the utility model. Therefore, the protection scope of the utility model patent shall be based on the attached claims.

Claims

1. A light emitting diode chip, It is characterized in that The invention comprises a substrate, a first light-emitting unit and a second light-emitting unit respectively arranged on the substrate, the first light-emitting unit and the second light-emitting unit are electrically connected, the first light-emitting unit comprises an epitaxial stack, a transparent conductive layer and a passivation layer, a step structure is arranged on the epitaxial stack, the step structure comprises a first step surface and a second step surface, the transparent conductive layer is arranged on the first step surface, and the area of ​​the second step surface does not exceed 15% of the effective light-emitting area of ​​the first light-emitting unit; A first conductive electrode and an insulating layer are provided on the second step surface, the first conductive electrode penetrates the insulating layer and contacts the second step surface, and the insulating layer covers a portion of the surface of the transparent conductive layer and a portion of the first step surface; The passivation layer covers a portion of the surface of the transparent conductive layer, a portion of the surface of the insulating layer, a portion of the surface of the first conductive electrode, and a side surface of the epitaxial stack.

2. The light emitting diode chip according to claim 1, It is characterized in that The transparent conductive layer is disposed on a side of the first step surface away from the second step surface, and the surface of the transparent conductive layer at one end close to the second step surface is covered with the insulating layer.

3. The light emitting diode chip according to claim 1, It is characterized in that The insulating layer includes SiNx, Al 2 O 3 、TiO X One or more combinations thereof, wherein the thickness of the insulating layer is 4. The light emitting diode chip according to claim 1, It is characterized in that The epitaxial stack includes a second semiconductor layer, an active layer and a first semiconductor layer stacked in sequence, the second semiconductor layer is provided with the second step surface on a portion of the surface on the side away from the substrate, the second semiconductor layer is provided with the active layer and the first semiconductor layer stacked in sequence on another portion of the surface on the side away from the substrate, and the first semiconductor layer is provided with the first step surface on the surface on the side away from the substrate.

5. The light emitting diode chip according to claim 4, It is characterized in that The first semiconductor layer is a P-type semiconductor layer, the second semiconductor layer is an N-type semiconductor layer, the second semiconductor layer is connected to the substrate, or a buffer layer is sandwiched between the second semiconductor layer and the substrate.

6. The light emitting diode chip according to claim 4, It is characterized in that The first conductive electrode is an N-type electrode, and the first conductive electrode penetrates the insulating layer and is electrically connected to the second semiconductor layer.

7. The light emitting diode chip according to claim 1, It is characterized in that The transparent conductive layer includes any one of ITO and IZO, and the thickness of the transparent conductive layer is 8. The light emitting diode chip according to claim 1, It is characterized in that The passivation layer includes SiO 2 、Al 2 O 3 、TiO X One or more combinations thereof, wherein the thickness of the passivation layer is 9. The light emitting diode chip according to claim 1, It is characterized in that A second conductive electrode is disposed on the second light emitting unit. The second conductive electrode is a P-type electrode, and the second conductive electrode is electrically connected to the second light emitting unit.

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