Linear Hall chip with adjustable power consumption

Abstract

The utility model discloses a linear Hall chip with adjustable power consumption, which comprises a Hall element, a voltage amplification circuit, an offset voltage elimination circuit, an output amplification circuit, a clock control circuit and a chip output port, a voltage amplification circuit, an offset voltage elimination circuit and an output amplification circuit which are connected in sequence are arranged between the Hall element and the chip output port; wherein the clock control circuit comprises a system clock, a frequency divider, a clock selector and a clock change-over switch, the system clock is connected with the clock selector through a first branch and a second branch, the first branch is provided with the frequency divider, one end of the clock change-over switch is connected with a main control chip outside the linear Hall chip, and the other end of the clock change-over switch is connected with the linear Hall chip. The other end is connected with the clock selector, and the clock selector is connected with the offset voltage elimination circuit.

Description

Technical Field

[0001] The utility model relates to the technical field of Hall chips, in particular to a linear Hall chip with adjustable power consumption. Background Art

[0002] Linear Hall Sensor is a sensor chip based on the Hall effect. The Hall effect means that when a current flows through a conductor or semiconductor, a voltage will be generated in the conductor material perpendicular to the current direction. This voltage is also perpendicular to the current direction. Linear Hall chip is a sensor that uses this Hall effect principle to measure the magnetic field strength. Linear Hall chip is widely used in current / voltage sensing, speed detection and other fields, and is the core device for realizing accurate magnetic field detection.

[0003] In the related technology, most linear Hall chips can only maintain a single power continuous output, resulting in the chip's working power consumption basically remaining at a high level. The power consumption is large when working, and it is not suitable for many wireless application scenarios. Utility Model Content

[0004] The utility model aims to solve at least one of the technical problems existing in the prior art. To this end, the utility model proposes a linear Hall chip with adjustable power consumption, which adjusts the power consumption of the chip according to the working scenario of the Hall chip, thereby improving the applicability of the Hall chip.

[0005] According to an embodiment of the utility model, a linear Hall chip with adjustable power consumption includes a Hall element, a voltage amplification circuit, an offset voltage elimination circuit, an output amplification circuit, a clock control circuit, a bias circuit and a chip output port, wherein the Hall element and the chip output port include the voltage amplification circuit, the offset voltage elimination circuit and the output amplification circuit connected in sequence;

[0006] Among them, the clock control circuit includes a system clock, a frequency divider, a clock selector and a clock switching switch, the system clock is connected to the clock selector through a first branch and a second branch, wherein the frequency divider is arranged on the first branch, one end of the clock switching switch is connected to the main control chip outside the linear Hall chip, and the other end is connected to the clock selector, and the clock selector is respectively connected to the voltage amplifier circuit and the output amplifier circuit through the bias circuit.

[0007] The linear Hall chip according to the embodiment of the utility model has at least the following beneficial effects:

[0008] The working clock of the linear Hall chip of the utility model can be dynamically switched and adjusted by the external main control chip sending a signal to the clock switching switch. When high-precision and high-bandwidth measurement is required, it can be switched to a high-frequency system clock, which has high power consumption; when high precision is not required, it can be switched to a low-frequency divided clock to reduce power consumption. By introducing the clock control circuit, the linear Hall chip is endowed with the ability to adjust power consumption, which can save power consumption accordingly while meeting the accuracy requirements in different application scenarios.

[0009] The utility model discloses a linear Hall chip with adjustable power consumption, comprising a Hall element, a voltage amplifying circuit, an offset voltage elimination circuit, an output amplifying circuit, a clock control circuit and a chip output port, wherein the Hall element and the chip output port comprise the voltage amplifying circuit, the offset voltage elimination circuit and the output amplifying circuit connected in sequence; wherein the clock control circuit comprises a system clock, a frequency divider, a clock selector and a clock switching switch, wherein the system clock is connected to the clock selector through a first branch and a second branch, wherein the frequency divider is arranged on the first branch, one end of the clock switching switch is connected to a main control chip outside the linear Hall chip, and the other end is connected to the clock selector, and the clock selector is connected to the offset voltage elimination circuit.

[0010] According to some embodiments of the present invention, the wire between the output amplifier circuit and the chip output port is grounded via a Schottky diode.

[0011] The clock selector is also connected to the Hall element and the offset voltage elimination circuit respectively through a digital logic circuit.

[0012] According to some embodiments of the utility model, the voltage amplification circuit also includes an omnipolar Hall voltage amplifier, a unipolar Hall voltage amplifier, a non-polar Hall voltage amplifier and a polarity control switch, the omnipolar Hall voltage amplifier, the unipolar Hall voltage amplifier and the non-polar Hall voltage amplifier are connected in parallel between the Hall element and the polarity control switch, and the polarity control switch is connected to the offset voltage elimination circuit.

[0013] According to some embodiments of the utility model, the polarity simulation switch is provided with a polarity control signal input port, and the polarity control signal input port is used to receive a polarity control signal, so that the polarity control switch selects a corresponding voltage amplifier among the omnipolar Hall voltage amplifier, the unipolar Hall voltage amplifier and the non-polar Hall voltage amplifier according to the polarity control signal.

[0014] According to some embodiments of the present utility model, the output amplifier circuit includes an output amplifier, a first array circuit and a second array circuit, the first input end of the output amplifier is connected to the first array circuit, the second input end is connected to the second array circuit, and the output end of the output amplifier is connected to the chip output port;

[0015] Wherein, the first array circuit and the second array circuit both include a sensitivity resistor array and a resistor array selection switch, the sensitivity resistor array is connected to the first input terminal or the second input terminal, and the resistor array selection switch is connected to the sensitivity resistor array.

[0016] According to some embodiments of the utility model, a sensitivity control signal input port is provided on the resistor array selection switch, and the sensitivity control signal input port is used to receive a sensitivity control signal so that the resistor array selection switch changes the resistance value of the first array circuit and the second array circuit access circuit according to the sensitivity control signal.

[0017] According to some embodiments of the present invention, the linear Hall chip further includes a step-down circuit, and the step-down circuit is arranged between the Hall element and the voltage amplification circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the specific implementation of the utility model or the technical solution in the prior art, the following is a brief introduction to the drawings required for the specific implementation or the prior art description. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, each element or part is not necessarily drawn according to the actual scale.

[0019] Figure 1 A block diagram of a linear Hall chip with adjustable power consumption provided by an embodiment of the utility model;

[0020] Figure 2 A schematic diagram of a voltage amplification circuit of a linear Hall chip with adjustable power consumption provided in an embodiment of the utility model;

[0021] Figure 3 A schematic diagram of an output amplifier circuit of a linear Hall chip with adjustable power consumption provided in an embodiment of the utility model;

[0022] Figure 4 Another module block diagram of a linear Hall chip with adjustable power consumption provided by an embodiment of the utility model; Description of the drawings:

[0024] Hall element 100,

[0025] Voltage amplifier circuit 200, omnipolar Hall voltage amplifier 210, unipolar Hall voltage amplifier 220, non-polar Hall voltage amplifier 230, polarity control switch 240,

[0026] The offset voltage cancellation circuit 300,

[0027] output amplifier circuit 400, output amplifier 410, first array circuit 420, second array circuit 430, first sensitivity resistor array 421, second sensitivity resistor array 431, first resistor array selection switch 422, second resistor array selection switch 432,

[0028] Clock control circuit 500, clock switching switch 510, system clock 520, frequency divider 530, clock selector 540,

[0029] Chip output port 600,

[0030] Schottky diode 700

[0031] Bias circuit 800,

[0032] Digital logic circuit 900,

[0033] Buck circuit 1000. DETAILED DESCRIPTION

[0034] The following embodiments of the technical solution of the utility model are described in detail in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the utility model, and are therefore only used as examples, and cannot be used to limit the protection scope of the utility model.

[0035] It should be noted that, unless otherwise specified, the technical terms or scientific terms used in this application should have the common meanings understood by technicians in the field to which the utility model belongs.

[0036] like Figure 1 As shown, a linear Hall chip with adjustable power consumption includes a Hall element 100, a voltage amplifier circuit 200, an offset voltage elimination circuit 300, an output amplifier circuit 400, a clock control circuit 500 and a chip output port 600, wherein the Hall element 100 and the chip output port 600 include the voltage amplifier circuit 200, the offset voltage elimination circuit 300 and the output amplifier circuit 400 connected in sequence;

[0037] Among them, the clock control circuit 500 includes a system clock 520, a divider 530, a clock selector 540 and a clock switching switch 510. The system clock 520 is connected to the clock selector 540 through a first branch and a second branch, wherein the divider 530 is arranged on the first branch, one end of the clock switching switch 510 is connected to a main control chip (not shown) outside the linear Hall chip, and the other end is connected to the clock selector 540. The clock selector 540 is respectively connected to the voltage amplifier circuit 200 and the output amplifier circuit 400 through the bias circuit 800.

[0038] Among them, the Hall element 100 is used to measure the magnetic field strength, the voltage amplifier circuit 200 is used to amplify the output of the Hall element 100, and the offset voltage elimination circuit 300 is used to eliminate or weaken the output offset voltage of the previous stage, eliminate the output error of the amplifier itself, and thus reduce the magnetic field recognition error. The offset voltage is caused by the internal factors of the operational amplifier of the voltage amplifier circuit 200. When the input of the operational amplifier is 0, the output is not 0, and the output voltage of this part is the offset voltage. This voltage will affect the accuracy of the output signal of the operational amplifier. The output amplifier circuit 400 is used to further amplify or condition the digital signal, the clock control circuit 500 is used to control the chip working clock frequency, and the bias circuit 800 is connected to the clock selector 540, and is respectively connected to the voltage amplifier circuit 200 and the output amplifier circuit 400, and is used to adjust the working state of these circuits to adapt to the different clock frequencies selected by the clock selector.

[0039] Among them, the clock control circuit 500 is the key to achieving adjustable power consumption: the system clock 520 provides a reference clock source for the chip, the divider 530 can divide the reference clock frequency, the clock selector 540 can choose to use the reference clock or the divided clock, and the clock switching switch 510 is controlled by the main control chip to decide which clock input to select.

[0040] Among them, the clock control circuit 500 uses the switching circuit of the bias circuit 800, which can switch the output bias to normally open or periodically open according to the input. When normally open is selected, the bias circuit 800 continuously outputs bias voltage and current to keep the operational amplifier in operation; when periodically open is selected, the bias circuit 800 outputs the periodic output of the slow clock so that the operational amplifier is also in a periodic working state, thereby reducing the power consumption of the operational amplifier.

[0041] The clock control circuit 500 is switched through the clock switching switch 510; when the clock switching switch 510 inputs 1, the slower system clock after frequency division is selected, and the bias circuit 800 input of the Hall voltage amplifier circuit is synchronized to the start-up frequency corresponding to the slow system clock 520, so that the entire chip system enters a periodic working state to reduce power consumption; when the clock switching switch 510 inputs 0, the normal speed system clock 520 is selected, and the bias switch circuit 800 is switched to the normally open state, so that the entire chip enters a normal mode of continuous operation.

[0042] This embodiment enables the working clock of the chip to be dynamically switched and adjusted by the external main control chip through a switch. When high-precision and high-bandwidth measurement is required, it can be switched to a high-frequency system clock, which consumes more power; when high-precision is not required, it can be switched to a low-frequency divided clock to reduce power consumption.

[0043] The introduction of the clock control circuit 500 enables the linear Hall chip to adjust power consumption, thereby meeting the accuracy requirements in different application scenarios while also saving power consumption and extending service life. The different requirements of the integrated sensor chip for power consumption and accuracy in different working modes are fully considered, thereby improving the application scope and flexibility of the chip.

[0044] Furthermore, the wire between the output amplifier circuit 400 and the chip output port 600 is grounded through a Schottky diode 700 .

[0045] The Schottky diode 700 can prevent the external improper voltage / signal from being reversely injected into the internal circuit of the chip, thereby playing the role of input terminal protection, which can prevent the internal precision circuit of the chip from being damaged by reverse injected overvoltage / overcurrent.

[0046] It should be noted that the Schottky diode 700 has a small forward conduction voltage drop characteristic, and when working under normal conditions, it will hardly produce a significant voltage drop and attenuation effect on the normal output signal of the linear Hall circuit, so that the original characteristics and accuracy of the output signal can be retained to the greatest extent.

[0047] Therefore, using Schottky diode 700 for output protection can effectively protect the chip from external misoperation or signal impact. At the same time, due to its own small voltage drop characteristics, it will basically not affect the integrity and accuracy of the output signal of the linear Hall circuit under normal working conditions.

[0048] Furthermore, the clock selector 500 is also connected to the Hall element 100 and the offset voltage elimination circuit 300 respectively through the digital logic circuit 900, allowing the clock selector 500 to dynamically adjust the working status of the Hall element 100 and the offset voltage elimination circuit 300 according to the needs of the system, thereby optimizing the performance and power consumption of the entire chip.

[0049] Furthermore, if Figure 2 As shown, the voltage amplifier circuit 200 also includes an omnipolar Hall voltage amplifier 210, a unipolar Hall voltage amplifier 220, a non-polar Hall voltage amplifier 230 and a polarity control switch 240. The omnipolar Hall voltage amplifier 210, the unipolar Hall voltage amplifier 220 and the non-polar Hall voltage amplifier 230 are connected in parallel between the Hall element 100 and the polarity control switch 240, and the polarity control switch 240 is connected to the offset voltage elimination circuit 300.

[0050] Furthermore, a polarity control signal input port 250 is provided on the polarity control switch 240, and the polarity control signal input port 250 is used to receive an external polarity control signal. The polarity control switch 240 dynamically selects one of the outputs from the three amplifiers of omnipolarity, unipolarity and non-polarity according to the received polarity control signal, and the selected amplifier output will be sent to the subsequent offset voltage elimination circuit 300 for processing.

[0051] Different types of amplifiers are suitable for different magnetic field polarity detection requirements. By connecting three amplifiers in parallel, the needs of three different application scenarios, omnipolar, unipolar and non-polar, can be met. Through the polarity control switch 240, the output of which amplifier can be dynamically switched, so that the offset voltage elimination circuit 300 can flexibly receive omnipolar, unipolar or non-polar input signals.

[0052] The polarity control signal is a two-bit control signal, and the polarity control signal input port 250 includes two signal receiving ports, and the corresponding truth table is as follows:

[0053]

[0054]

[0055] Table 1 Polarity control switch truth table

[0056] As shown in Table 1, the control selection results of the polarity control switch 240 include:

[0057] When the control signal 0 is input to port 1 of the polarity control switch 240 and the control signal 1 is input to port 2, the polarity control switch 240 selects the omnipolar Hall voltage amplifier 210 as the output of the voltage operational amplifier circuit, that is, the linear Hall chip is in omnipolar mode at this time: the output voltage is half of the power supply voltage when the magnetic field is zero, and when the S magnetic pole is close to the chip marking surface, the output voltage will increase linearly with the increase of the magnetic field strength; on the contrary, the N magnetic pole will make the output voltage decrease linearly with the increase of the magnetic field strength.

[0058] When the control signal 1 is input to port 1 of the polarity control switch 240 and the control signal 0 is input to port 2, the polarity control switch 240 selects the unipolar Hall voltage amplifier 220 as the output of the voltage operational amplifier circuit, that is, the linear Hall chip is in unipolar mode at this time: the output voltage is zero when the magnetic field is zero, and when the S pole or N pole chip is marked, the output voltage will increase linearly with the increase of the magnetic field strength.

[0059] When control signal 1 is input to port 1 of polarity control switch 240 and control signal 1 is input to port 2, polarity control switch 240 selects non-polarity Hall voltage amplifier 230 as the output of voltage operational amplifier circuit, that is, linear Hall chip is in non-polarity mode at this time: output voltage is zero at zero magnetic field, and when S pole and N pole chip are marked, output voltage will increase linearly with the increase of magnetic field strength.

[0060] It should be noted that the logical relationship in Table 1 is only used as an example. In actual applications, the control selection logic of the polarity control switch 240 can be set according to actual conditions and is not limited here.

[0061] Furthermore, if Figure 3 As shown, the output amplifier circuit 400 includes an output amplifier 410, a first array circuit 420 and a second array circuit 430, a first input terminal of the output amplifier 410 is connected to the first array circuit 420, a second input terminal is connected to the second array circuit 430, and an output terminal of the output amplifier 410 is connected to a chip output port 600;

[0062] Among them, the first array circuit 420 and the second array circuit 430 both include sensitivity resistor arrays and resistor array selection switches, wherein the first array circuit 420 includes a first sensitivity resistor array 421 and a first resistor array selection switch 422, and the second array circuit 430 includes a second sensitivity resistor array 431 and a second resistor array selection switch 432, the first sensitivity resistor array 421 and the second sensitivity resistor array 431 are respectively connected to the output amplifier 410, the first resistor array selection switch 422 is connected to the first sensitivity resistor 421, and the second resistor array selection switch 432 is connected to the second sensitivity resistor 431.

[0063] Furthermore, a sensitivity control signal input port 440 is provided on the first resistor array selection switch 422 and the second resistor array selection switch 432, and the sensitivity control signal input port 440 is used to receive a sensitivity control signal so that the first resistor array selection switch 422 and the second resistor array selection switch 432 change the resistance value of the circuit connected to the first array circuit 420 and the second array circuit 430 according to the sensitivity control signal.

[0064] In some examples, the positive input terminal of the output amplifier 410 is connected to the first array circuit 420, and the reverse input terminal is connected to the second array circuit 430. This connection method of different positive feedback resistors realizes the adjustability of the amplifier gain. The gain of the amplifier is equal to the ratio of the feedback resistor to the input resistor. When the control signal of the first resistor array selection switch 422 and the second resistor array selection switch 432 changes, the equivalent resistance of the first sensitivity resistor array 421 and the second sensitivity resistor array 431 will change, resulting in the ratio of the feedback resistor to the input resistor also changing, thereby adjusting the gain of the amplifier. Finally, the output voltage of the output amplifier 410 will be equal to the output voltage of the linear Hall chip multiplied by the adjustable gain. By changing the gain, the linear adjustment of the output sensitivity of the linear Hall chip can be achieved. This design based on the inverting amplifier and adjusting the gain by changing the positive feedback resistor ratio makes the amplification adjustment of the entire circuit more accurate and linear, and has better noise resistance.

[0065] Further, the sensitivity control signal is a three-bit control signal, and the sensitivity control signal input port 440 includes three signal receiving ports. According to the sensitivity control signal, the first sensitivity resistor array 421 and the second sensitivity resistor array 431 are short-circuited and open-circuited in part of the unit resistance according to the preset control logic, and a variety of resistor array combinations are provided to adjust the output resistance of the first sensitivity resistor array 421 and the second sensitivity resistor array 431, and then adjust the resistance ratio of the output amplifier 410, so as to adjust the output sensitivity of the linear Hall chip. This embodiment takes Table 2 as an example to illustrate the control adjustment results of the first resistor array selection switch 422 and the second resistor array selection switch 432:

[0066]

[0067]

[0068] Table 2 Resistor array selector switch truth table

[0069] As shown in Table 2, the first resistor array selection switch 422 and the second resistor array selection switch 432 can adjust different output sensitivities according to the three-way input control signal. It should be noted that the specific values ​​and logical relationships in Table 2 are only used as examples. In actual applications, the output sensitivity adjustment results of the Hall chip by the first resistor array selection switch 422 and the second resistor array selection switch 432 can be set according to actual conditions and are not limited here.

[0070] In actual applications, the polarity control switch 240, the first resistor array selection switch 422, and the second resistor array selection switch 432 are controlled by setting a small PAD with a corresponding number of bits. When the chip package is wired, the corresponding PADs are respectively wired to the power supply or ground, and the output of the analog switch is selected according to the truth table through different voltage combinations.

[0071] Furthermore, if Figure 4 As shown, the linear Hall chip further includes a buck circuit 1000, and the buck circuit 1000 is arranged between the Hall element and the voltage amplification circuit.

[0072] In some embodiments, the buck circuit 1000 is an LDO (Low Drop Out) buck circuit. LDO is a linear regulator that stably reduces the input voltage to a preset output voltage value. The output voltage of the Hall element may not match the operating voltage of the subsequent amplifier circuit. LDO can accurately reduce the input voltage to the voltage range required by the amplifier circuit to avoid operating point offset or component damage. In addition, LDO can not only stabilize the voltage, but also effectively suppress interference such as ripple and noise at the input end, provide a clean and stable operating voltage for the subsequent sensitive analog circuit, and improve the system's anti-interference ability. The LDO buck circuit usually adopts the working principle of feedback control and can accurately adjust and regulate the output voltage. Although its efficiency is slightly lower than that of the switching buck, it has the advantages of strong voltage resistance, small ripple, and small EMI radiation, and is very suitable for powering high-precision analog and digital circuits.

[0073] The working clock of the linear Hall chip of the utility model can be dynamically switched and adjusted by the external main control chip sending a signal to the clock switching switch. When high-precision and high-bandwidth measurement is required, it can be switched to a high-frequency system clock, which has high power consumption; when high precision is not required, it can be switched to a low-frequency divided clock to reduce power consumption. By introducing the clock control circuit, the linear Hall chip is endowed with the ability to adjust power consumption, which can save power consumption accordingly while meeting the accuracy requirements in different application scenarios.

[0074] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the utility model, rather than to limit it. Although the utility model has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. These modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the utility model, and they should all be included in the scope of the claims and specification of the utility model.

Claims

1. A linear Hall chip with adjustable power consumption, characterized in that: It includes a Hall element, a voltage amplification circuit, an offset voltage elimination circuit, an output amplification circuit, a clock control circuit, a bias circuit and a chip output port, wherein the voltage amplification circuit, the offset voltage elimination circuit and the output amplification circuit are connected in sequence between the Hall element and the chip output port; Among them, the clock control circuit includes a system clock, a frequency divider, a clock selector and a clock switching switch, the system clock is connected to the clock selector through a first branch and a second branch, wherein the frequency divider is arranged on the first branch, one end of the clock switching switch is connected to the main control chip outside the linear Hall chip, and the other end is connected to the clock selector, and the clock selector is respectively connected to the voltage amplifier circuit and the output amplifier circuit through the bias circuit.

2. A linear Hall chip with adjustable power consumption according to claim 1, characterized in that: The wire between the output amplifier circuit and the chip output port is grounded through a Schottky diode.

3. The linear Hall chip with adjustable power consumption according to claim 1, characterized in that: The clock selector is also connected to the Hall element and the offset voltage elimination circuit respectively through a digital logic circuit.

4. The linear Hall chip with adjustable power consumption according to claim 1, characterized in that: The voltage amplification circuit also includes an omnipolar Hall voltage amplifier, a unipolar Hall voltage amplifier, a non-polar Hall voltage amplifier and a polarity control switch. The omnipolar Hall voltage amplifier, the unipolar Hall voltage amplifier and the non-polar Hall voltage amplifier are connected in parallel between the Hall element and the polarity control switch, and the polarity control switch is connected to the offset voltage elimination circuit.

5. The linear Hall chip with adjustable power consumption according to claim 4, characterized in that: The polarity simulation switch is provided with a polarity control signal input port, and the polarity control signal input port is used to receive a polarity control signal, so that the polarity control switch selects a corresponding voltage amplifier from the omnipolar Hall voltage amplifier, the unipolar Hall voltage amplifier and the non-polar Hall voltage amplifier according to the polarity control signal.

6. The linear Hall chip with adjustable power consumption according to claim 1, characterized in that: The output amplifier circuit comprises an output amplifier, a first array circuit and a second array circuit, a first input terminal of the output amplifier is connected to the first array circuit, a second input terminal is connected to the second array circuit, and an output terminal of the output amplifier is connected to the chip output port; Wherein, the first array circuit and the second array circuit both include a sensitivity resistor array and a resistor array selection switch, the sensitivity resistor array is connected to the first input terminal or the second input terminal, and the resistor array selection switch is connected to the sensitivity resistor array.

7. The linear Hall chip with adjustable power consumption according to claim 6, characterized in that: The resistor array selection switch is provided with a sensitivity control signal input port, and the sensitivity control signal input port is used to receive a sensitivity control signal so that the resistor array selection switch changes the resistance value of the first array circuit and the second array circuit access circuit according to the sensitivity control signal.

8. The linear Hall chip with adjustable power consumption according to claim 1, characterized in that: The linear Hall chip further includes a step-down circuit, which is arranged between the Hall element and the voltage amplification circuit.

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