Chip high-density wiring packaging structure

Abstract

The utility model relates to a chip high-density wiring packaging structure, which comprises a circuit substrate. The upper carrier plate is arranged above the circuit substrate, the upper carrier plate comprises a plurality of groups of carrier plates, and every two adjacent groups of carrier plates are communicated through lead bonding; the plurality of groups of carrier plates are connected with the upper end of the circuit substrate; the chips comprise first chips and second chips, the multiple groups of first chips are stacked at the upper end of the circuit substrate, and the first chips are electrically connected to the circuit substrate; the second chip is arranged at the upper end of the carrier plate, and the second chip is electrically connected to the carrier plate. By adopting the structure, the interference during signal operation is reduced, the diversified functions of the product are improved, and an integrated chip with more functions is formed.

Description

Technical Field

[0001] The utility model relates to the technical field of chip packaging, in particular to a chip high-density wiring packaging structure. Background Art

[0002] With the continuous development of science and technology, the functions of electronic devices are becoming more and more abundant, and the requirements for chip integration and performance are becoming higher and higher. Traditional chip packaging technology can no longer meet the needs of modern electronic devices.

[0003] Although chip packaging technology is mature today, when faced with more complex chip packaging needs, there are generally difficulties and troubles in circuit wiring design. It is often necessary to use more substrate wiring layers (2 layers, 4 layers, 6 layers, 8 layers), and increase the thickness of the substrate in exchange for a better wiring area, but at the same time increase the difficulty and cost of substrate production, and also reduce the available space for bare chip packaging, resulting in the chip packaging process can not play a greater role, or integrate more chip functions and make the package size can not be reduced.

[0004] Therefore, there is an urgent need to provide a chip high-density wiring packaging structure to solve the above problems. Utility Model Content

[0005] The purpose of the utility model is to overcome the shortcomings and defects of the prior art, provide a chip high-density wiring packaging structure, reduce interference during signal operation, enhance product diversification, and form an integrated chip with more functions.

[0006] The purpose of this utility model is achieved through the following technical solutions:

[0007] A chip high-density wiring packaging structure, characterized by comprising:

[0008] Circuit substrate;

[0009] An upper carrier board is arranged above the circuit substrate, and the upper carrier board includes a plurality of carrier boards, and two adjacent carrier boards are connected by wire bonding; the plurality of carrier boards are connected to the upper end of the circuit substrate;

[0010] The chip includes a first chip and a second chip, wherein a plurality of groups of the first chips are stacked on the upper end of the circuit substrate, and the first chips are electrically connected to the circuit substrate; the second chip is arranged on the upper end of the carrier, and the second chip is electrically connected to the carrier.

[0011] Optionally, a wiring layer is provided on the upper end of the second chip, the wiring layer is arranged at one end of the second chip away from the carrier board, and two adjacent second chips are connected by wire bonding through the wiring layer.

[0012] Optionally, the chip high-density wiring packaging structure further includes a wire, and the wiring layer is electrically connected to the circuit substrate through the wire.

[0013] Optionally, the upper loading board is arranged adjacent to the first chip.

[0014] Optionally, the second chip is fixed on the carrier board after being packaged as an integrated circuit.

[0015] Optionally, the integrated circuit package is configured as a BGA package.

[0016] Optionally, the second chip includes a flip chip, and the second chip is connected to the carrier board via the flip chip.

[0017] Optionally, the second chip also includes a radio frequency chip.

[0018] Compared with the prior art, the utility model has the following beneficial effects:

[0019] In the utility model, the chip high-density wiring sealing structure includes a circuit substrate and an upper carrier plate, wherein the upper carrier plate is arranged above the circuit substrate and is detachably connected to the circuit substrate, the upper carrier plate is provided with multiple groups of carrier plates, two adjacent groups of carrier plates are connected by wire bonding, so that adjacent carrier plates can be connected to each other and realize signal connection; the chip includes a first chip and a second chip, and the first chip and the second chip are both provided with multiple groups, the first chip is electrically connected to the circuit substrate, so that the first chip stack formed by stacking the first chips on each other can also connect and exchange signals between the circuit substrates, and the second chip is arranged at the upper end of the carrier plate to realize signal connection and conduction between the second chip and the circuit substrate; through the separate arrangement of multiple groups of carrier plates, the packaging design of the multi-functional chip is realized, the interference during signal operation is reduced, the diversified functions of the product are improved, and a more functional integrated chip is formed. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is the structural principle diagram of the utility model.

[0021] Figure 2 It is a schematic diagram of the packaging principle in the utility model.

[0022] The above drawings include the following reference numerals:

[0023] 1. Circuit substrate, 2. Upper carrier board, 21. Carrier board, 31. First chip, 32. Second chip, 33. Wire, 41. Flip chip, 42. RF chip, 43. Power chip, 44. IO chip, 45. Circuit packaging. DETAILED DESCRIPTION

[0024] The present invention is further described in detail below in conjunction with embodiments and drawings, but the implementation manner of the present invention is not limited thereto.

[0025] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "provided with", "connected", etc. should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the technical field of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0027] The technical solution of the utility model proposes a chip high-density wiring packaging structure.

[0028] Reference Figure 1 and Figure 2 , in this embodiment, includes:

[0029] Circuit substrate 1;

[0030] The upper carrier board 2 is disposed above the circuit substrate 1. The upper carrier board 2 includes a plurality of carrier boards 21. Two adjacent carrier boards 21 are connected by wire bonding. The plurality of carrier boards 21 are connected to the upper end of the circuit substrate 1.

[0031] The chip includes a first chip 31 and a second chip 32. Multiple groups of first chips 31 are stacked on the upper end of the circuit substrate 1, and the first chip 31 is electrically connected to the circuit substrate 1; the second chip 32 is arranged on the upper end of the carrier 21, and the second chip 32 is electrically connected to the carrier 21.

[0032] Optionally, in this embodiment, the chip high-density wiring sealing structure includes a circuit substrate 1 and an upper carrier board 2, wherein the upper carrier board 2 is arranged above the circuit substrate 1 and is detachably connected to the circuit substrate 1, and the upper carrier board 2 is provided with a plurality of groups of carrier boards 21, two adjacent groups of carrier boards 21 are connected by wire bonding, and the communication interfaces on each group of carrier boards 21 are retained, and the adjacent carrier boards 21 can be connected by wire bonding to achieve signal connection; the chip includes a first chip 31 and a second chip 32, and the first chip 31 and the second chip 32 are provided with a plurality of groups, and the plurality of groups of first chips 31 are arranged on the upper end of the circuit substrate 1 in a stacked manner, and the adjacent first chips 31 are connected by wires to achieve signal connection and conduction, and the first chip 31 The second chip 32 is electrically connected to the circuit substrate 1, that is, the stack of first chips 31 formed by stacking the first chips 31 on each other can also connect and exchange signals between the circuit substrates 1. The second chip 32 is arranged on the upper end of the carrier 21, wherein the carrier 21 is arranged on the upper end of the circuit substrate 1, that is, the second chip 32 is electrically connected to the carrier 21, that is, the second chip 32 is connected to the circuit substrate 1 through the carrier 21, so as to realize the signal connection and conduction between the second chip 32 and the circuit substrate 1; through the separate arrangement of multiple groups of carriers 21, it is prevented that the number of layers of the carrier 21 is increased when multiple functional chips need to be made, resulting in wiring difficulties, expanding the functionality of the chip, and preventing the problems of signal transmission being interfered with and insufficient wiring distance in the production of multifunctional chips, thereby realizing the packaging design of multifunctional chips. The separated structure can create a better EMS effect, that is, electromagnetic sensitivity, reduce interference during signal operation, enhance product diversification functions, and form more functional integrated chips.

[0033] In the present embodiment, a wiring layer is provided at the upper end of the second chip 32, and the wiring layer is provided at one end of the second chip 32 away from the carrier 21, and two adjacent groups of second chips 32 are connected by wire bonding through the wiring layer, that is, the two adjacent groups of carriers 21 can be connected through the connection between the two groups of second chips 32, thereby realizing separate connection of multiple groups of carriers 21, and the types of chips arranged on different groups of carriers 21 can be different, thereby improving the versatility of the chip; further, in the present embodiment, the chip high-density wiring packaging structure also includes a wire 33, and the wiring layer on the second chip 32 can be electrically connected to the circuit substrate 1 by bonding the wire 33, and on the circuit substrate 1, the upper carrier 2 is arranged adjacent to the first chip 31, that is, the carriers 21 are arranged adjacent to the first chip 31, so that the space occupied by the carrier 21 is reduced as much as possible.

[0034] In this embodiment, the second chip 32 is fixed on the carrier 21 after being packaged with an integrated circuit 45. By using a single second chip 32 with an integrated circuit package 45, or integrating multiple carriers 21 and second chips 32 into another high-density stacked or multifunctional package sheet by packaging and bonding, the possibility and flexibility of product application are directly expanded. The circuit packaging 45 of the second chip 32 can better protect the chip and prevent the chip from being affected by the external environment, such as moisture or impurities in the air, etc., which can improve the stability and service life of the chip and prevent mechanical damage to the chip during transportation. The integrated circuit package 45 stacks multiple chips together to form a highly integrated circuit system, which can reduce the volume of the entire system, improve the integration, and facilitate the thinning and miniaturization of the product. Further, in this embodiment, the integrated circuit package 45 is configured as a BGA package. The BGA package connects the electrodes of the integrated circuit to the substrate through small balls to achieve high-density and high-speed signal transmission. The integrated circuit package 45 can use an LGA package or a CSP package, which is not limited here.

[0035] In this embodiment, the second chip 32 also includes a flip chip 41, and the second chip 32 is connected to the carrier 21 through the flip chip 41. Compared with the traditional wire bonding method, the flip chip 41 directly deposits bumps on the I / O pads of the chip, and then flips the chip for heating, so that the molten solder is combined with the substrate or frame, and the chip electrical surface faces down. This method solves the electromagnetic compatibility and electromagnetic interference problems and can withstand higher frequencies; the I / O density is high, which can effectively reduce the packaging area; the flip packaging form allows the back of the chip to directly contact the air, thereby improving the heat dissipation capacity of the chip. Further, the second chip 32 also includes a radio frequency chip 42, which is responsible for receiving and transmitting wireless signals. The second chip 32 also includes a power chip 43 and an IO chip 44, wherein the power chip 43 is stacked and connected to the carrier 21 by wire bonding. The power chip 43 is mainly responsible for providing and regulating electrical energy to ensure the normal operation of the chip; the IO chip 44 is responsible for realizing the communication between the chip and the external environment. It contains input and output circuits for receiving and sending signals, so that the chip can exchange data and control with external devices.

[0036] The above-mentioned embodiments only express the implementation methods of the utility model, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent of the utility model. It should be pointed out that, for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the utility model, and these all belong to the protection scope of the utility model. Therefore, the protection scope of the utility model patent shall be based on the attached claims.

Claims

1. A chip high-density wiring packaging structure, characterized in that: include: Circuit substrate; An upper carrier board is provided above the circuit substrate, and the upper carrier board includes multiple groups of carrier boards, and two adjacent groups of carrier boards are connected by wire bonding; the multiple groups of carrier boards are all connected to the upper end of the circuit substrate; The chip includes a first chip and a second chip, multiple groups of the first chips are stacked on the upper end of the circuit substrate, and the first chips are electrically connected to the circuit substrate; the second chip is arranged on the upper end of the carrier, and the second chip is electrically connected to the carrier.

2. A chip high-density wiring packaging structure according to claim 1, characterized in that: A wiring layer is provided on the upper end of the second chip. The wiring layer is arranged at one end of the second chip away from the carrier board. Two adjacent second chips are connected by wire bonding through the wiring layer.

3. A chip high-density wiring packaging structure according to claim 2, characterized in that: The chip high-density wiring packaging structure further includes a wire, and the wiring layer is electrically connected to the circuit substrate through the wire.

4. The chip high-density wiring packaging structure according to claim 1, characterized in that: The upper carrier board is disposed adjacent to the first chip.

5. The chip high-density wiring packaging structure according to claim 1, characterized in that: The second chip is fixed on the carrier board after being packaged by an integrated circuit.

6. The chip high-density wiring packaging structure according to claim 5, characterized in that: The integrated circuit package is configured as a BGA package.

7. The chip high-density wiring packaging structure according to claim 1, characterized in that: The second chip includes a flip chip, and the second chip is connected to the carrier board through the flip chip.

8. The chip high-density wiring packaging structure according to claim 1, characterized in that: The second chip also includes a radio frequency chip.

Images