Semiconductor device

Abstract

The utility model provides a semiconductor device. The semiconductor device includes a photodiode and an isolation structure at least partially surrounding the photodiode. The semiconductor device includes a grid structure on the isolation structure, wherein the grid structure includes a metal layer having at least one air gap and at least one dielectric layer. Shielding structures of air gaps formed on a grid structure between pixel sensors in a pixel array reduce crosstalk. The efficiency and signal-to-noise ratio of the pixel sensor are increased due to the reduction of crosstalk. Because the air gap does not absorb photons, the shielding structure also increases the quantum efficiency of the pixel array.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device including a shielding structure having an air gap. Background Art

[0002] Digital cameras and other optical imaging devices use image sensors. Image sensors convert optical images into digital data, which can be presented as digital images. Image sensors include a pixel sensor array and supporting logic. The pixel sensor array is a unit device used to measure incident light, and the supporting logic facilitates the output of the measurement. One type of image sensor used in optical imaging devices is a back side illumination (BSI) image sensor. For low cost, small size and high integration, the manufacture of BSI image sensors can be integrated into semiconductor processes. Furthermore, BSI image sensors have low operating voltage, low power consumption, high quantum efficiency and low output noise, and allow random access. Utility Model Content

[0003] One aspect of the present disclosure is to provide a semiconductor device. The semiconductor device includes a photodiode and an isolation structure at least partially surrounding the photodiode. The semiconductor device includes a grid structure on the isolation structure, wherein the grid structure includes a metal layer having at least one air gap and at least one dielectric layer.

[0004] Another aspect of the present disclosure is to provide a semiconductor device, comprising a photodiode; an isolation structure at least partially surrounding the photodiode; a metal layer on the isolation structure, wherein the metal layer comprises an air gap; and at least one dielectric layer on the metal layer, wherein the at least one dielectric layer surrounds the air gap in the metal layer.

[0005] Another aspect of the present disclosure is to provide a semiconductor device. The semiconductor device includes a photodiode, an isolation structure at least partially surrounding the photodiode, and a grid structure on the isolation structure. The isolation structure includes at least one air gap. The grid structure includes a metal layer and at least one dielectric layer, wherein the at least one air gap further extends into the metal layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure is better understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, as is standard practice in the industry, many features are not drawn to scale. In fact, for the sake of clarity of discussion, the dimensions of many features may be arbitrarily scaled.

[0007] Figure 1is a schematic diagram illustrating an exemplary environment in which the system and / or method described in the present disclosure may be implemented;

[0008] Figure 2 is a diagram illustrating an exemplary pixel array described in the present disclosure;

[0009] FIG. 3A to FIG. 3D is a schematic diagram illustrating an exemplary semiconductor structure described in the present disclosure;

[0010] 4A to 4F is a schematic diagram illustrating an exemplary embodiment of the present disclosure;

[0011] FIG. 5A to FIG. 5C is a schematic diagram illustrating an exemplary embodiment of the present disclosure;

[0012] 6A to 6F is a schematic diagram illustrating an exemplary embodiment of the present disclosure;

[0013] FIG. 7A to FIG. 7C is a schematic diagram illustrating an exemplary embodiment of the present disclosure;

[0014] Figure 8 It is a diagram of the disclosure Figure 1 a schematic diagram of exemplary elements of one or more devices;

[0015] Fig. 9 is a flow chart illustrating an exemplary process of fabricating a semiconductor structure according to the present disclosure.

[0016]

Explanation of symbols

[0017] 100: Environment

[0018] 102:Semiconductor process tools / deposition tools

[0019] 104:Semiconductor process tools / exposure tools

[0020] 106:Semiconductor process tools / development tools

[0021] 108:Semiconductor process tools / etching tools

[0022] 110:Semiconductor process tools / planarization tools

[0023] 112:Semiconductor process tools / electroplating tools

[0024] 114:Semiconductor process tools / photoresist removal tools

[0025] 116:Semiconductor process tools / annealing tools

[0026] 118: Wafer / die transfer tool

[0027] 200: Pixel array

[0028] 202: Pixel sensor

[0029] 300: Pixel Array

[0030] 302a, 302b, 302c: pixel sensors

[0031] 304: Base material

[0032] 306: Photodiode

[0033] 308: Isolation Structure

[0034] 310: Anti-reflective coating

[0035] 312: Dielectric layer

[0036] 314:Metal layer

[0037] 316: Grid structure

[0038] 318: Dielectric layer

[0039] 320: Air gap

[0040] 322: Passivation layer

[0041] 324a, 324b, 324c: Color filter area

[0042] 326: Microlens layer

[0043] 332: Dielectric layer

[0044] 330,350,370: Pixel array

[0045] 352: Etching stop layer

[0046] 400, 500, 600, 700: Illustrative Embodiments

[0047] 402: Etching stop layer

[0048] 404: Buffer layer

[0049] 406: Groove

[0050] 500: Example

[0051] 600: Example

[0052] 700: Example embodiment

[0053] 800: Device

[0054] 810: Bus

[0055] 820: Processor

[0056] 830: Memory

[0057] 840: Input component

[0058] 850: Output component

[0059] 860: Communication components

[0060] 900: Craftsmanship

[0061] 910,920,930: Blocks DETAILED DESCRIPTION

[0062] The following disclosure provides many different embodiments or examples to implement different features of the provided aspects. The specific examples of components and configurations described below are intended to simplify the disclosure. These are of course only for illustration and are not intended to be limiting. For example, the description of a first feature formed on or above a second feature includes embodiments in which the first feature and the second feature are in direct contact, and also includes embodiments in which other features are formed between the first feature and the second feature, so that the first feature and the second feature are not in direct contact. In addition, the disclosure repeats component symbols and / or letters in various specific examples. The purpose of this repetition is to simplify and clarify the description and does not indicate a relationship between the various discussed embodiments and / or configurations.

[0063] Furthermore, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," etc., are used to facilitate description of the relationship of parts or features illustrated in the drawings to other parts or features. Spatially relative terms encompass different orientations of the elements in use or operation in addition to the orientation depicted in the drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used in the present disclosure may be interpreted so.

[0064] Optical crosstalk can occur between adjacent pixel regions in a pixel array, such as a back side illumination (BSI) complementary metal oxide semiconductor (CMOS) image sensor and / or other types of CMOS image sensors. Optical crosstalk is a phenomenon where incident light passes through a pixel region at a non-perpendicular angle and is at least partially absorbed by the photodiode of an adjacent pixel region. Optical crosstalk in a pixel array of a CMOS image sensor can reduce the spatial resolution of the CMOS image sensor, reduce the overall sensitivity of the CMOS image sensor, cause color mixing between pixel regions of the CMOS image sensor, and / or cause image noise after color correction.

[0065] In some examples, a shielding structure may be formed on a grid structure between pixel sensors in a pixel array. The shielding structure helps reduce crosstalk between pixel sensors. The shielding structure may be composed of metal, but metal absorbs photons and thus reduces the quantum efficiency (QE) of the pixel array. Therefore, instead, a hybrid shielding structure composed of metal and oxide may be used. The hybrid shielding structure improves the quantum efficiency and signal-to-noise ratio (SNR) of the pixel array. However, the hybrid shielding structure still suffers from quantum efficiency loss due to the metal in the hybrid grid. In addition, the oxide of the hybrid shielding structure increases crosstalk compared to the metal shielding structure.

[0066] Some embodiments described in the present disclosure provide techniques and apparatus for forming shielding structures of air gaps, wherein the air gaps are on a grid structure between pixel sensors in a pixel array. The air gaps reduce crosstalk because air provides near-total reflection, and also increase the quantum efficiency of the pixel array because the air gaps do not absorb photons. In addition, the efficiency and signal-to-noise ratio of the pixel sensor are increased due to the reduction in crosstalk.

[0067] Figure 1 1 is a schematic diagram of an example environment 100 in which the systems and / or methods described herein may be implemented. Figure 1As shown, the environment 100 may include a plurality of semiconductor process tools 102 to 116 and a wafer / die transfer tool 118. The plurality of semiconductor process tools 102 to 116 may include a deposition tool 102, an exposure tool 104, a development tool 106, an etching tool 108, a planarization tool 110, a plating tool 112, a photoresist removal tool 114, an annealing tool 116, and / or other types of semiconductor process tools. The tools included in the exemplary environment 100 may be included in a semiconductor cleaning chamber, a semiconductor wafer foundry, a semiconductor process facility, and / or a manufacturing facility, among other examples.

[0068] Deposition tool 102 is a semiconductor process tool that includes a semiconductor process chamber and one or more devices that can be used to deposit various materials on a substrate. In some embodiments, deposition tool 102 includes a spin coating tool that can be used to deposit a photoresist layer on a substrate such as a wafer. In some embodiments, deposition tool 102 includes a chemical vapor deposition (CVD) tool, such as a plasma enhanced CVD (PECVD) tool, a low pressure CVD (LPCVD) tool, a high-density plasma CVD (HDP-CVD) tool, a sub-atmospheric CVD (SACVD) tool, an atomic layer deposition (ALD) tool, a plasma enhanced atomic layer deposition (PEALD) tool, or other types of chemical vapor deposition tools. In some embodiments, the deposition tool 102 includes a physical vapor deposition (PVD) tool, such as a sputtering tool or other types of PVD tools. In some embodiments, the exemplary environment 100 includes a plurality of deposition tools 102 .

[0069] The exposure tool 104 is a semiconductor processing tool that can expose the photoresist layer to a radiation source, such as an ultraviolet (UV) light source [e.g., a deep UV light source, an extreme UV (EUV) light source, and / or the like], an X-ray light source, an electron beam (e-beam) source, and / or the like. The exposure tool 104 can expose the photoresist layer to the radiation source to transfer a pattern from a mask to the photoresist layer. The pattern can include one or more semiconductor device layer patterns used to form one or more semiconductor devices, can include patterns used to form one or more structures of a semiconductor device, can include patterns used to etch various portions of a semiconductor device, and / or the like. In some embodiments, the exposure tool 104 includes a scanner, an exposure machine, or a similar type of exposure tool.

[0070] The developing tool 106 is a semiconductor process tool that can develop the photoresist layer that has been exposed to the radiation source to develop the pattern transferred to the photoresist layer from the exposure tool 104. In some embodiments, the developing tool 106 develops the pattern by removing the unexposed portion of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by removing the exposed portion of the photoresist layer. In some embodiments, the developing tool 106 dissolves the exposed portion or the unexposed portion of the photoresist layer through the use of a chemical developer to develop the pattern.

[0071] The etching tool 108 is a semiconductor processing tool that can etch various types of substrates, wafers, or materials of semiconductor devices. For example, the etching tool 108 can include a wet etching tool, a dry etching tool, and / or the like. In some embodiments, the etching tool 108 includes a chamber filled with an etchant, and the substrate is placed in the chamber for a specific period of time to remove a specific amount of one or more portions of the substrate. In some embodiments, the etching tool 108 can utilize plasma etching or plasma-assisted etching to etch one or more portions of the substrate, which includes utilizing an ionized gas to etch the one or more portions isotropically or directionally.

[0072] The planarization tool 110 is a semiconductor process tool that can grind or planarize the layers of a wafer or semiconductor device. For example, the planarization tool 110 may include a chemical mechanical planarization (CMP) tool and / or other types of planarization tools that can grind or planarize layers or surfaces of deposited or plated materials. The planarization tool 110 can combine chemical and mechanical forces (such as chemical etching and abrasive-free grinding) to grind or planarize the surface of the semiconductor device. The planarization tool 110 can use abrasives and corrosive chemical polishing liquids in combination with a polishing pad and a retaining ring (e.g., typically having a diameter larger than the semiconductor device). The polishing pad and the semiconductor device can be pressed together by a powered polishing head and held in place by a retaining ring. The powered polishing head can rotate on different rotation axes to remove material and equalize the irregular surface morphology of the semiconductor device to flatten or planarize the semiconductor device.

[0073] The electroplating tool 112 is a semiconductor processing tool that can electroplate a substrate (e.g., a wafer, a semiconductor device, and / or the like) or a portion thereof with one or more metals. For example, the electroplating tool 112 can include a copper electroplating device, an aluminum electroplating device, a nickel electroplating device, a tin electroplating device, a compound material or alloy (e.g., tin-silver, tin-lead, and / or the like) electroplating device, and / or an electroplating device for one or more other types of conductive materials, metals, and / or similar types of materials.

[0074] The photoresist removal tool 114 is a semiconductor processing tool that can remove the remaining portion of the photoresist layer from the substrate after the etching tool 108 removes the portion of the substrate. For example, the photoresist removal tool 114 can use chemical strippers and / or other techniques to remove the photoresist layer from the substrate.

[0075] The annealing tool 116 is a semiconductor process tool that includes a semiconductor process chamber and one or more devices that can heat a semiconductor substrate or a semiconductor device. For example, the annealing tool 116 may include a rapid thermal annealing (RTA) tool or other type of annealing tool that can heat a semiconductor substrate to cause a reaction between two or more materials or gases or to cause material decomposition. In another specific example, the annealing tool 116 may be configured to heat (e.g., increase or increase its temperature) a structure or layer (or portion thereof) to reflow the structure or layer, or crystallize the structure or layer to remove defects such as pores or seams. In another specific example, the annealing tool 116 may be configured to heat (e.g., increase or increase its temperature) a layer (or portion thereof) to bond two or more semiconductor devices.

[0076] The wafer / die transfer tool 118 may be included in a cluster tool or other type of tool including multiple process chambers, and is configured to transfer substrates and / or semiconductor devices between multiple process chambers, between a process chamber and a buffer area, between a process chamber and an interface tool (e.g., an equipment front end module (EFEM)), and / or between a process chamber and a transport carrier (e.g., a front opening unified pod (FOUP)), among other examples. In some embodiments, the wafer / die transfer tool 118 may be included in a multi-chamber (or cluster) deposition tool 102, which may include a pre-clean process tool (e.g., for cleaning or removing oxides, oxidation, and / or other types of contaminants or byproducts from substrates and / or semiconductor devices) and multiple types of deposition process chambers (e.g., process chambers for depositing different types of materials, process chambers for performing different types of deposition operations).

[0077] In some embodiments, one or more of the semiconductor process tools 102 to the semiconductor process tools 116 and / or the wafer / die transfer tool 118 can perform one or more semiconductor process operations described herein. For example, the semiconductor process tools 102 to the semiconductor process tools 116 and / or the wafer / die transfer tool 118 can form a metal layer on an isolation structure, wherein the isolation structure at least partially surrounds a photodiode, etch a portion of the metal layer to form at least one recess, and / or form at least one dielectric layer on the metal layer, wherein the at least one dielectric layer surrounds an air gap in the metal layer, and other examples.

[0078] Figure 1 The number and arrangement of devices shown are provided as one or more specific examples. In practice, there may be additional devices, fewer devices, different devices, or different Figure 1 The device configuration shown. Furthermore, Figure 1 Two or more of the devices shown may be used in a single device, or Figure 1 The single device shown may be used in a variety of distributed devices. For example, deposition tool 102 may include electroplating tool 112. Additionally or alternatively, one set of devices (e.g., one or more devices) of example environment 100 may perform one or more functions performed by another set of devices of example environment 100.

[0079] Figure 22 is an illustration of an exemplary pixel array 200 (or a portion thereof) described herein. Pixel array 200 may be included in an image sensor, such as a CMOS image sensor, a BSI CMOS image sensor, or another type of image sensor.

[0080] Figure 2 FIG. 2 shows a top view of the pixel array 200. Figure 2 As shown, the pixel array 200 may include a plurality of pixel sensors 202. Figure 2 As shown, the pixel sensors 202 may be arranged in a grid. In some embodiments, the pixel sensors 202 are square (eg, Figure 2 In some embodiments, the pixel sensor 202 includes other shapes, such as a circle, an octagon, a diamond, and / or other shapes.

[0081] Pixel sensor 202 may be configured to sense and / or accumulate incident light (e.g., light directed toward pixel array 200). For example, pixel sensor 202 may absorb and accumulate photons of incident light. Photons accumulated in a photodiode may generate a charge representing the intensity or brightness of the incident light (e.g., a larger amount of charge may correspond to a greater intensity or brightness, while a smaller amount of charge may correspond to a lower intensity or brightness).

[0082] Pixel array 200 may be electrically connected to a back-end-of-line (BEOL) metal stack (not shown) of an image sensor. The BEOL metal stack may electrically connect pixel array 200 to a control circuit that may be used to measure the amount of incident light accumulated in pixel sensor 202 and convert the measured value into an electrical signal.

[0083] As mentioned above, Figure 2 is provided as a specific example. Figure 2 Other specific examples may be different from those described.

[0084] Figure 3A is a schematic diagram of an exemplary pixel array 300 described in the present disclosure. Figure 3A The exemplary pixel array 300 in FIG. 1 may include or may be included in the pixel array 200 (or a portion thereof). In some embodiments, the pixel array 300 may be included in an image sensor. The image sensor may be a CMOS image sensor, a BSI CMOS image sensor, or another type of image sensor.

[0085] like Figure 3AAs shown, pixel array 300 may include a plurality of adjacent pixel sensors, such as pixel sensor 302a, pixel sensor 302b, and pixel sensor 302c. In some embodiments, pixel sensor 302a, pixel sensor 302b, and pixel sensor 302c are configured as square pixel sensors 202 included in pixel array 200. In some embodiments, pixel sensor 302a, pixel sensor 302b, and pixel sensor 302c are configured as octagonal pixel sensors and / or square pixel sensors. In some embodiments, pixel sensor 302a, pixel sensor 302b, and pixel sensor 302c include additional or other shapes of pixel sensors or combinations thereof.

[0086] Pixel sensors 302a, 302b, and 302c may be formed in a substrate 304, wherein substrate 304 may include a semiconductor die substrate, a semiconductor wafer, or other types of substrates in which semiconductor pixels may be formed. In some embodiments, substrate 304 is made of silicon (Si), materials including silicon, III-V compound semiconductor materials such as gallium arsenide (GaAs), silicon on insulator (SOI), or other types of semiconductor materials that can generate charges from incident light photons.

[0087] Each of pixel sensor 302a, pixel sensor 302b, and pixel sensor 302c may include a photodiode 306. Photodiode 306 may include a region of substrate 304 doped with various types of ions to form a pn junction or a PIN junction (e.g., a junction between a p-type portion, an intrinsic (or undoped) portion, and an n-type portion). For example, substrate 304 is doped with an n-type dopant to form a first portion (e.g., an n-type portion) of photodiode 306, and is doped with a p-type dopant to form a second portion (e.g., a p-type portion) of photodiode 306. Photodiode 306 is configured to absorb photons of incident light. The absorption of photons causes photodiode 306 to accumulate charge (referred to as a photocurrent) due to the photoelectric effect. Thereby, photons strike photodiode 306, which causes photodiode 306 to emit electrons. The emission of electrons causes the generation of electron-hole pairs, wherein the electrons migrate toward the cathode of photodiode 306 and the holes migrate toward the anode, thereby generating a photocurrent.

[0088] Isolation structures 308 may be included in substrate 304 between adjacent pixel sensors 302a-302c. Isolation structures 308 may provide optical isolation by blocking or preventing light from diffusing or escaping from one of pixel sensors 302a-302c to another of pixel sensors 302a-302c, thereby reducing crosstalk between adjacent pixel sensors 302a-302c. Isolation structures 308 may include trenches or deep trench isolation (DTI) structures covered or laid with antireflective coating (ARC) 310 and filled with a dielectric layer (e.g., on antireflective coating 310). Isolation structures 308 may be formed in a grid layout, where isolation structures 308 extend around pixel sensors 302a-302c in pixel array 300 and are staggered in each position of pixel array 300. In some embodiments, the isolation structure 308 is formed on the back side of the substrate 304 to provide optical isolation between the pixel sensors 302 a and 302 c , and is thus referred to as a backside deep trench isolation (BDTI) structure.

[0089] An anti-reflective coating 310 may be included in the isolation structure 308 and on the substrate 304 above the photodiode 306. The anti-reflective coating 310 may include a suitable material to reduce reflection of incident light projected toward the photodiode 306. For example, the anti-reflective coating 310 may include a nitrogen-containing material.

[0090] The dielectric layer 312 may serve as a dielectric buffer layer between the photodiode 306 and the layers above the photodiode 306. The dielectric layer 312 may include an oxide material, such as silicon oxide (SiO x ) (such as silicon dioxide (SiO2)), silicon nitride (SiN x ), Silicon Carbide (SiC x ), titanium nitride (TiN x ), Tantalum Nitride (TaN x ), hafnium oxide (HfO x ), tantalum oxide (TaO x ) or aluminum oxide (AlO x ) or other dielectric materials that can provide optical isolation between pixel sensors 302a to 302c.

[0091] Metal layer 314 may be included on and / or over dielectric layer 312. Metal layer 314 may include a metallization material such as tungsten (W), copper (Cu), aluminum (Al), cobalt (Co), nickel (Ni), titanium (Ti), tantalum (Ta), other conductive materials, and / or alloys including one or more of the foregoing. Metal layer 314 may be etched such that a mesh structure 316 is formed between pixel sensors 302a-302c and over isolation structure 308. Mesh structure 316 may include a plurality of interconnecting posts of metal layer 314. Mesh structure 316 may surround pixel sensors 302a-302c and may be configured to provide additional crosstalk reduction and / or mitigation in conjunction with isolation structure 308.

[0092] To further reduce the crosstalk between the adjacent pixel sensors 302a to 302c, a dielectric layer 318 may be included in the mesh structure 316. The dielectric layer 318 may include an oxide material, such as silicon oxide (SiO x ) (such as silicon dioxide (SiO2)), silicon nitride (SiN x ), Silicon Carbide (SiC x ), titanium nitride (TiN x ), Tantalum Nitride (TaN x ), hafnium oxide (HfO x ), tantalum oxide (TaO x ) or aluminum oxide (AlO x ) or other dielectric materials that can provide optical isolation between pixel sensors 302a and 302c. Metal layer 314 and dielectric layer 318 can form a hybrid shielding structure of mesh structure 316.

[0093] The hybrid shield structure may include an air gap 320 enclosed in the metal layer 314 (and optionally in the dielectric layer 312 supporting the metal layer 314). For example, a groove may be etched into the metal layer 314 so that the air gap 320 is enclosed when the dielectric layer 318 is formed on the metal layer 314. Since the refractive index of air is very low (approximately less than 1.0001, which is very close to the refractive index of a vacuum defined as 1), incident light is likely to experience total reflection from the air gap 320, as shown in FIG. Figure 3A Therefore, the air gap 320 reduces photon loss, thereby increasing the quantum efficiency and signal-to-noise ratio of the pixel sensors 302a to 302c. In addition, the air gap 320 further reduces the crosstalk between the adjacent pixel sensors 302a to 302c.

[0094] In some embodiments, an oxide material may be formed on the surface of the air gap 320. For example, as shown in FIG. Figure 4FAs described above, when the dielectric layer 318 is formed on the metal layer 314, the air gap 320 may be closed. However, during the formation of the dielectric layer 318, some oxide material may be formed on one or more surfaces of the air gap 320, such as the exposed surface of the metal layer 314 and / or the exposed surface of the dielectric layer 312. In addition or in the alternative, the precursor material and / or the carrier gas used to form the dielectric layer 318 may remain enclosed in the air gap 320. Since the air gap 320 remains enclosed after the dielectric layer 318 is formed, the oxide material may remain (at least in trace amounts) on the surface of the air gap 320. As used herein, "trace amounts" means an amount less than 50% of the surface area.

[0095] The passivation layer 322 may be included on the mesh structure 316, on the hybrid shield structure, and on portions of the dielectric layer 312 not covered by the hybrid shield structure. The passivation layer 322 may include an oxide material to provide protection to layers below the passivation layer 322 from layers and structures formed on the passivation layer 322.

[0096] Color filter regions 324a to 324c may be included in the regions between mesh structures 316 and on passivation layer 322. For example, color filter region 324a is formed between mesh structures 316 on photodiode 306 of pixel sensor 302a, color filter region 324b is formed between mesh structures 316 on photodiode 306 of pixel sensor 302b, color filter region 324c is formed between mesh structures 316 on photodiode 306 of pixel sensor 302c, etc. In addition, the regions between mesh structures 316 may be completely filled with passivation layer 322, and the color filter layer including color filter region 324a may be formed on mesh structures 316 on passivation layer 322.

[0097] Each of the color filter regions 324a to 324c may be configured to filter incident light so that incident light of a specific wavelength passes through the photodiode 306 of the associated pixel sensor 302a to 302c. For example, the color filter region 324a included in the pixel sensor 302a may filter red light of the pixel sensor 302a (thus, the pixel sensor 302a may be a red pixel sensor), the color filter region 324b included in the pixel sensor 302b may filter green light of the pixel sensor 302b (thus, the pixel sensor 302b may be a green pixel sensor), the color filter region 324c included in the pixel sensor 302c may filter blue light of the pixel sensor 302c (thus, the pixel sensor 302c may be a blue pixel sensor), and so on.

[0098] The blue filter region allows incident light components with a wavelength of about 450 nanometers to pass through the color filter region 324a to the color filter region 324c, and blocks other wavelengths from passing through. The green filter region allows incident light components with a wavelength of about 550 nanometers to pass through the color filter region 324a to the color filter region 324c, and blocks other wavelengths from passing through. The red filter region allows incident light components with a wavelength of about 650 nanometers to pass through the color filter region 324a to the color filter region 324c, and blocks other wavelengths from passing through. The yellow filter region allows incident light components with a wavelength of about 580 nanometers to pass through the color filter region 324a to the color filter region 324c, and blocks other wavelengths from passing through.

[0099] In some embodiments, the color filter regions 324a-324c may be indifferent or non-filtering, which may define a white pixel sensor. The indifferent or non-filtering color filter regions 324a-324c may include a material that allows all wavelengths of light to pass into the associated photodiode 306 (e.g., to determine overall brightness to increase the light sensitivity of the image sensor). In some embodiments, the color filter regions 324a-324c may be near infrared (NIR) bandpass color filter regions, which may define an NIR pixel sensor. The NIR bandpass color filter regions 324a-324c may include a material that allows a portion of incident light in the near infrared wavelength range to pass through the associated photodiode 306 while blocking visible light from passing through.

[0100] Microlens layer 326 may be included on and / or over color filter regions 324a-324c. Microlens layer 326 may include a respective microlens for each of pixel sensors 302a-302c. For example, a microlens is formed to focus incident light toward photodiode 306 of pixel sensor 302a, another microlens is formed to focus incident light toward photodiode 306 of pixel sensor 302b, another microlens is formed to focus incident light toward photodiode 306 of pixel sensor 302c, and so on.

[0101] Figure 3B is a schematic diagram of an exemplary pixel array 330 described in the present disclosure. Figure 3B The exemplary pixel array 330 in FIG. 1 may include or may be included in the pixel array 200 (or a portion thereof). In some embodiments, the pixel array 330 may be included in an image sensor. The image sensor may be a CMOS image sensor, a BSI CMOS image sensor, or another type of image sensor.

[0102] Figure 3B The exemplary pixel array 330 is similar to Figure 3A 300. The air gap 320 in the exemplary pixel array 330 extends into the dielectric layer 318. For example, after the dielectric layer 318 is deposited, the air gap 320 can be reopened by etching, and when the dielectric layer 332 is formed on the dielectric layer 318, the air gap 320 is surrounded. The dielectric layer 332 can include an oxide material, such as silicon oxide (SiO x ) (such as silicon dioxide (SiO2)), silicon nitride (SiN x ), Silicon Carbide (SiC x ), titanium nitride (TiN x ), Tantalum Nitride (TaN x ), hafnium oxide (HfO x ), tantalum oxide (TaO x ) or aluminum oxide (AlO x ) or other dielectric materials that can provide optical isolation between pixel sensors 302a and 302c. Therefore, metal layer 314, dielectric layer 318, and dielectric layer 332 can form a hybrid shielding structure of mesh structure 316.

[0103] Since the refractive index of air is very low (approximately less than 1.0001, which is very close to the refractive index of a vacuum being defined as 1), the incident light is likely to undergo total reflection at air gap 320. Since air gap 320 extends into dielectric layer 318, more photons undergo total reflection, which further reduces photon loss and thus increases the quantum efficiency and signal-to-noise ratio of pixel sensors 302a to 302c.

[0104] In some embodiments, an oxide material may be formed on the surface of the air gap 320. For example, as shown in FIG. Figure 5C As described above, air gap 320 may be closed when dielectric layer 332 is formed on dielectric layer 318. However, during the formation of dielectric layer 332, some oxide material may be formed on one or more surfaces of air gap 320, such as an exposed surface of dielectric layer 318, an exposed surface of metal layer 314, and / or an exposed surface of dielectric layer 312. Additionally or alternatively, the precursor material and / or carrier gas used to form dielectric layer 332 may remain enclosed in air gap 320. Since air gap 320 remains enclosed after dielectric layer 332 is formed, oxide material may remain (at least in trace amounts) on the surface of air gap 320.

[0105] Figure 3C is a schematic diagram of an exemplary pixel array 350 described in the present disclosure. Figure 3CThe exemplary pixel array 350 in FIG. 1 may include or may be included in the pixel array 200 (or a portion thereof). In some embodiments, the pixel array 350 may be included in an image sensor. The image sensor may be a CMOS image sensor, a BSI CMOS image sensor, or another type of image sensor.

[0106] Figure 3C The exemplary pixel array 350 is similar to Figure 3A 300 of the exemplary pixel array 350. The air gap 320 in the exemplary pixel array 350 extends into the isolation structure 308. For example, an etch stop layer (ESL) 352 allows the recess to be etched below the metal layer 314 and into the isolation structure 308 without extending below the isolation structure 308. The etch stop layer includes a material that is resistant (or at least partially resistant) to a particular type of dry etching and / or wet etching. The etch stop layer may include a material that is resistant to an etchant that may otherwise be used to etch other layers near the etch stop layer. Selecting this material provides etching selectivity and may allow the etch stop layer to remain unetched (or mostly unetched) while other layers are etched. For example, the etch stop layer 352 may include a nitride (e.g., aluminum nitride (AlN) and / or silicon nitride (SiN)) and / or an oxide (e.g., silicon oxynitride (SiO x N y ), aluminum oxynitride (AlON) and / or silicon oxide (SiO x )). In some embodiments, the etch stop layer 352 includes a plurality of etch stop layers stacked together and configured to serve as a single etch stop layer.

[0107] Since the refractive index of air is very low (approximately less than 1.0001, which is very close to the refractive index of a vacuum being defined as 1), the incident light is likely to undergo total reflection at the air gap 320. Since the air gap 320 extends into the isolation structure 308, more photons undergo total reflection, which further reduces photon loss and thus increases the quantum efficiency and signal-to-noise ratio of the pixel sensors 302a to 302c.

[0108] In some embodiments, an oxide material may be formed on the surface of the air gap 320. For example, as shown in FIG. Fig. 6FAs described above, air gap 320 may be closed when dielectric layer 318 is formed on metal layer 314. However, during the formation of dielectric layer 318, some oxide material may be formed on one or more surfaces of air gap 320, such as exposed surfaces of metal layer 314, exposed surfaces of dielectric layer 312, and / or exposed surfaces of isolation structure 308. Additionally or alternatively, the precursor material and / or carrier gas used to form dielectric layer 318 may remain enclosed in air gap 320. Since air gap 320 remains enclosed after dielectric layer 318 is formed, oxide material may remain (at least in trace amounts) on the surface of air gap 320.

[0109] Figure 3D is a schematic diagram of an exemplary pixel array 370 described in the present disclosure. Figure 3D The exemplary pixel array 370 in FIG. 1 may include or may be included in the pixel array 200 (or a portion thereof). In some embodiments, the pixel array 370 may be included in an image sensor. The image sensor may be a CMOS image sensor, a BSI CMOS image sensor, or another type of image sensor.

[0110] Figure 3D The exemplary pixel array 370 is similar to Figure 3A 300 of the exemplary pixel array 370. The air gap 320 in the exemplary pixel array 370 extends into the isolation structure 308. For example, the etch stop layer 352 allows the recess to be etched below the metal layer 314 and into the isolation structure 308 without extending below the isolation structure 308.

[0111] In addition, the air gap 320 in the exemplary pixel array 370 extends into the dielectric layer 318. For example, after the dielectric layer 318 is deposited, the air gap 320 can be reopened by etching, and when the dielectric layer 332 is formed on the dielectric layer 318, the air gap 320 is surrounded. Therefore, the metal layer 314, the dielectric layer 318, and the dielectric layer 332 can form a hybrid shielding structure of the mesh structure 316.

[0112] Since the refractive index of air is very low (approximately less than 1.0001, which is very close to the refractive index of a vacuum being defined as 1), the incident light is likely to undergo total reflection at air gap 320. Since air gap 320 extends into isolation structure 308 and into dielectric layer 332, more photons undergo total reflection, which further reduces photon losses and thereby increases the quantum efficiency and signal-to-noise ratio of pixel sensors 302a to 302c.

[0113] In some embodiments, an oxide material may be formed on the surface of the air gap 320. For example, as shown in FIG. Figure 7CAs described above, air gap 320 may be closed when dielectric layer 332 is formed on dielectric layer 318. However, during the formation of dielectric layer 332, some oxide material may be formed on one or more surfaces of air gap 320, such as an exposed surface of dielectric layer 318, an exposed surface of metal layer 314, an exposed surface of dielectric layer 312, and / or an exposed surface of isolation structure 308. Additionally or alternatively, the precursor material and / or carrier gas used to form dielectric layer 332 may remain enclosed in air gap 320. Since air gap 320 remains enclosed after dielectric layer 332 is formed, oxide material may remain (at least in trace amounts) on the surface of air gap 320.

[0114] As mentioned above, FIG. 3A to FIG. 3D is provided as a specific example. FIG. 3A to FIG. 3D Other specific examples may be different from those described.

[0115] 4A to 4F is a schematic diagram of an exemplary embodiment 400 of the present disclosure. Exemplary embodiment 400 may be an exemplary process for forming an exemplary pixel array 300 having air gaps in a metal layer of a hybrid shield structure. The exemplary pixel array formed using exemplary embodiment 400 may be included in a CMOS image sensor, a BSI CMOS image sensor, or other types of image sensors.

[0116] like Figure 4A , an exemplary process for forming a pixel array may be performed with respect to a substrate 304. As described above, the substrate 304 may include a semiconductor die substrate, a semiconductor wafer, a stacked semiconductor wafer, or other types of substrates in which semiconductor pixels may be formed. For example, the substrate 304 is made of silicon (Si), a material including silicon, a III-V compound semiconductor material (e.g., gallium arsenide (GaAs)), silicon on insulator (SOI), or other types of semiconductor materials that can generate charge from incident light photons. In some embodiments, the substrate 304 is composed of a doped material (e.g., a p-doped material or an n-doped material) such as doped silicon.

[0117] In addition, the substrate 304 may have a photodiode 306 formed therein. Figure 4A As shown, an isolation structure 308 (e.g., a deep trench isolation structure) may be included in the substrate 304 and at least partially surround the photodiode 306. The isolation structure 308 may cover or lay an anti-reflective coating 310 and fill a dielectric layer (e.g., on the anti-reflective coating 310). In addition or alternatively, the anti-reflective coating 310 may include a high dielectric constant material. Specific examples of high dielectric constant dielectric materials that can be used in the anti-reflective coating 310 may include high dielectric constant metal oxides, such as hafnium oxide (HfOx ), aluminum oxide (Al x O y )、ZrO x ), magnesium oxide (MgO x ), yttrium oxide (Y x O y ), Tantalum Oxide (Ta x O y ), titanium oxide (TiO x ), lanthanum oxide (La x O y ), barium oxide (BaO x ) or other types of high dielectric constant metal oxides. The substrate 304 may be supported by an etch stop layer 402 to prevent over-etching of the substrate 304 during the formation of the isolation structure 308.

[0118] like Figure 4B As shown, dielectric layer 312 may be formed on isolation structure 308. For example, deposition tool 102 may form dielectric layer 312 on and / or over the front surface of substrate 304 (e.g., on a dielectric layer filling isolation structure 308). In some embodiments, deposition tool 102 may form dielectric layer 312 using spin coating technology, chemical vapor deposition technology, physical vapor deposition technology, atomic layer deposition technology, and / or other deposition technology.

[0119] like Figure 4C As shown, buffer layer 404 may be formed on dielectric layer 312. For example, deposition tool 102 may form buffer layer 404 on and / or over the front surface of substrate 304 (e.g., on dielectric layer 312). In some embodiments, deposition tool 102 may form buffer layer 404 using spin coating, chemical vapor deposition, physical vapor deposition, atomic layer deposition, and / or other deposition techniques.

[0120] The buffer layer 404 may include a dielectric material to provide protection to the layers below the buffer layer 404 from the layers and structures formed on the buffer layer 404. In addition or alternatively, the buffer layer 404 may be formed with a dielectric material used to deposit the metal layer 314 (e.g., see Figure 4D Therefore, the buffer layer 404 can provide a surface for forming the metal layer 314.

[0121] like Figure 4DAs shown, metal layer 314 may be formed on buffer layer 404. For example, deposition tool 102 may form metal layer 314 on and / or over the front surface of substrate 304 (e.g., on buffer layer 404). In some embodiments, deposition tool 102 may form metal layer 314 using spin coating, chemical vapor deposition, physical vapor deposition, atomic layer deposition, and / or other deposition techniques.

[0122] In some embodiments, the metal layer 314 may be formed on the entire dielectric layer 312. Figure 4E As shown, a portion of metal layer 314 is removed. For example, deposition tool 102 may form a photoresist layer on and / or over the front side surface of metal layer 314, exposure tool 104 may expose the photoresist layer to a radiation source to form a pattern on the photoresist layer, and development tool 106 may develop and remove a portion of the photoresist layer to expose the pattern. Thus, etching tool 108 may etch a portion of metal layer 314 formed on photodiode 306, but not a portion of metal layer 314 on isolation structure 308. For example, etching tool 108 may use a wet etching technique, a dry etching technique, a plasma assisted etching technique, and / or other types of etching techniques to etch a portion of metal layer 314. After etching tool 108 patterns metal layer 314, photoresist removal tool 114 may remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or other techniques).

[0123] Further Figure 4E As shown, in addition to removing the portion of metal layer 314 formed on photodiode 306, etching tool 108 can form recess 406 in the portion of metal layer 314 on isolation structure 308. In some embodiments, the pattern exposed by developing tool 106 can also cause etching tool 108 to form recess 406. In addition, etching tool 108 can form recess 406 in a variety of etching processes, such as a wet etching process, a dry etching process, a plasma-assisted etching process, and / or other types of etching processes. Further, as shown in FIG. Figure 4E As shown, the recess 406 may extend into the buffer layer 404 and / or the dielectric layer 312. For example, when forming the recess 406, the etching tool 108 may etch portions of the buffer layer 404 and / or the dielectric layer 312.

[0124] like Figure 4F As shown, dielectric layer 318 may be formed on metal layer 314. For example, deposition tool 102 may form dielectric layer 318 on and / or over the front surface of substrate 304 (e.g., on metal layer 314). In some embodiments, deposition tool 102 may form dielectric layer 318 using spin coating techniques, chemical vapor deposition techniques, physical vapor deposition techniques, atomic layer deposition techniques, and / or other deposition techniques.

[0125] In some embodiments, the deposition tool 102 may utilize a precursor material that selectively bonds to metal to form the dielectric layer 318. Thus, the precursor material may be selected to adhere to the metal layer 314 and not to the dielectric layer 312. Additionally or alternatively, the etching tool 108 may remove portions of the dielectric layer 318 formed on the dielectric layer 312. The dielectric layer 318 is formed such that the recess 406 is closed and the air gap 320 is enclosed in the metal layer 314. Thus, the carrier gas used to form the dielectric layer 318 (and any ambient gas present in the deposition tool 102) is enclosed in the air gap 320.

[0126] The air gap 320 may further include a precursor material (and / or a dielectric material) on a surface of the air gap 320. For example, during the formation of the dielectric layer 318, some precursor material may be deposited and / or some dielectric material may be formed on one or more surfaces of the air gap 320, such as an exposed surface of the metal layer 314, an exposed surface of the buffer layer 404, and / or an exposed surface of the dielectric layer 312.

[0127] Since the refractive index of air is very low (approximately less than 1.0001, which is very close to the refractive index of 1 defined for a vacuum), incident light is likely to undergo total reflection from air gap 320. Therefore, air gap 320 reduces photon loss and thus increases the quantum efficiency and signal-to-noise ratio of the pixel sensor including photodiode 306.

[0128] In addition, deposition tool 102 may form a passivation layer (not shown) on dielectric layer 318 and on exposed portions of dielectric layer 312. For example, deposition tool 102 may form the passivation layer on and / or over the front surface of substrate 304. In some embodiments, deposition tool 102 may form the passivation layer using spin coating, chemical vapor deposition, physical vapor deposition, atomic layer deposition, and / or other deposition techniques.

[0129] As mentioned above, 4A to 4F is provided as a specific example. 4A to 4F Other specific examples may be different from those described.

[0130] FIG. 5A to FIG. 5C is a schematic diagram of an exemplary embodiment 500 of the present disclosure. Exemplary embodiment 500 may be an exemplary process for forming an exemplary pixel array 330 having air gaps in a metal layer of a hybrid shield structure and a dielectric layer of a hybrid shield structure. The exemplary pixel array formed using exemplary embodiment 500 may be included in a CMOS image sensor, a BSICMOS image sensor, or other types of image sensors.

[0131] like Figure 5AAs shown, the exemplary embodiment 500 may include reference 4A to 4F The process described. Figure 5B As shown, portions of dielectric layer 318 may be removed. For example, deposition tool 102 may form a photoresist layer on and / or over the front surface of dielectric layer 318, exposure tool 104 may expose the photoresist layer to a radiation source to form a pattern on the photoresist layer, and development tool 106 may develop and remove portions of the photoresist layer to expose the pattern. Thus, etching tool 108 may etch portions of dielectric layer 318 on isolation structure 308, such as Figure 5B For example, the etching tool 108 may use a wet etching technique, a dry etching technique, a plasma-assisted etching technique, and / or other types of etching techniques to etch portions of the dielectric layer 318. After the etching tool 108 patterns the dielectric layer 318, the photoresist removal tool 114 may remove the remaining portions of the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or other techniques).

[0132] Therefore, the etching tool 108 can again expose the air gap 320, such as Figure 5B As shown. Figure 5C As shown, dielectric layer 332 may be formed on dielectric layer 318. For example, deposition tool 102 may form dielectric layer 332 on and / or over the front surface of substrate 304 (e.g., on dielectric layer 318). In some embodiments, deposition tool 102 may form dielectric layer 332 using spin coating techniques, chemical vapor deposition techniques, physical vapor deposition techniques, atomic layer deposition techniques, and / or other deposition techniques.

[0133] In some embodiments, the deposition tool 102 may form the dielectric layer 332 using a precursor material that selectively bonds to the dielectric layer 318. Thus, the precursor material may selectively bond to the dielectric layer 318 and not bond to the metal layer 314. Additionally or alternatively, the etching tool 108 may remove portions of the dielectric layer 332 that are formed on the metal layer 314 and / or the dielectric layer 312. The dielectric layer 332 is formed such that the air gap 320 is closed again and is within the dielectric layer 318 and the metal layer 314. Thus, the carrier gas used to form the dielectric layer 332 (and any ambient gas present in the deposition tool 102) is confined within the air gap 320.

[0134] The air gap 320 may further include a precursor material (and / or a dielectric material) on a surface of the air gap 320. For example, during the formation of the dielectric layer 332, some precursor material may be deposited and / or some dielectric material may be formed on one or more surfaces of the air gap 320, such as an exposed surface of the dielectric layer 318, an exposed surface of the metal layer 314, an exposed surface of the buffer layer 404, and / or an exposed surface of the dielectric layer 312.

[0135] Since the air gap 320 extends into the dielectric layer 318 and the metal layer 314, the incident light may experience total reflection from the air gap 320 rather than passing through the dielectric layer 318 and into the adjacent photodiode. Therefore, the air gap 320 reduces crosstalk.

[0136] In addition, deposition tool 102 may form a passivation layer (not shown) on dielectric layer 332 and on exposed portions of dielectric layer 312. For example, deposition tool 102 may form the passivation layer on and / or over the front surface of substrate 304. In some embodiments, deposition tool 102 may form the passivation layer using spin coating, chemical vapor deposition, physical vapor deposition, atomic layer deposition, and / or other deposition techniques.

[0137] As mentioned above, FIG. 5A to FIG. 5C is provided as a specific example. FIG. 5A to FIG. 5C Other specific examples may be different from those described.

[0138] 6A to 6F is a schematic diagram of an exemplary embodiment 600 described in the present disclosure. Exemplary embodiment 600 can be an exemplary process for forming an exemplary pixel array 350 having an air gap in an isolation structure around a photodiode and in a metal layer of a hybrid shielding structure. The exemplary pixel array formed using exemplary embodiment 600 can be included in a CMOS image sensor, a BSI CMOS image sensor, or other types of image sensors.

[0139] like Fig. 6A , an exemplary process for forming a pixel array may be performed with respect to a substrate 304. As described above, the substrate 304 may include a semiconductor die substrate, a semiconductor wafer, a stacked semiconductor wafer, or other types of substrates in which semiconductor pixels may be formed. For example, the substrate 304 is made of silicon (Si), a material including silicon, a III-V compound semiconductor material (e.g., gallium arsenide (GaAs)), silicon on insulator (SOI), or other types of semiconductor materials that can generate charge from incident light photons. In some embodiments, the substrate 304 is composed of a doped material (e.g., a p-doped material or an n-doped material) such as doped silicon.

[0140] In addition, the substrate 304 may have a photodiode 306 formed therein. Fig. 6AAs shown, an isolation structure 308 (e.g., a deep trench isolation structure) may be included in the substrate 304 and at least partially surround the photodiode 306. The isolation structure 308 may be covered or covered with an anti-reflective coating 310 and filled with a dielectric layer (e.g., on the anti-reflective coating 310). The isolation structure 308 may include an etch stop layer 352 to prevent over-etching of the dielectric layer filling the isolation structure 308. Similarly, the substrate 304 may be supported by an etch stop layer 402 to prevent over-etching of the substrate 304 during the formation of the isolation structure 308.

[0141] like Figure 6B As shown, dielectric layer 312 may be formed on isolation structure 308. For example, deposition tool 102 may form dielectric layer 312 on and / or over the front surface of substrate 304 (e.g., on a dielectric layer filling isolation structure 308). In some embodiments, deposition tool 102 may form dielectric layer 312 using spin coating technology, chemical vapor deposition technology, physical vapor deposition technology, atomic layer deposition technology, and / or other deposition technology.

[0142] like Figure 6C As shown, buffer layer 404 may be formed on dielectric layer 312. For example, deposition tool 102 may form buffer layer 404 on and / or over the front surface of substrate 304 (e.g., on dielectric layer 312). In some embodiments, deposition tool 102 may form buffer layer 404 using spin coating, chemical vapor deposition, physical vapor deposition, atomic layer deposition, and / or other deposition techniques.

[0143] The buffer layer 404 may include a dielectric material to provide protection to the layers below the buffer layer 404 from the layers and structures formed on the buffer layer 404. In addition or alternatively, the buffer layer 404 may be formed with a dielectric material used to deposit the metal layer 314 (e.g., see Fig.6D Therefore, the buffer layer 404 can provide a surface for forming the metal layer 314.

[0144] like Fig.6D As shown, metal layer 314 may be formed on buffer layer 404. For example, deposition tool 102 may form metal layer 314 on and / or over the front surface of substrate 304 (e.g., on buffer layer 404). In some embodiments, deposition tool 102 may form metal layer 314 using spin coating, chemical vapor deposition, physical vapor deposition, atomic layer deposition, and / or other deposition techniques.

[0145] In some embodiments, the metal layer 314 may be formed on the entire dielectric layer 312. Fig. 6EAs shown, a portion of metal layer 314 is removed. For example, deposition tool 102 may form a photoresist layer on and / or over the front side surface of metal layer 314, exposure tool 104 may expose the photoresist layer to a radiation source to form a pattern on the photoresist layer, and development tool 106 may develop and remove a portion of the photoresist layer to expose the pattern. Thus, etching tool 108 may etch a portion of metal layer 314 formed on photodiode 306, but not a portion of metal layer 314 on isolation structure 308. For example, etching tool 108 may use a wet etching technique, a dry etching technique, a plasma assisted etching technique, and / or other types of etching techniques to etch a portion of metal layer 314. After etching tool 108 patterns metal layer 314, photoresist removal tool 114 may remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or other techniques).

[0146] Further Fig. 6E As shown, in addition to removing the portion of metal layer 314 formed on photodiode 306, etching tool 108 can form recess 406 in the portion of metal layer 314 on isolation structure 308. In some embodiments, the pattern exposed by developing tool 106 can also cause etching tool 108 to form recess 406. In addition, etching tool 108 can form recess 406 in a variety of etching processes, such as a wet etching process, a dry etching process, a plasma-assisted etching process, and / or other types of etching processes. Further, as shown in FIG. Fig. 6E As shown, the recess 406 can extend into the isolation structure 308. For example, when forming the recess 406, the etching tool 108 can etch a portion of the isolation structure 308. In addition, the etching tool 108 can expand the recess 406 into the isolation structure 308 in a separate etching process, such as a wet etching process, a dry etching process, a plasma-assisted etching process, and / or other types of etching processes.

[0147] like Fig. 6F As shown, dielectric layer 318 may be formed on metal layer 314. For example, deposition tool 102 may form dielectric layer 318 on and / or over the front surface of substrate 304 (e.g., on metal layer 314). In some embodiments, deposition tool 102 may form dielectric layer 318 using spin coating techniques, chemical vapor deposition techniques, physical vapor deposition techniques, atomic layer deposition techniques, and / or other deposition techniques.

[0148] In some embodiments, the deposition tool 102 may utilize a precursor material that selectively bonds to metal to form the dielectric layer 318. Thus, the precursor material may be selected to adhere to the metal layer 314 and not to the dielectric layer 312. Additionally or alternatively, the etching tool 108 may remove portions of the dielectric layer 318 formed on the dielectric layer 312. The dielectric layer 318 is formed such that the recess 406 is closed and the air gap 320 is enclosed in the metal layer 314. Thus, the carrier gas used to form the dielectric layer 318 (and any ambient gas present in the deposition tool 102) is enclosed in the air gap 320.

[0149] The air gap 320 may further include a precursor material (and / or a dielectric material) on a surface of the air gap 320. For example, during the formation of the dielectric layer 318, some precursor material may be deposited and / or some dielectric material may be formed on one or more surfaces of the air gap 320, such as an exposed surface of the metal layer 314, an exposed surface of the buffer layer 404, an exposed surface of the dielectric layer 312, and / or an exposed surface of the isolation structure 308.

[0150] Since the air gap 320 extends into the isolation structure 308 and the metal layer 314, the incident light may experience total reflection from the air gap 320 rather than passing through the isolation structure 308 and into the adjacent photodiode. Therefore, the air gap 320 reduces crosstalk.

[0151] In addition, deposition tool 102 may form a passivation layer (not shown) on dielectric layer 318 and on exposed portions of dielectric layer 312. For example, deposition tool 102 may form the passivation layer on and / or over the front surface of substrate 304. In some embodiments, deposition tool 102 may form the passivation layer using spin coating, chemical vapor deposition, physical vapor deposition, atomic layer deposition, and / or other deposition techniques.

[0152] As mentioned above, 6A to 6F is provided as a specific example. 6A to 6F Other specific examples may be different from those described.

[0153] FIG. 7A to FIG. 7C is a schematic diagram illustrating an exemplary embodiment 700 of the present disclosure. Exemplary embodiment 700 may be an exemplary process for forming an exemplary pixel array 370 having air gaps in an isolation structure around a photodiode, in a metal layer of a hybrid shield structure, and in a dielectric layer of a hybrid shield structure. The exemplary pixel array formed using exemplary embodiment 700 may be included in a CMOS image sensor, a BSI CMOS image sensor, or other types of image sensors.

[0154] like Fig. 7A As shown, the exemplary embodiment 700 may include reference 6A to 6F The process described. Figure 7B As shown, portions of dielectric layer 318 may be removed. For example, deposition tool 102 may form a photoresist layer on and / or over the front surface of dielectric layer 318, exposure tool 104 may expose the photoresist layer to a radiation source to form a pattern on the photoresist layer, and development tool 106 may develop and remove portions of the photoresist layer to expose the pattern. Thus, etching tool 108 may etch portions of dielectric layer 318 on isolation structure 308, such as Figure 7B For example, the etching tool 108 may use a wet etching technique, a dry etching technique, a plasma-assisted etching technique, and / or other types of etching techniques to etch portions of the dielectric layer 318. After the etching tool 108 patterns the dielectric layer 318, the photoresist removal tool 114 may remove the remaining portions of the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or other techniques).

[0155] Therefore, the etching tool 108 can again expose the air gap 320, such as Figure 7B As shown. Figure 7C As shown, dielectric layer 332 may be formed on dielectric layer 318. For example, deposition tool 102 may form dielectric layer 332 on and / or over the front surface of substrate 304 (e.g., on dielectric layer 318). In some embodiments, deposition tool 102 may form dielectric layer 332 using spin coating techniques, chemical vapor deposition techniques, physical vapor deposition techniques, atomic layer deposition techniques, and / or other deposition techniques.

[0156] In some embodiments, the deposition tool 102 may form the dielectric layer 332 using a precursor material that selectively bonds to the dielectric layer 318. Thus, the precursor material may selectively bond to the dielectric layer 318 and not bond to the metal layer 314. Additionally or alternatively, the etching tool 108 may remove portions of the dielectric layer 332 that are formed on the metal layer 314 and / or the dielectric layer 312. The dielectric layer 332 is formed such that the air gap 320 is closed again and is within the dielectric layer 318 and the metal layer 314. Thus, the carrier gas used to form the dielectric layer 332 (and any ambient gas present in the deposition tool 102) is confined within the air gap 320.

[0157] The air gap 320 may further include a precursor material (and / or a dielectric material) on a surface of the air gap 320. For example, during the formation of the dielectric layer 332, some precursor material may be deposited and / or some dielectric material may be formed on one or more surfaces of the air gap 320, such as an exposed surface of the dielectric layer 318, an exposed surface of the metal layer 314, an exposed surface of the buffer layer 404, an exposed surface of the dielectric layer 312, and / or an exposed surface of the isolation structure 308.

[0158] Since air gap 320 extends into isolation structure 308, dielectric layer 318, and metal layer 314, incident light may experience total reflection from air gap 320 rather than passing through dielectric layer 318 and into an adjacent photodiode. Thus, air gap 320 reduces crosstalk.

[0159] In addition, deposition tool 102 may form a passivation layer (not shown) on dielectric layer 332 and on exposed portions of dielectric layer 312. For example, deposition tool 102 may form the passivation layer on and / or over the front surface of substrate 304. In some embodiments, deposition tool 102 may form the passivation layer using spin coating, chemical vapor deposition, physical vapor deposition, atomic layer deposition, and / or other deposition techniques.

[0160] As mentioned above, FIG. 7A to FIG. 7C is provided as a specific example. FIG. 7A to FIG. 7C Other specific examples may be different from those described.

[0161] Figure 8 8 is a schematic diagram illustrating exemplary components of the apparatus 800 described herein. In some embodiments, one or more of the semiconductor process tool 102 to the semiconductor process tool 116 and / or the wafer / die transfer tool 118 may include one or more apparatuses 800 and / or one or more components of the apparatus 800. Figure 8 As shown, device 800 may include a bus 810 , a processor 820 , a memory 830 , an input component 840 , an output component 850 , and / or a communication component 860 .

[0162] Bus 810 includes one or more components that enable wired and / or wireless communication between components of device 800. Bus 810 may be connected to Figure 8 The processor 820 may be a computer program product or a processor that is coupled together, for example, by operational coupling, communicative coupling, electrical coupling, and / or electrical coupling. The processor 820 may include a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field programmable logic gate array, an application specific integrated circuit, and / or other types of process elements. The processor 820 may be implemented in hardware, firmware, or a combination of hardware and software. In some embodiments, the processor 820 may include one or more processors that may be programmed to perform one or more operations or processes described elsewhere in the present disclosure.

[0163] The memory 830 may include volatile and / or non-volatile memory. For example, the memory 830 may include random access memory (RAM), read only memory (ROM), a hard disk drive, and / or other types of memory (e.g., flash memory, magnetic memory, and / or optical memory). The memory 830 may include internal memory (e.g., RAM, ROM, or hard disk drive) and / or removable memory (e.g., removable via a universal serial bus connection). The memory 830 may be a non-transitory computer-readable medium. The memory 830 may store information, one or more instructions, and / or software (e.g., one or more software applications) related to the operation of the device 800. In some embodiments, the memory 830 may include one or more memories coupled (e.g., communicatively coupled) to one or more processors (e.g., processor 820), for example, via a bus 810.

[0164] Input components 840 enable device 800 to receive input, such as user input and / or sensor input. For example, input components 840 may include a touch screen, a keyboard, a keypad, a mouse, a button, a microphone, a converter, a sensor, a global positioning system sensor, a global satellite navigation system sensor, an accelerometer, a gyroscope and / or a brake. Output components 850 enable device 800 to provide output, such as through a screen, a loudspeaker and / or a light emitting diode. Communication components 860 enable device 800 to communicate with other devices through wired connections and / or wireless connections. For example, communication components 860 may include a receiver, a transmitter, a transceiver, a modem, a network interface card and / or an antenna.

[0165] The device 800 may perform one or more operations or processes described in the present disclosure. For example, a non-transitory computer-readable medium (e.g., memory 830) may store a set of instructions (e.g., one or more instructions or program codes) executed by the processor 820. The processor 820 may perform one or more operations or processes described in the present disclosure. In some embodiments, a set of instructions executed by one or more processors 820 causes one or more processors 820 and / or the device 800 to perform one or more operations or processes described in the present disclosure. In some embodiments, fixed-wire circuits may replace or be combined with instructions to perform one or more operations or processes described in the present disclosure. In addition or alternatively, the processor 820 is configured to perform one or more operations or processes described in the present disclosure. Therefore, the embodiments described in the present disclosure are not limited to any particular combination of fixed-wire circuits and software.

[0166] Figure 8 The number and configuration of components shown are provided for illustration only. Device 800 may include additional components, fewer components, different components, or different Figure 8 Additionally or alternatively, one set of components (eg, one or more components) of device 800 may perform one or more functions described as being performed by another set of components of device 800.

[0167] Fig. 9 is a flow chart of an exemplary process 900 associated with forming a pixel sensor. In some embodiments, Fig. 9 One or more process blocks of are performed by one or more semiconductor process tools (e.g., one or more of semiconductor process tools 102 to semiconductor process tools 116). In addition or alternatively, Fig. 9 One or more process blocks may be performed by one or more components of the apparatus 800 , such as a processor 820 , a memory 830 , an input component 840 , an output component 850 , and / or a communication component 860 .

[0168] like Fig. 9 As shown, process 900 may include forming a metal layer on an isolation structure, wherein the isolation structure at least partially surrounds the photodiode (block 910). For example, one or more of semiconductor process tools 102 to semiconductor process tools 116 may form metal layer 314 on isolation structure 308, wherein isolation structure 308 at least partially surrounds photodiode 306, as described herein.

[0169] Further Fig. 9 As shown, process 900 may include etching a portion of the metal layer to form at least one recess (block 920). For example, one or more of semiconductor process tools 102 to 116 may etch a portion of metal layer 314 to form at least one recess 406 as described herein.

[0170] Further Fig. 9 As shown, the process 900 may include forming at least one dielectric layer on the metal layer to surround the air gap in the metal layer (block 930). For example, one or more of the semiconductor process tools 102 to the semiconductor process tools 116 may form at least one dielectric layer 318 on the metal layer 314 such that the at least one dielectric layer 318 surrounds the air gap 320 in the metal layer 314, as described herein.

[0171] Process 900 may include additional embodiments, such as any single embodiment or any combination of the embodiments described below and / or in combination with one or more other processes described elsewhere in this disclosure.

[0172] In the first embodiment, the process 900 includes etching a portion of the isolation structure 308 to enlarge the at least one recess 406 so that the air gap 320 extends further into the isolation structure 308 .

[0173] In the second embodiment, alone or in combination with the first embodiment, etching a portion of the isolation structure 308 includes etching the isolation structure 308 until the at least one etch stop layer 352 is exposed, wherein the at least one etch stop layer 352 is between the isolation structure 308 and the surrounding substrate 304 .

[0174] In the third embodiment, alone or in combination with one or more of the first and second embodiments, forming the at least one dielectric layer includes forming a first dielectric layer 318 on the metal layer 314 , and forming a second dielectric layer 332 on the first dielectric layer 318 .

[0175] In a fourth embodiment, alone or in combination with one or more of the first to third embodiments, the process 900 includes etching a portion of the first dielectric layer 318 to expose the at least one recess 406 to extend the air gap 320 further into the first dielectric layer 318 .

[0176] Although Fig. 9 Example blocks of process 900 are shown. In some embodiments, process 900 includes additional blocks, fewer blocks, different blocks, or blocks that are different from Fig. 9 The block configuration is depicted. Additionally or alternatively, two or more blocks of process 900 may be performed simultaneously.

[0177] Thus, the shielding structure of the air gaps on the grid structure between the pixel sensors in the pixel array reduces crosstalk. The efficiency and signal-to-noise ratio of the pixel sensor are increased due to the reduced crosstalk. The shielding structure also increases the quantum efficiency of the pixel array because the air gaps do not absorb photons.

[0178] As described in detail above, some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a photodiode and an isolation structure at least partially surrounding the photodiode. The semiconductor device includes a grid structure on the isolation structure, wherein the grid structure includes a metal layer having at least one air gap and at least one dielectric layer.

[0179] As described in detail above, some embodiments of the present disclosure provide a method. The method includes forming a metal layer on an isolation structure, wherein the isolation structure at least partially surrounds a photodiode. The method includes etching a portion of the metal layer to form at least one groove. The method includes forming at least one dielectric layer on the metal layer, wherein the at least one dielectric layer surrounds an air gap in the metal layer.

[0180] As described in detail above, some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a photodiode and an isolation structure at least partially surrounding the photodiode and including at least one air gap. The semiconductor device includes a mesh structure on the isolation structure, wherein the mesh structure includes a metal layer and at least one dielectric layer, wherein the at least one air gap extends into the metal layer.

[0181] Depending on the context, "satisfying a threshold" as used in the present disclosure may mean a value greater than a threshold, greater than or equal to a threshold, less than a threshold, less than or equal to a threshold, equal to a threshold, not equal to a threshold, etc.

[0182] One aspect of the present disclosure provides a semiconductor device comprising a photodiode, an isolation structure at least partially surrounding the photodiode, and a mesh structure on the isolation structure, wherein the mesh structure comprises a metal layer having at least one air gap and at least one dielectric layer.

[0183] In some embodiments, the semiconductor device further includes an oxide material on a surface of the at least one air gap.

[0184] In some embodiments, the at least one dielectric layer includes a first dielectric layer and a second dielectric layer.

[0185] In some embodiments, the at least one air gap further extends into the first dielectric layer.

[0186] In some embodiments, the semiconductor device further includes a buffer layer between the isolation structure and the metal layer.

[0187] In some embodiments, the at least one air gap further extends into the buffer layer.

[0188] One aspect of the present disclosure provides a method for manufacturing a semiconductor device, comprising forming a metal layer on an isolation structure, wherein the isolation structure at least partially surrounds a photodiode; etching a portion of the metal layer to form at least one groove; and forming at least one dielectric layer on the metal layer, wherein the at least one dielectric layer surrounds an air gap in the metal layer.

[0189] In some embodiments, the method further includes etching a portion of the isolation structure to enlarge the at least one recess so that the air gap further extends into the isolation structure.

[0190] In some embodiments, etching a portion of the isolation structure includes etching the isolation structure until at least one etch stop layer is exposed, wherein the at least one etch stop layer is between the isolation structure and the surrounding substrate.

[0191] In some embodiments, forming the at least one dielectric layer includes forming a first dielectric layer on the metal layer, and forming a second dielectric layer on the first dielectric layer.

[0192] In some embodiments, the method includes etching a portion of the first dielectric layer to expose the at least one recess such that the air gap extends further into the first dielectric layer.

[0193] Another aspect of the present disclosure provides a semiconductor device. The semiconductor device includes a photodiode, an isolation structure at least partially surrounding the photodiode, and a grid structure on the isolation structure. The isolation structure includes at least one air gap. The grid structure includes a metal layer and at least one dielectric layer, wherein the at least one air gap further extends into the metal layer.

[0194] In some embodiments, the semiconductor device further includes an oxide material on a surface of the at least one air gap.

[0195] In some embodiments, the semiconductor device further includes at least one etch stop layer between the isolation structure and the surrounding substrate.

[0196] In some embodiments, the semiconductor device further includes a high dielectric constant layer between the isolation structure and the surrounding substrate.

[0197] In some embodiments, the at least one etch stop layer is between the oxide filling of the isolation structure and the high dielectric constant layer.

[0198] In some embodiments, the at least one dielectric layer includes a first dielectric layer and a second dielectric layer.

[0199] In some embodiments, the at least one air gap further extends into the first dielectric layer.

[0200] In some embodiments, the semiconductor device further includes a buffer layer between the isolation structure and the metal layer.

[0201] In some embodiments, the at least one air gap further extends into the buffer layer.

[0202] Another aspect of the present disclosure is to provide a semiconductor device, comprising a photodiode; an isolation structure at least partially surrounding the photodiode; a metal layer on the isolation structure, wherein the metal layer comprises an air gap; and at least one dielectric layer on the metal layer, wherein the at least one dielectric layer surrounds the air gap in the metal layer.

[0203] In some embodiments, the dielectric layer includes a first dielectric layer on the metal layer, wherein the air gap further extends into the first dielectric layer; and a second dielectric layer on the first dielectric layer.

[0204] The above summarizes the features of many embodiments, so that those with ordinary knowledge in the art can better understand the aspects of the present disclosure. Those with ordinary knowledge in the art should understand that other processes and structures can be designed or modified based on the present disclosure to achieve the same purpose and / or achieve the same advantages as the embodiments described. Those with ordinary knowledge in the art should also understand that equivalent structures do not deviate from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: Include: a photodiode; an isolation structure at least partially surrounding the photodiode; and A grid structure is on the isolation structure, wherein the grid structure comprises a metal layer and at least one dielectric layer, and the metal layer has at least one air gap.

2. The semiconductor device according to claim 1, wherein The at least one dielectric layer includes a first dielectric layer and a second dielectric layer.

3. The semiconductor device according to claim 2, wherein: The at least one air gap further extends into the first dielectric layer.

4. The semiconductor device according to any one of claims 1 to 3, wherein: Also includes: A buffer layer is between the isolation structure and the metal layer.

5. The semiconductor device according to claim 4, wherein: The at least one air gap further extends into the buffer layer.

6. A semiconductor device, characterized in that: Include: a photodiode; an isolation structure, wherein the isolation structure at least partially surrounds the photodiode; a metal layer on the isolation structure, wherein the metal layer includes an air gap; as well as At least one dielectric layer is on the metal layer, wherein the at least one dielectric layer surrounds the air gap in the metal layer.

7. The semiconductor device according to claim 6, wherein: The at least one dielectric layer comprises: a first dielectric layer on the metal layer, wherein the air gap further extends into the first dielectric layer; and A second dielectric layer is on the first dielectric layer.

8. A semiconductor device, characterized in that: Include: a photodiode; an isolation structure at least partially surrounding the photodiode, wherein the isolation structure includes at least one air gap; and A grid structure is on the isolation structure, wherein the grid structure comprises a metal layer and at least one dielectric layer, and the at least one air gap further extends into the metal layer.

9. The semiconductor device according to claim 8, wherein: Also includes: At least one etch stop layer is between the isolation structure and a surrounding substrate.

10. The semiconductor device according to claim 8 or 9, wherein: Also includes: A buffer layer is between the isolation structure and the metal layer, wherein the at least one air gap further extends into the buffer layer.

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