Solar cell, photovoltaic module and photovoltaic system

Abstract

The utility model relates to the technical field of solar cells, in particular to a solar cell, a photovoltaic module and a photovoltaic system. The potential risk that high-temperature slurry is sintered and diffused into a tunneling oxide layer is reduced while parasitic absorption of a doped polycrystalline silicon layer is reduced, and non-radiative recombination is reduced. A solar cell comprises a silicon substrate layer which comprises a first surface and a second surface which are oppositely arranged; the tunneling oxide layer is arranged on the first surface of the silicon substrate layer; the doped polycrystalline silicon layer is arranged on one side, far away from the silicon substrate layer, of the tunneling oxide layer; the doped polycrystalline silicon layer comprises a first sub-layer and a second sub-layer which are sequentially stacked in the direction gradually away from the silicon substrate layer; and a gate line electrode pattern; wherein the first sub-layer is further doped with a carbon element, and ohmic contact is formed between the grid line electrode pattern and the second sub-layer.

Description

Technical Field

[0001] The present application relates to the technical field of solar cells, and in particular to a solar cell, a photovoltaic module and a photovoltaic system. Background Art

[0002] In solar cells, when the stacked structure of the tunnel oxide layer and the doped polysilicon layer is used as a back-side passivation contact structure, the doped polysilicon layer has severe parasitic absorption of light. Therefore, if the doped polysilicon layer grows too thick, it will be detrimental to the solar cell's absorption of light, thereby reducing the short-circuit current of the cell. If the doped polysilicon layer grows too thin, the high-temperature slurry will sinter and diffuse into the tunnel oxide layer, which will easily cause unnecessary non-radiative recombination. Utility Model Content

[0003] Based on this, it is necessary to provide a solar cell, a photovoltaic module and a photovoltaic system to reduce the parasitic absorption of the doped polysilicon layer, reduce the potential risk of high-temperature slurry sintering and diffusion into the tunnel oxide layer, and reduce non-radiative recombination.

[0004] In a first aspect, a solar cell is provided, comprising:

[0005] A silicon base layer, the silicon base layer comprising a first surface and a second surface arranged opposite to each other;

[0006] A tunneling oxide layer, disposed on the first surface of the silicon base layer;

[0007] A doped polysilicon layer, wherein the doped polysilicon layer is disposed on a side of the tunnel oxide layer away from the silicon base layer; and the doped polysilicon layer comprises: a first sublayer and a second sublayer sequentially stacked in a direction gradually away from the silicon base layer; and

[0008] A grid electrode pattern;

[0009] The first sub-layer is doped with carbon elements, and an ohmic contact is formed between the gate line electrode pattern and the second sub-layer.

[0010] Optionally, both the first sublayer and the second sublayer are doped with N-type doping elements;

[0011] The doping concentration of the N-type doping element in the first sublayer is less than the doping concentration of the N-type doping element in the second sublayer.

[0012] Optionally, the doped polysilicon layer has a thickness of 60 nm to 80 nm.

[0013] Optionally, the thickness of the first sublayer is 10 nm to 20 nm, and the thickness of the second sublayer is 50 nm to 60 nm.

[0014] Optionally, the first sublayer is doped with acetylene and / or ethylene to dope the first sublayer with carbon elements.

[0015] Optionally, the solar cell further comprises: a doping element diffusion barrier layer, the doping element diffusion barrier layer being used to block the doping element in the second sub-layer from diffusing into the first sub-layer and the tunneling oxide layer;

[0016] The doping element diffusion barrier layer is disposed between the first sub-layer and the second sub-layer.

[0017] Optionally, the doping element diffusion barrier layer is a silicon oxide layer.

[0018] Optionally, the slurry sintered diffusion barrier layer has a thickness of 1 nm to 2 nm.

[0019] In a second aspect, a photovoltaic assembly is provided, comprising: a plurality of solar cells connected in series and / or in parallel;

[0020] At least one of the solar cells is a solar cell as described in the first aspect.

[0021] In a third aspect, a photovoltaic system is provided, comprising the photovoltaic assembly as described in the second aspect.

[0022] The beneficial effects of the above-mentioned solar cell, photovoltaic module and photovoltaic system are as follows:

[0023] Since the doped polysilicon layer includes: a first sublayer and a second sublayer sequentially stacked in a direction gradually away from the silicon base layer, the first sublayer and the second sublayer are both polysilicon layers doped with N-type or P-type doping elements. Therefore, since the first sublayer is also doped with carbon elements, compared with the related art in which only N-type or P-type doping elements are doped in the doped polysilicon layer, when the thickness of the doped polysilicon layer remains unchanged, the band gap of the first sublayer is increased, which can reduce the parasitic absorption of the doped polysilicon layer and has a positive effect on the improvement of current; at the same time, the carbon element in the first sublayer can form a dense structure, so on the one hand, it can prevent the doping elements (such as N-type or P-type doping elements) in the second sublayer from diffusing at high temperature to impact the tunneling oxide layer, and reduce Auger recombination caused by excessive doping concentration of N-type or P-type doping elements in the silicon base layer; on the other hand, it can prevent the subsequent slurry from penetrating the doped polysilicon layer and diffusing into the tunneling oxide layer during the sintering process, thereby reducing the potential risk of the tunneling oxide layer being penetrated during the subsequent sintering process, and further reducing carrier recombination. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A schematic diagram of the cross-sectional structure of a solar cell provided in an embodiment of the present application. DETAILED DESCRIPTION

[0025] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited by the specific embodiments disclosed below.

[0026] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0027] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0028] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0029] Herein, unless otherwise specified, "one or more" means one or more than or equal to two.

[0030] In this document, "for example", "such as", "example", "for example", etc. are used for descriptive purposes, indicating that the previous and subsequent technical solutions are related in terms of the content covered, but should not be understood as limiting the previous technical solution, nor can they be understood as limiting the scope of protection of this document. In this document, unless otherwise specified, A (such as B) means that B is a non-limiting example of A, and it can be understood that A is not limited to B.

[0031] In this article, "optionally", "optional", and "optional" mean optional, that is, any one of the two parallel options of "yes" or "no". If there are multiple "options" in a technical solution, unless otherwise specified and there is no contradiction or mutual restriction, each "option" is independent.

[0032] Herein, descriptions such as "optionally contain", "optionally include", etc., mean "contain or not contain". "Optional component X" means component X exists or does not exist, or means containing or not containing the component X.

[0033] In this document, the terms "first", "second", etc. in "the first aspect", "the second aspect", etc. are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or quantity, nor can they be understood as implicitly indicating the importance or quantity of the indicated technical features.

[0034] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used herein are for illustrative purposes only and are not intended to be the only implementation method.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0036] In this article, the technical features described in an open manner include closed technical solutions composed of the listed features, and also include open technical solutions containing the listed features.

[0037] In this document, "at least one" means more than one, such as one, two and more than two. "Multiple" or "several" means at least two, such as two, three, etc., and "multilayer" means at least two layers, such as two layers, three layers, etc., unless otherwise clearly and specifically defined. In the description of this application, "several" means at least one, such as one, two, etc., unless otherwise clearly and specifically defined.

[0038] Herein, when it comes to a numerical interval (i.e., a numerical range), unless otherwise specified, the distribution of the optional numerical values ​​in the numerical interval is considered to be continuous, and includes the two numerical endpoints (i.e., the minimum and maximum values) of the numerical interval, and each numerical value between the two numerical endpoints. Unless otherwise specified, when the numerical interval only refers to the integers in the numerical interval, including the two endpoint integers of the numerical range, and each integer between the two endpoints, is equivalent to directly listing each integer. When multiple numerical ranges are provided to describe features or characteristics, these numerical ranges can be combined. In other words, unless otherwise specified, the numerical ranges disclosed herein should be understood to include any and all sub-ranges included therein. The "numerical value" in the numerical interval can be any quantitative value, such as a number, a percentage, a ratio, etc. "Numerical interval" allows broadly including numerical interval types such as percentage intervals, ratio intervals, and ratio intervals.

[0039] In this article, when it comes to temperature parameters, unless otherwise specified, both constant temperature treatment and treatment within a certain temperature range are allowed. The constant temperature treatment allows the temperature to fluctuate within the accuracy range of instrument control.

[0040] Herein, the term "room temperature" or "normal temperature" generally refers to 4°C to 35°C, for example, 20°C ± 5°C. In some embodiments herein, "room temperature" or "normal temperature" refers to 10°C to 30°C. In some embodiments herein, "room temperature" or "normal temperature" refers to 20°C to 30°C.

[0041] The fill factor (FF) used in this article refers to the ratio of the actual maximum obtainable power (Pm or Vmp*Jmp) to the theoretical (not actually obtainable) power (Jsc*Voc). Therefore, FF can be determined by the following formula:

[0042] FF=(Vmp*Jmp) / (Jsc*Voc)

[0043] Where Jmp and Vmp represent the current density and voltage at the maximum power point (Pm), which is obtained by changing the resistance in the circuit until J*V is the maximum value; Jsc and Voc represent the short-circuit current and open-circuit voltage, respectively. Fill factor is a key parameter for evaluating solar cells. Commercial solar cells usually have a fill factor of about 60% and above.

[0044] As used herein, open circuit voltage (Voc) is the potential difference between the anode and cathode of a device with no external load connected.

[0045] The power conversion efficiency (PCE) of a solar cell as used herein refers to the percentage of power converted from absorbed light to electrical energy. The power conversion efficiency (PCE) of a solar cell can be measured by the incident light irradiance (E: W / m2 ) and the surface area of ​​the solar cell (Ac:m 2 ) divided by the maximum power point (Pm). STC usually refers to the temperature of 25℃ and the irradiance of 1000W / m 2 , the spectrum of air quality 1.5 (AM1.5).

[0046] In the stacked passivation contact structure of the tunneling oxide layer and the doped polysilicon layer, the passivation mechanism is: utilizing the quantum tunneling effect and pinhole structure of the tunneling oxide layer to prevent minority carriers from passing through to reduce the recombination of carriers. At the same time, the dangling bonds on the interface of the silicon base layer and the tunneling oxide layer can be saturated with hydrogen atoms in the hydrogen-containing annealing atmosphere, thereby reducing the surface state density and playing a chemical passivation role. In addition, since the tunneling oxide layer itself carries a fixed positive charge, it will induce a built-in electric field in the contact area, allowing carriers to pass selectively, playing a field passivation effect.

[0047] In this process, the doped polysilicon layer can effectively improve the battery performance due to its good carrier transport performance and low resistance. In the process of amorphous silicon being transformed into polysilicon through high-temperature annealing, the interface state defect density can be reduced, the carrier recombination loss can be reduced, and the open circuit voltage and fill factor of the battery can be improved.

[0048] However, the doped polysilicon layer has severe parasitic absorption of light. If the thickness is too large, it will not only increase the process cost, but also have a great loss in performance. For example, it is not conducive to the absorption and utilization of light by solar cells and reduces the short-circuit current of the battery. If the thickness is too small, in the subsequent slurry sintering process, at a higher temperature, the slurry will burn through the doped polysilicon layer and diffuse into the tunneling oxide layer and even the silicon base layer, causing unnecessary non-radiative recombination and reducing the conversion efficiency of the solar cell.

[0049] Based on this, in a first aspect, some embodiments of the present application provide a solar cell 1, such as Figure 1 As shown, the solar cell 1 comprises: a silicon base layer 11, a tunneling oxide layer 12, a doped polysilicon layer 13 and a gate electrode pattern 14. The silicon base layer 11 comprises a first surface 11a and a second surface 11b arranged opposite to each other, the tunneling oxide layer 12 is arranged on the first surface 11a of the silicon base layer 11, the doped polysilicon layer 13 is arranged on a side of the tunneling oxide layer 12 away from the silicon base layer 11, and the doped polysilicon layer 13 comprises: a first sublayer 131 and a second sublayer 132 stacked in sequence in a direction gradually away from the silicon base layer 11. The first sublayer 131 is also doped with carbon, and an ohmic contact is formed between the gate electrode pattern 14 and the second sublayer 132.

[0050] The solar cell 1 can be exemplarily a TOPCon (Tunnel Oxide Passivation Contact) solar cell or an IBC (Interdigitated Back Contact) solar cell, which is not specifically limited here. All passivation contact structures using a stacked structure of a tunnel oxide layer and a doped polysilicon layer are within the protection scope of this application.

[0051] In the following embodiments, the present application will be described in detail by taking the solar cell 1 as a TOPCon (Tunnel Oxide Passivation Contact) solar cell as an example.

[0052] In some embodiments, the first surface 11 a may be the back surface or the front surface of the silicon base layer 11 , which is not specifically limited herein.

[0053] In some embodiments, the silicon substrate layer 11 may be an N-type silicon substrate. In this case, the first surface 11a is the back side of the silicon substrate layer 11, and the second surface 11b is the front side of the silicon substrate layer 11. In this case, the doped polysilicon layer 13 may be an N-type doped polysilicon layer or a P-type doped polysilicon layer. The N-type doped polysilicon layer may be doped with an N-type doping element, such as a P element, and the P-type doped polysilicon layer may be doped with a P-type doping element, such as a B element. In addition, Figure 1 As shown, the solar cell 1 may further include a light trapping structure disposed on the second surface 11 b , a P-type emitter or an N-type emitter 16 , a front passivation layer 17 , an anti-reflection layer 18 , and a front electrode pattern 19 .

[0054] Since the doped polysilicon layer 13 includes: a first sublayer 131 and a second sublayer 132 stacked in sequence in a direction gradually away from the silicon base layer 11, according to the definition of the doped polysilicon layer 13, the first sublayer 131 and the second sublayer 132 are both polysilicon layers doped with N-type or P-type doping elements. Therefore, since the first sublayer 131 is also doped with carbon elements, compared with the related art in which only N-type or P-type doping elements are doped in the doped polysilicon layer 13, when the thickness of the doped polysilicon layer 13 remains unchanged, the band gap of the first sublayer 131 is increased, which can reduce the parasitic absorption of the doped polysilicon layer 13 and has a positive effect on the improvement of current; at the same time, the carbon elements in the first sublayer 131 can form a dense structure, so on the one hand, it can prevent the doping elements (such as N-type or P-type doping elements) in the second sublayer 132 from diffusing at high temperature to impact the tunneling oxide layer 12, and reduce Auger recombination caused by excessive doping concentration of N-type or P-type doping elements in the silicon base layer; on the other hand, it can prevent the subsequent slurry from penetrating the doped polysilicon layer 13 and diffusing into the tunneling oxide layer 12 during the sintering process, thereby reducing the potential risk of the tunneling oxide layer 12 being penetrated during the subsequent sintering process, and further reducing carrier recombination.

[0055] The doped polysilicon layer 13 may be doped with an N-type doping element or a P-type doping element. In the embodiment of the present application, only the doped polysilicon layer 13 doped with an N-type doping element is used as an example for description.

[0056] In some embodiments, taking the example that both the first sublayer 131 and the second sublayer 132 are doped with N-type doping elements, the doping concentration of the N-type doping element in the first sublayer 131 is less than the doping concentration of the N-type doping element in the second sublayer 132 .

[0057] In these embodiments, it is possible to ensure that the second sublayer 132 has good carrier transport performance and low resistance, thereby improving the conductivity of the solar cell 1, and the doping concentration of the N-type doping element in the first sublayer 131 is relatively low, which can further reduce parasitic absorption. On the other hand, the N-type doping element in the first sublayer 131 will diffuse into the silicon base layer during the high-temperature annealing process, thereby ensuring that the silicon base layer has a certain amount of N-type doping elements, which plays a role in field passivation, and the doping of carbon elements can form a dense film structure, which can prevent the excessive diffusion of N-type doping elements from impacting the tunneling oxide layer, and can reduce the Auger recombination caused by the excessively high doping concentration of the N-type doping element in the silicon base layer. In addition, the doping of the above-mentioned carbon element can also increase the band gap of the first sublayer, which has a positive effect on the improvement of current.

[0058] In some embodiments, the thickness of the doped polysilicon layer 13 is 60 nm to 80 nm. For example, the thickness of the doped polysilicon layer 13 can be 60 nm, 61 nm, 62 nm, 63 nm, 64 nm, 65 nm, 66 nm, 67 nm, 68 nm, 69 nm, 70 nm, 71 nm, 72 nm, 73 nm, 74 nm, 75 nm, 76 nm, 77 nm, 78 nm, 79 nm or 80 nm.

[0059] In these embodiments, by controlling the thickness of the doped polysilicon layer 13 within the above range, the doped polysilicon layer 13 can be kept at a relatively large thickness, thereby better blocking the diffusion of the slurry into the tunneling oxide layer 12 and the silicon base layer 11, and on this basis, minimizing the parasitic absorption of light by the doped polysilicon layer 13.

[0060] In some embodiments, the thickness of the first sublayer 131 is 10nm to 20nm, and the thickness of the second sublayer 132 is 50nm to 60nm. For example, the thickness of the first sublayer 131 can be 10nm, 11nm, 12nm, 13nm, 14nm, 15nm, 16nm, 17nm, 18nm, 19nm or 20nm; the thickness of the second sublayer 132 can be 50nm, 51nm, 52nm, 53nm, 54nm, 55nm, 56nm, 57nm, 58nm, 59nm or 60nm.

[0061] In these embodiments, by controlling the thickness of the first sublayer 131 and the second sublayer 132 within the above ranges, the band gap of the doped polysilicon layer 13 can be increased to a large extent, and the parasitic absorption of light by the doped polysilicon layer 13 can be reduced. At the same time, the potential risk of the slurry diffusing into the tunneling oxide layer 12 and the silicon base layer 11 can be reduced as much as possible, thereby minimizing carrier recombination.

[0062] In some embodiments, acetylene and / or ethylene are doped into the first sub-layer 131 to dope carbon into the first sub-layer 131 .

[0063] In these embodiments, by doping acetylene and / or ethylene into the first sublayer 131, carbon elements can be doped into the first sublayer 131, thereby increasing the band gap of the first sublayer 131, reducing parasitic absorption, and improving the density of the first sublayer 131, reducing the potential risk of slurry diffusion into the tunneling oxide layer 12 and the silicon base layer 11, thereby reducing recombination.

[0064] Among them, the specific implementation method of doping acetylene and / or ethylene in the above-mentioned first sublayer 131 is not limited, as long as N-type doping elements and acetylene and / or ethylene can be doped in the polysilicon layer to dope N-type doping elements and carbon elements in the polysilicon layer.

[0065] In some embodiments, the first sub-layer 131 can be prepared by directly depositing a polysilicon layer, or by crystallizing amorphous silicon, which is not specifically limited here.

[0066] In some embodiments, the first sublayer 131 can be prepared by chemical vapor deposition. In these embodiments, in-situ doping can be achieved during the deposition process, which has the advantages of good uniformity and high doping concentration, and the thickness of the prepared first sublayer 131 can be made relatively thin, thereby further reducing the optical loss caused by parasitic absorption.

[0067] Here, taking the doping of acetylene in the first sub-layer 131 as an example, the preparation of the first sub-layer 131 by chemical vapor deposition is described:

[0068] Step 1), selecting silane, hydrogen, phosphine and acetylene as gas sources;

[0069] Step 2), silane, hydrogen, phosphine and acetylene are introduced into the vacuum chamber, glow discharge is performed in the vacuum chamber under the action of electrode voltage, and active particle groups are generated. These active particle groups diffuse to the surface of the tunneling oxide layer and react with the adsorbed molecules to generate a doped amorphous silicon layer doped with acetylene and P element;

[0070] In which, in the vacuum chamber, the pressure during the reaction can be 2000mtorr~3000mtorr, the flow rate of silane can be 3000sccm~3500sccm, the flow rate of hydrogen can be 8000sccm~12000sccm, the flow rate of phosphine can be 350sccm~550sccm, and the flow rate of acetylene can be 100sccm~300sccm. During the reaction, the heating temperature in the vacuum chamber can be 400℃~550℃, and the time can be 70s~140s.

[0071] Step 3) annealing the doped amorphous silicon layer to convert the doped amorphous silicon layer into a doped polysilicon layer, thereby obtaining the first sublayer 131.

[0072] The pressure of the annealing treatment may be 200 mbar to 500 mbar, the flow rate of the inert gas may be 2000 sccm to 4000 sccm, the temperature of the annealing treatment may be 800° C. to 1000° C., and the time may be 1400 s to 1880 s.

[0073] The parameters when ethylene is doped into the first sub-layer 131 are substantially the same as the above parameters, and will not be described in detail herein.

[0074] In other embodiments, the second sublayer 132 can also be prepared by chemical vapor deposition, which can also achieve in-situ doping, has the advantages of good uniformity and high doping concentration, and the thickness of the prepared second sublayer 132 can be made very thin, thereby further reducing the optical loss caused by parasitic absorption.

[0075] In some embodiments, chemical vapor deposition is used to prepare the second sublayer 132. Similar to the chemical vapor deposition used to prepare the first sublayer 131, the above-mentioned preparation method can be referred to, and the only difference is that the gas source of the second sublayer 132 can be silane, hydrogen and phosphine, and in order to increase the doping concentration of the P-doped element in the second sublayer 132, the pressure and flow rate of each gas source and the RF power and other parameters can be controlled to achieve this. For example, when other conditions remain unchanged, the flow rate of phosphine can be increased to prepare the second sublayer 132 with a higher doping concentration of the N-type doping element.

[0076] For example, when chemical vapor deposition is used to prepare the second sublayer 132, in the vacuum chamber, the pressure during the reaction can be 2000mtorr~3000mtorr, the flow rate of silane can be 3000sccm~3500sccm, the flow rate of hydrogen can be 8000sccm~12000sccm, and the flow rate of phosphine can be 350sccm~550sccm. During the reaction, the heating temperature in the vacuum chamber can be 400℃~550℃, and the time can be 500s~700s.

[0077] In some embodiments, the solar cell 1 also includes: an impurity diffusion barrier layer 15, which is used to block the impurity in the second sublayer from diffusing into the first sublayer 131 and the tunneling oxide layer 12; the impurity diffusion barrier layer 15 is arranged between the first sublayer 131 and the second sublayer 132.

[0078] In these embodiments, by providing the doping element diffusion barrier layer 15 , the diffusion of the doping element into the tunneling oxide layer 12 can be blocked, thereby reducing the risk of the doping element penetrating the tunneling oxide layer 12 .

[0079] In some embodiments, the doping element diffusion barrier layer 15 is a silicon oxide layer.

[0080] In these embodiments, the silicon oxide layer can also play a role in blocking the slurry from sintering and diffusion, thereby blocking the slurry from sintering and diffusion into the tunnel oxide layer, thereby reducing the non-radiative recombination.

[0081] In some embodiments, the thickness of the doping element diffusion barrier layer 15 is 1 nm to 2 nm.

[0082] In these embodiments, while ensuring the barrier effect on the diffusion of doping elements and slurry during sintering, the thickness of the doping element diffusion barrier layer 15 can be reduced as much as possible to reduce the degradation of carrier transport performance caused by this.

[0083] In some embodiments, Figure 1 As shown, the solar cell may further include a back passivation layer 20 , which may be disposed between the second sublayer 132 and the gate electrode pattern 14 . In this case, the gate electrode pattern 14 also passes through the back passivation layer 20 to form an ohmic contact with the second sublayer 132 .

[0084] In a second aspect, some embodiments of the present application provide a photovoltaic assembly, the photovoltaic assembly comprising: a plurality of solar cells connected in series and / or in parallel;

[0085] At least one of the solar cells is a solar cell as described in the first aspect.

[0086] Since the photovoltaic module includes the solar cell provided by the above embodiment, it has the same beneficial effects as the solar cell described in the first aspect, which will not be described in detail here.

[0087] In a third aspect, some embodiments of the present application provide a photovoltaic system, comprising the photovoltaic component as described in the second aspect.

[0088] Since the photovoltaic system includes the photovoltaic assembly provided by the above embodiment, it has the same beneficial effects as the photovoltaic assembly described in the second aspect, which will not be described in detail here.

[0089] Photovoltaic systems can be used in photovoltaic power stations, such as ground power stations, rooftop power stations, water power stations, etc., and can also be used in equipment or devices that use solar energy to generate electricity, such as user solar power supplies, solar street lights, solar cars, solar buildings, etc. Of course, it is understandable that the application scenarios of photovoltaic systems are not limited to this, that is to say, photovoltaic systems can be used in all fields that require solar energy to generate electricity. Taking the photovoltaic power generation system network as an example, the photovoltaic system may include a photovoltaic array, a junction box and an inverter. The photovoltaic array can be an array combination of multiple solar cells. For example, multiple solar cells can form multiple photovoltaic arrays. The photovoltaic array is connected to the junction box. The junction box can converge the current generated by the photovoltaic array. The converged current flows through the inverter and is converted into the alternating current required by the mains power grid. After that, it is connected to the mains network to realize solar power supply.

[0090] In order to objectively evaluate the technical effects of the embodiments of the present application, the present application will be described in detail and exemplarily through the following embodiments and comparative examples.

[0091] In the following examples and comparative examples, all raw materials can be purchased commercially, and in order to maintain the reliability of the experiment, the raw materials used in the following examples and comparative examples have the same physical and chemical parameters or are prepared by the same processing method.

[0092] Example 1

[0093] The method for preparing the solar cell provided in Example 1 is as follows:

[0094] S1), performing texturing treatment on the front side of the N-type silicon wafer to form a surface light trapping structure;

[0095] S2), preparing a P-type emitter on the front side of the N-type silicon wafer;

[0096] S31), forming a tunneling oxide layer on the back side of the N-type silicon wafer forming the P-type emitter; the preparation method of the tunneling oxide layer is as follows:

[0097] Laughing gas is used as a reaction gas and is deposited on the surface of an N-type silicon wafer through plasma under high temperature to form a tunneling oxide layer. During this process, the pressure in the vacuum chamber is 1940mtorr, the reaction temperature is 460°C, the reaction time is 110s, the flow rate of the laughing gas is 12000sccm, and the thickness of the prepared tunneling oxide layer is 1.5nm.

[0098] S32), forming a first sublayer and a second sublayer stacked in sequence on the tunnel oxide layer; the first sublayer is a polysilicon layer doped with P element and acetylene, and the second sublayer is a polysilicon layer doped with P element; the preparation method of the first sublayer and the second sublayer is as follows:

[0099] Silane, hydrogen, phosphine and ethylene are used as reaction gases to prepare an amorphous silicon layer doped with P element and ethylene. During this process, the pressure in the vacuum chamber is 2650 mtorr, the reaction temperature is 550°C, the reaction time is 140 s, the silane flow rate is 3500 sccm, the hydrogen flow rate is 12000 sccm, the phosphine flow rate is 550 sccm, and the ethylene flow rate is 300 sccm. The thickness of the amorphous silicon film prepared in this step is 20 nm.

[0100] Silane, hydrogen and phosphine are used as reaction gases to prepare an amorphous silicon layer doped with P element. The pressure in the vacuum chamber is 2650 mtorr. The reaction temperature of this step is 550°C. The reaction time is 420 s. The flow rate of silane is 3500 sccm. The flow rate of hydrogen is 12000 sccm. The flow rate of phosphine is 550 sccm. The thickness of the amorphous silicon film prepared in this step is 60 nm.

[0101] Annealing the amorphous silicon layer to activate doped phosphorus and convert the amorphous silicon into polycrystalline silicon. The reaction temperature is 800° C., the reaction time is 1400 s, the flow rate of nitrogen is 2000 sccm, and the pressure in the vacuum chamber is 200 mbar, thereby obtaining a first sublayer and a second sublayer.

[0102] S4), using TMA (Tri-Methyl Aluminum) and water as precursor vapor to perform an atomic layer deposition reaction to form an Al2O3 layer on the front side of the N-type silicon wafer;

[0103] S5), forming a silicon nitride film on the surface of the Al2O3 layer;

[0104] S6), forming a silicon nitride film on the back side of the N-type silicon wafer;

[0105] S7), preparing the front electrode pattern and the back electrode pattern by screen printing.

[0106] Example 2

[0107] The method for preparing a solar cell provided in Example 2 is substantially the same as the method for preparing a solar cell provided in Example 1, except that:

[0108] In step S31), the pressure in the vacuum chamber for forming the tunneling oxide layer is 1940 mtorr, the reaction temperature is 550° C., the reaction time is 110 s, the flow rate of nitrous oxide is 12000 sccm, and the thickness of the prepared tunneling oxide layer is 1.5 nm.

[0109] In step S32), when preparing an amorphous silicon layer doped with P element and ethylene, the pressure in the vacuum chamber is 2650 mtorr, the reaction temperature is 550°C, the reaction time is 140 s, the silane flow rate is 3500 sccm, the hydrogen flow rate is 12000 sccm, the phosphine flow rate is 550 sccm, and the ethylene flow rate is 300 sccm. The thickness of the amorphous silicon layer prepared in this step is 20 nm.

[0110] The pressure in the vacuum chamber for preparing the amorphous silicon layer doped with P element is 2650 mtorr, the reaction temperature is 550°C, the reaction time is 385 s, the flow rate of silane is 3500 sccm, the flow rate of hydrogen is 12000 sccm, and the flow rate of phosphine is 550 sccm. The thickness of the amorphous silicon layer prepared in this step is 55 nm.

[0111] The reaction temperature of the annealing treatment is 1000° C., the reaction time is 1880 s, the flow rate of nitrogen is 4000 sccm, and the reaction pressure is 500 mbar.

[0112] In addition, before preparing the amorphous silicon layer doped with the P element, the solar cell in Example 2 further includes: S33), forming a silicon dioxide barrier layer on the amorphous silicon layer doped with the P element and ethylene, and the thickness of the silicon dioxide barrier layer is 1 nm.

[0113] Example 3

[0114] The method for preparing a solar cell provided in Example 3 is substantially the same as the method for preparing a solar cell provided in Example 1, except that:

[0115] In step S31), the pressure in the vacuum chamber for forming the tunneling oxide layer is 1940 mtorr, the reaction temperature is 500° C., the reaction time is 110 s, the flow rate of nitrous oxide is 12000 sccm, and the thickness of the prepared tunneling oxide layer is 1.5 nm.

[0116] In step S32), when preparing an amorphous silicon layer doped with P element and ethylene, the pressure in the vacuum chamber is 2650 mtorr, the reaction temperature is 400°C, the reaction time is 105 s, the flow rate of silane is 3200 sccm, the flow rate of hydrogen is 10000 sccm, the flow rate of phosphine is 450 sccm, and the flow rate of ethylene is 200 sccm. The thickness of the amorphous silicon layer prepared in this step is 15 nm.

[0117] The pressure in the vacuum chamber for preparing the amorphous silicon layer doped with P element is 2650 mtorr, the reaction temperature is 550°C, the reaction time is 315 s, the flow rate of silane is 3500 sccm, the flow rate of hydrogen is 12000 sccm, and the flow rate of phosphine is 550 sccm. The thickness of the amorphous silicon layer prepared in this step is 45 nm.

[0118] The reaction temperature of the annealing treatment is 900° C., the reaction time is 1500 s, the flow rate of nitrogen is 3000 sccm, and the reaction pressure is 400 mbar.

[0119] In addition, before preparing the amorphous silicon layer doped with the P element, the solar cell in Example 3 further includes: S33), forming a silicon dioxide barrier layer on the amorphous silicon layer doped with the P element and ethylene, and the thickness of the silicon dioxide barrier layer is 1.5 nm.

[0120] Example 4

[0121] The method for preparing the solar cell provided in Example 4 is substantially the same as the method for preparing the solar cell provided in Example 3, except that the thickness of the silicon dioxide barrier layer is 2 nm.

[0122] Example 5

[0123] The method for preparing a solar cell provided in Example 5 is substantially the same as the method for preparing a solar cell provided in Example 1, except that:

[0124] The reaction time for preparing the amorphous silicon layer doped with P element and ethylene is 70s and the thickness is 10nm.

[0125] Comparative Example 1

[0126] The method for preparing the solar cell provided in Comparative Example 1 is substantially the same as the method for preparing the solar cell provided in Example 1, except that:

[0127] In step S32) of comparative example 1, only a polysilicon layer doped with P element is prepared, and the thickness of the polysilicon layer is 80 nm.

[0128] Test Case

[0129] The short-circuit current, open-circuit voltage, fill factor and PCE of the solar cells provided in Examples 1 to 5 and Comparative Example 1 were tested and calculated, and the results were shown in Table 1 below:

[0130] Table 1

[0131] Group ECP(%) Uoc(V) Isc(A) FF(%) Comparative Example 1 25.6777 0.7151 18.4517 85.8108 Example 1 25.7060 0.7152 18.4720 85.8011 Example 2 25.7896 0.7149 18.540 85.8003 Example 3 25.8667 0.715 18.593 85.7995 Example 4 25.7152 0.7151 18.542 85.5195 Example 5 25.6997 0.7151 18.531 85.5191

[0132] It can be seen from Table 1 that the thickness of the N-type doped polysilicon layer in Comparative Example 1 is 80nm; in Example 1 of the present application, the N-type doped polysilicon layer is divided into two layers, and carbon is doped in the amorphous silicon. Compared with Comparative Example 1, the introduction of carbon makes the film structure more compact, which can reduce the impact of phosphorus on the tunneling oxide layer at high temperature, and after the introduction of carbon, a thinner polysilicon layer is allowed, which can reduce the parasitic absorption of the film layer, so the current is slightly improved; on the basis of Example 1, Example 2 adds a silicon oxide barrier layer, and appropriately reduces the thickness of the amorphous silicon layer, which can reduce the parasitic absorption of the film layer, so the current of Example 2 is greatly improved. The improvement makes a great contribution to the efficiency. Example 3 further increases the thickness of the silicon oxide barrier layer and reduces the thickness of the amorphous silicon layer again, thereby further improving the efficiency. Example 4 further increases the thickness of the silicon oxide barrier layer relative to Example 3, and its efficiency decreases accordingly, which indicates that the silicon oxide barrier layer has the best effect when the thickness is 1.5nm, which can maximize the efficiency. The thickness of the amorphous silicon layer doped with P element and ethylene in Example 5 is slightly smaller than that in Example 2, which can also reduce the parasitic absorption of the film layer. Therefore, the efficiency of the solar cell provided by it is relatively high, which is almost equivalent to the efficiency of the solar cell provided by Example 4.

[0133] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0134] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A solar cell, characterized in that: include: A silicon base layer, the silicon base layer comprising a first surface and a second surface arranged opposite to each other; A tunneling oxide layer, disposed on the first surface of the silicon base layer; a doped polysilicon layer, the doped polysilicon layer being disposed on a side of the tunneling oxide layer away from the silicon base layer, and the doped polysilicon layer comprising: a first sublayer and a second sublayer stacked in sequence in a direction gradually away from the silicon base layer; and A grid electrode pattern; The first sub-layer is doped with carbon elements, and an ohmic contact is formed between the gate line electrode pattern and the second sub-layer.

2. The solar cell according to claim 1, characterized in that The first sublayer and the second sublayer are both doped with N-type doping elements; The doping concentration of the N-type doping element in the first sublayer is less than the doping concentration of the N-type doping element in the second sublayer.

3. The solar cell according to claim 1, characterized in that The thickness of the doped polysilicon layer is 60nm-80nm.

4. The solar cell according to claim 1, characterized in that The thickness of the first sublayer is 10 nm to 20 nm, and the thickness of the second sublayer is 50 nm to 60 nm.

5. The solar cell according to any one of claims 1 to 4, characterized in that: The first sublayer is doped with acetylene and / or ethylene to dope the first sublayer with carbon elements.

6. The solar cell according to any one of claims 1 to 4, characterized in that: Also includes: A doping element diffusion barrier layer; the doping element diffusion barrier layer is used to block the doping element in the second sub-layer from diffusing into the first sub-layer and the tunneling oxide layer; The doping element diffusion barrier layer is disposed between the first sub-layer and the second sub-layer.

7. The solar cell according to claim 6, characterized in that: The doping element diffusion barrier layer is a silicon oxide layer.

8. The solar cell according to claim 6, characterized in that: The thickness of the doped element diffusion barrier layer is 1 nm to 2 nm.

9. A photovoltaic module, characterized in that: include: A plurality of solar cells connected in series and / or in parallel; At least one of the solar cells is a solar cell according to any one of claims 1 to 8.

10. A photovoltaic system, characterized in that: Comprising the photovoltaic module as claimed in claim 9.

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