TOPCon battery and preparation method thereof, photovoltaic module and photovoltaic system

Abstract

The embodiment of the invention relates to the technical field of solar cells, in particular to a TOPCon cell, a preparation method of the TOPCon cell, a photovoltaic module and a photovoltaic system. The TOPCon battery comprises a semiconductor substrate, and grid lines are arranged on the front face and the back face of the semiconductor substrate respectively. Each grid line comprises a fine grid, and each fine grid comprises a contact electrode for extracting current carriers; the contact electrodes of at least one of the fine grids on the front face and the back face are distributed in a discrete mode, and strip-shaped continuous electrodes are arranged on the tops of the contact electrodes distributed in the discrete mode. Compared with a fine grid which adopts continuous lines to extract current carriers, the contact electrodes of the fine grid are designed to be distributed in a discrete mode, on the premise that extraction and transportation of the current carriers are met, the overall size of the fine grid is reduced, and the use amount of silver paste is effectively reduced.

Description

Technical Field

[0001] The present application relates to the technical field of solar cells, and in particular to a TOPCon cell and a preparation method thereof, a photovoltaic module, and a photovoltaic system. Background Art

[0002] Photovoltaic power generation is a technology that uses solar cells to convert light energy into electrical energy. Solar energy is an inexhaustible renewable energy source that can generate electricity as long as there is light. It is green and environmentally friendly and will not pollute the environment. Using solar power generation can meet the sustainable development strategy.

[0003] With the rapid growth of the photovoltaic industry, the annual output of photovoltaic cells has increased exponentially. Most of the annual global mined silver supply is used in the photovoltaic industry, and the cost of silver paste has become the second largest material cost of solar cells.

[0004] To reduce the cost of silver paste, photovoltaic companies are looking for some alternative metals, such as copper plating, aluminum evaporation, silver-coated copper and other technologies. However, the equipment and process of copper plating and aluminum evaporation are immature, the equipment is expensive, and the pollution to the environment is also large. At present, mass production is difficult. And it is difficult to completely cover the copper particles with silver-coated copper technology. The exposed copper is easy to cause great damage to the polysilicon layer and semiconductor substrate.

[0005] It should be noted that the above content is not necessarily prior art, nor is it intended to limit the scope of patent protection of this application. Summary of the invention

[0006] The embodiments of the present application provide a TOPCon cell and a preparation method thereof, a photovoltaic module, and a photovoltaic system to solve or alleviate one or more of the technical problems raised above.

[0007] A first aspect of an embodiment of the present application provides a TOPCon battery, comprising a semiconductor substrate, wherein a gate line is provided on the front side and the back side of the semiconductor substrate respectively;

[0008] The gate lines all include fine gates, and the fine gates all include contact electrodes for extracting carriers;

[0009] The contact electrode of at least one of the fine grids on the front side and the back side is distributed in a discrete manner, and a strip-shaped continuous electrode is provided on the top of the discretely distributed contact electrode.

[0010] In the first aspect of the embodiments of the present application, compared with the fine grid using continuous lines to extract carriers, the embodiments of the present application design the contact electrodes of the fine grid to be discretely distributed. Under the premise of satisfying the extraction and transportation of carriers, the overall volume of the fine grid is reduced, effectively reducing the amount of silver paste used.

[0011] A second aspect of the embodiment of the present application provides a method for preparing a TOPCon battery, comprising the following operations:

[0012] Providing a semiconductor substrate, and cleaning and polishing the back side of the semiconductor substrate;

[0013] A silicon oxide film is prepared on the back side of the semiconductor substrate as a first tunneling oxide layer, and a polysilicon layer is grown on the first tunneling oxide layer to obtain a first polysilicon layer;

[0014] Performing a first doping on the back side to form a first doped polysilicon layer on the first polysilicon layer, and then removing the borosilicate glass or phosphosilicate glass;

[0015] Preparing a first aluminum oxide layer and a first silicon nitride layer on the first doped polysilicon layer as a first passivation layer;

[0016] The laser is used to partially open the first passivation layer to obtain discretely distributed holes;

[0017] Printing a first contact electrode in the hole using silver paste, and then sintering it;

[0018] Then, a copper paste or an aluminum paste is used to print a strip-shaped first electrode, wherein the first electrode is used to connect the first contact electrodes in the same row, and then the first electrode is sintered to form a strip-shaped first electrode; and / or

[0019] Cleaning and texturing the front side of the semiconductor substrate;

[0020] Prepare a silicon oxide film on the front side of the semiconductor substrate as a second tunneling oxide layer;

[0021] growing a polysilicon layer on the second tunnel oxide layer to obtain a second polysilicon layer;

[0022] Printing a mask layer on the second polysilicon layer in the shape of a preset discrete contact electrode, then removing the second tunneling oxide layer and the second polysilicon layer on the front side not covered by the mask layer, and then removing the mask layer;

[0023] Performing second diffusion doping to form an emitter in the area of ​​the front surface not covered by the mask layer, and forming the second polysilicon layer into a second doped polysilicon layer, and then removing the borosilicate glass or phosphosilicate glass;

[0024] Preparing a second aluminum oxide layer and a second silicon nitride layer on the emitter as a second passivation layer;

[0025] Printing a second contact electrode on the second doped polysilicon layer using silver paste, and sintering to form the second contact electrode after printing;

[0026] Then, a copper paste or an aluminum paste is used to print a strip-shaped second electrode, wherein the second electrode is used to connect the second contact electrodes in the same row, and the second electrode is sintered after printing.

[0027] In the second aspect of the embodiment of the present application, a TOPCon battery with discrete contact electrodes on the front or / and back is prepared. Since the back contact is reduced, the passivation layer area that needs to be destroyed is smaller, thereby reducing the amount of charge recombination and increasing the open circuit voltage; and the front side uses fewer contact passivation structures, which reduces parasitic absorption and increases short-circuit current. In the second aspect of the embodiment of the present application, the prepared TOPCon battery requires less silver paste and also improves performance.

[0028] A third aspect of an embodiment of the present application provides a photovoltaic module, which includes the TOPCon cell as described above.

[0029] A fourth aspect of an embodiment of the present application provides a photovoltaic system, comprising the photovoltaic assembly as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in the present application and should not be regarded as limiting the scope of the present application.

[0031] Figure 1 It is a schematic diagram of the structure of the TOPCon battery provided in the embodiment of the present application;

[0032] Figure 2 It is a schematic diagram of the structure of discrete holes provided in an embodiment of the present application.

[0033] Description of reference numerals:

[0034] 1-semiconductor substrate; 2-first tunneling oxide layer; 3-first doped polysilicon layer; 4-first aluminum oxide layer; 5-first silicon nitride layer; 6-first contact electrode; 7-first electrode; 8-second tunneling oxide layer; 9-second doped polysilicon layer; 10-emitter; 11-second aluminum oxide layer; 12-second silicon nitride layer; 13-second contact electrode; 14-second electrode. DETAILED DESCRIPTION

[0035] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings. In the accompanying drawings, for clarity, the sizes of layers, regions, elements and their relative sizes may be exaggerated. Wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limitations on the present application. It should be noted that, in the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

[0036] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. When the second element, component, region, layer or part is discussed, it does not indicate that the present application necessarily has the first element, component, region, layer or part.

[0037] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0038] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein, for example. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0039] In the present application, when it comes to a numerical interval (i.e., a numerical range), unless otherwise specified, the distribution of the optional numerical values ​​in the numerical interval is considered to be continuous, and includes the two numerical endpoints (i.e., the minimum and maximum values) of the numerical interval, and each numerical value between the two numerical endpoints. Unless otherwise specified, when the numerical interval only refers to an integer in the numerical interval, it includes the two endpoint integers of the numerical range, and each integer between the two endpoints, which is equivalent to directly listing each integer. When multiple numerical ranges are provided to describe features or characteristics, these numerical ranges can be merged. In other words, unless otherwise specified, the numerical range disclosed in the present application should be understood to include any and all sub-ranges included therein. The "numerical value" in the numerical interval can be any quantitative value, such as a number, a percentage, a ratio, etc. "Numerical interval" allows for broadly including quantitative intervals such as percentage intervals, ratio intervals, and ratio intervals.

[0040] The embodiment of the present application provides a TOPCon cell and a preparation method thereof, a photovoltaic module, and a technical solution of a photovoltaic system. Based on this, the amount of silver paste used is reduced and the performance of the TOPCon cell is improved. See below for details.

[0041] Hereinafter, exemplary embodiments according to the present application will be described in more detail with reference to the accompanying drawings. It should be noted that these exemplary embodiments can be implemented in many different forms and should not be construed as being limited to the embodiments described herein.

[0042] like Figure 1 As shown, an embodiment of the present application provides a schematic structural diagram of a TOPCon battery. The TOPCon battery may include: a semiconductor substrate, wherein the front and back sides of the semiconductor substrate are respectively provided with gate lines;

[0043] The gate lines each include a main gate and a fine gate, all the fine gates are gathered on the main gate, and the fine gates each include a contact electrode for extracting carriers;

[0044] The contact electrode of at least one of the fine grids on the front side and the back side is distributed in a discrete manner, and a strip-shaped continuous electrode is provided on the top of the discretely distributed contact electrode.

[0045] Compared with the fine gate using continuous lines to directly contact the doped polysilicon layer on the semiconductor substrate, the embodiment of the present application designs the contact electrode of the fine gate to be distributed in a discrete manner. Under the premise of satisfying the extraction and transportation of carriers, the volume of the fine gate is reduced as a whole, effectively reducing the amount of silver paste. In addition, due to the reduced contact formation, the passivation layer area that needs to be destroyed is less, thereby reducing the amount of charge recombination and increasing the open circuit voltage.

[0046] It is worth noting that on the front or back side, the fine grids are arranged in parallel, each row of fine grids is connected by a main grid, and the main grids are also arranged in parallel. For example, there are 160 to 190 fine grids independently, and 15 to 25 main grids independently.

[0047] In some embodiments, the arrangement of the discretely distributed contact electrodes is adapted to the semiconductor substrate. The front passivation contact structures are arranged in a row along a first direction, and the first direction is the direction of the front fine grid. Similarly, the discretely distributed contact electrodes are also arranged in a row along the first direction, thereby facilitating the printing of strip-shaped continuous electrodes above the discretely distributed contact electrodes. The back contact electrodes are also discretely distributed along the back fine grid direction. For example, see Figure 2 When the semiconductor substrate is a regular rectangle, the discrete holes are arranged parallel to the two sides of the semiconductor substrate. Thus, the shape of the gate line electrode is relatively regular. At this time, the contact electrodes are all discrete points on the strip line, and the fine gate can establish sufficient contact with the semiconductor substrate.

[0048] The embodiment of the present application does not limit the shape of the contact electrode. For example, Figure 2 The positive projection of the middle contact electrode on the semiconductor substrate is a rectangle, which is convenient for printing and forming.

[0049] The principle of setting the total area of ​​all the contact electrodes is to reduce the total area of ​​all the contact electrodes as much as possible under the premise of satisfying carrier extraction and transportation, thereby achieving the purpose of reducing the amount of silver paste. Preferably, the total area of ​​all the contact electrodes accounts for 2% to 4% of the front area of ​​the semiconductor substrate, for example, it can be 2%, 3%, 4%, etc. If the total area of ​​all the contact electrodes accounts for less than 2% of the front area of ​​the semiconductor substrate, it will affect the carrier extraction and transportation. If the total area of ​​all the contact electrodes accounts for more than 4% of the front area of ​​the semiconductor substrate, the ability of carrier extraction and transportation will no longer increase as the total area of ​​all the contact electrodes increases. It can be understood that the total area of ​​all the contact electrodes accounts for 2% to 4% of the front area of ​​the semiconductor substrate, including: the total area of ​​all the contact electrodes located on the front accounts for 2% to 4% of the front area of ​​the semiconductor substrate; the total area of ​​all the contact electrodes located on the back accounts for 2% to 4% of the back area of ​​the semiconductor substrate.

[0050] In some embodiments, see Figure 1 The front passivation contact structure of the semiconductor substrate is distributed in a discrete manner, and the front passivation contact structure includes a second tunneling oxide layer 8 and a second doped polysilicon layer 9 stacked in sequence; a second contact electrode 13 is provided on each passivation contact structure; the remaining area of ​​the front side of the semiconductor substrate is stacked with an emitter 10 and a second passivation layer in sequence; the top of each row of second contact electrodes 13 is connected by a strip-shaped second electrode 14; wherein the doping type of the emitter 10 and the doping type of the second doped polysilicon layer 9 are opposite to the doping type of the semiconductor substrate. Compared with the existing linearly distributed front passivation contact structure, the embodiment of the present application reduces the area of ​​the front passivation contact structure. Therefore, it is beneficial to reduce the parasitic absorption of the front passivation contact structure and increase the short-circuit current.

[0051] Furthermore, the second passivation layer includes a second aluminum oxide layer 11 and a second silicon nitride layer 12 stacked in sequence, thereby reducing the recombination of charges on the front side.

[0052] Furthermore, the second contact electrode 13 is made of silver paste; the second electrode 14 is made of copper paste or aluminum paste. Thus, the carrier extraction and transportation capacity can be met and silver paste can be saved. In addition, the corrosion of silver paste during the sintering process is much weaker than that of copper paste and aluminum paste, and the damage to the semiconductor substrate is minimal, which will not cause a decrease in the open circuit voltage.

[0053] Furthermore, the thickness of the second tunnel oxide layer 8 is 0.4 nm to 2 nm, for example, 0.4 nm, 0.5 nm, 1 nm, 1.5 nm, 2 nm, so as to have good passivation ability and facilitate carriers to pass through and be collected.

[0054] Furthermore, the thickness of the second doped polysilicon layer 9 is 60 nm to 130 nm, for example, 60 nm, 80 nm, 110 nm, 130 nm, etc. Thus, the risk of polysilicon burn-through is reduced while the parasitic absorption is reduced.

[0055] In some embodiments, in a TOPCon cell, the back contact passivation structure of the semiconductor substrate includes a first tunneling oxide layer 2 and a first doped polysilicon layer 3 stacked in sequence, and a first passivation layer is provided on the back contact passivation structure; a plurality of rows of discretely distributed holes are provided on the first passivation layer, and the holes are filled with first contact electrodes 6, and the top of the first contact electrodes 6 is located on the first passivation layer, and the top of each row of first contact electrodes 6 is connected by a strip-shaped first electrode 7; wherein the doping type of the first doped polysilicon layer 3 is the same as the doping type of the semiconductor substrate. Therefore, the first contact electrode 6 on the back side is also distributed in a discrete manner, reducing the amount of back electrode slurry used.

[0056] Furthermore, the first passivation layer includes a first aluminum oxide layer 4 and a first silicon nitride layer 5 which are sequentially stacked on the first doped polysilicon layer 3. Thus, the recombination of charges on the back side is reduced.

[0057] Furthermore, the first contact electrode 6 is made of silver paste, and the first electrode 7 is made of copper paste or aluminum paste. Therefore, the silver paste as the contact electrode can form a better contact while reducing the damage to the semiconductor substrate, while the material of the first electrode 7 saves cost and can well guide the carriers of the contact electrode.

[0058] Furthermore, the thickness of the first tunnel oxide layer 2 is 0.8 nm to 2 nm, for example, 0.8 nm, 1 nm, 1.5 nm, 2 nm, so that it has good passivation ability and facilitates carriers to pass through and realize collection.

[0059] Furthermore, the thickness of the first doped polysilicon layer 3 is 60 nm to 130 nm, for example, 60 nm, 80 nm, 110 nm, 130 nm, etc. Thus, the risk of polysilicon burn-through is reduced while the parasitic absorption is reduced.

[0060] It is worth noting that the semiconductor substrate can be N-type silicon or P-type silicon. Taking the semiconductor substrate as N-type silicon as an example, the doping type of the first doped polysilicon layer 3 located on the front side is the same as the doping type of the semiconductor substrate, which is N + The doping type of the second doped polysilicon layer 9 located on the back is opposite to the doping type of the semiconductor substrate, which is P + The semiconductor substrate may be a P-type silicon, which will not be described in detail herein. In addition, the front side in the present application refers to the light-receiving side, and the back side refers to the backlight side.

[0061] The present application embodiment provides a method for preparing a TOPCon battery, comprising the following operations:

[0062] Cleaning and polishing the back side of the semiconductor substrate;

[0063] A silicon oxide film is prepared on the back side of the semiconductor substrate as a first tunneling oxide layer 2, and a polysilicon layer is grown on the first tunneling oxide layer 2 to obtain a first polysilicon layer;

[0064] Performing a first doping on the back side to form a first doped polysilicon layer 3 on the first polysilicon layer, and then removing the borosilicate glass or phosphosilicate glass;

[0065] A first aluminum oxide layer 4 and a first silicon nitride layer 5 are formed on the first doped polysilicon layer 3 as a first passivation layer;

[0066] The laser is used to partially open the first passivation layer to obtain discretely distributed holes;

[0067] Printing the first contact electrode 6 in the hole with silver paste, and then sintering it;

[0068] Then, a strip-shaped first electrode 7 and a main grid are printed using copper paste or aluminum paste, wherein the first electrode 7 is used to connect the first contact electrodes 6 in the same row, and the main grid is used to connect the first electrodes 7, and then sintered to form;

[0069] Cleaning and texturing the front side of the semiconductor substrate;

[0070] Prepare a silicon oxide film on the front side of the semiconductor substrate as a second tunneling oxide layer 8;

[0071] growing a polysilicon layer on the second tunnel oxide layer 8 to obtain a second polysilicon layer;

[0072] A mask layer is printed on the obtained second polysilicon layer according to a preset discrete contact electrode, and then the second tunnel oxide layer 8 and the second polysilicon layer on the front side not covered by the mask layer are removed, and then the mask layer is removed;

[0073] Performing second diffusion doping to form an emitter 10 in the area of ​​the front side not covered by the mask layer, and forming the second doped polysilicon layer 9 from the second polysilicon layer, and then removing the borosilicate glass or phosphosilicate glass;

[0074] A second aluminum oxide layer 11 and a second silicon nitride layer 12 are formed on the emitter 10 as a second passivation layer;

[0075] Printing a second contact electrode 13 on the second doped polysilicon layer 9 by using silver paste, and sintering the printed second contact electrode 13;

[0076] Then, copper paste or aluminum paste is used to print strip-shaped second electrodes 14 and main grids. The second electrodes 14 are used to connect the second contact electrodes 13 in the same row, and the main grids are used to connect the second electrodes 14. After printing, sintering is performed.

[0077] In the embodiment of the present application, a mask method is used on the front side to prepare a discrete front contact passivation structure, and silver paste is used as the second contact electrode, and copper paste or aluminum paste is used as the second electrode on the front side; laser mold opening is used on the back side to form discrete holes on the first passivation layer as the area of ​​the first contact electrode. On the basis of achieving full contact, the damage to the first passivation layer is reduced, the charge recombination is reduced, and the open circuit voltage is improved.

[0078] Furthermore, the sintering temperature after the silver paste printing is completed is 670° C. to 700° C., for example, 670° C., 680° C., 700° C., etc. Thus, the contact electrode is formed.

[0079] Furthermore, the sintering temperature after printing the copper paste or aluminum paste is 140° C. to 160° C., such as 140° C., 150° C., 160° C., etc., and the sintering time is 4 min to 6 min., such as 4 min, 5 min, 6 min, etc. Thus, the sintering of the first electrode and the second electrode is performed at a relatively low temperature, thereby reducing damage to the semiconductor substrate.

[0080] The following will conduct performance tests on the manufacturing method of the TOPCon battery provided in the embodiments of the present application and related comparative examples.

[0081] [Example 1]

[0082] The specific preparation process of TOPCon battery is as follows:

[0083] Step 1: providing a 1 μm N-type silicon wafer as a semiconductor substrate 1, and cleaning and polishing the back side of the semiconductor substrate 1;

[0084] Step 2: preparing a 1 nm thick silicon oxide film on the back side of the semiconductor substrate 1 as a first tunneling oxide layer 2, and growing a 90 nm thick polysilicon layer on the first tunneling oxide layer 2 to obtain a first polysilicon layer;

[0085] Step 3: performing a first doping of phosphorus element on the back side to form a first doped polysilicon layer 3 on the first polysilicon layer, and then removing the phosphorus silicon glass;

[0086] Step 4: preparing a first aluminum oxide layer 4 with a thickness of 5 nm and a first silicon nitride layer 5 with a thickness of 35 nm on the first doped polysilicon layer 3 as a first passivation layer;

[0087] Step 5: Use laser to partially open the first passivation layer to obtain discretely distributed holes;

[0088] The holes are evenly distributed on the first passivation layer. The holes are cuboid-shaped. The two-dimensional size of the holes is 25 μm × 22 μm. The thickness is the same as the thickness of the first passivation layer. The total area of ​​all hole openings accounts for 2% of the area of ​​the first passivation layer.

[0089] Step 6: Print the first contact electrode 6 in the hole with silver paste, and then sinter at 680° C. for 5 minutes; wherein the silver paste is purchased from Guangzhou Ruxing Technology Co., Ltd. Model RX2835 silver paste;

[0090] Step 7: Use copper paste to print strip-shaped first electrodes 7 and main grids, the first electrodes 7 are used to connect the first contact electrodes 6 in the same row, and the main grids are used to connect the first electrodes 7, and then sintered at 150° C. for 5 minutes; wherein the copper paste is purchased from Copprint Company, model LF-371 copper paste;

[0091] Step 8: Cleaning and texturing the front surface of the semiconductor substrate;

[0092] Step 9: preparing a silicon oxide film with a thickness of 1.5 nm on the front side of the semiconductor substrate as the second tunneling oxide layer 8;

[0093] Step 10: growing a polysilicon layer with a thickness of 60 nm on the second tunneling oxide layer 8 to obtain a second polysilicon layer;

[0094] Step 11: Printing a mask layer on the obtained second polysilicon layer according to the preset discrete contact electrodes, then removing the second tunneling oxide layer 8 and the second polysilicon layer that are not covered by the mask layer on the front side, and then removing the mask layer; wherein the discrete contact electrodes are evenly distributed on the second polysilicon layer, the shape of the contact electrodes is rectangular, and the size is 28μm×18μm. The area of ​​all contact electrodes accounts for 4% of the area of ​​the second polysilicon layer.

[0095] Step 12: performing a second diffusion doping of boron element to form an emitter 10 with a thickness of 240 nm in the area of ​​the front side not covered by the mask layer, and forming the second polysilicon layer into a second doped polysilicon layer 9, and then removing the borosilicate glass;

[0096] Step 13: preparing a second aluminum oxide layer 11 with a thickness of 5 nm and a second silicon nitride layer 12 with a thickness of 35 nm on the emitter 10 as a second passivation layer;

[0097] Step 14: printing a second contact electrode 13 on the second doped polysilicon layer 9 using silver paste, and sintering at 700° C. for 3 minutes after printing;

[0098] Step 14: Then, a strip-shaped second electrode 14 and a main grid are printed with aluminum paste. The second electrode 14 is used to connect the second contact electrodes 13 in the same row, and the main grid is used for the second electrode 14. After printing, the strip-shaped second electrode 14 is sintered at 160° C. for 6 minutes to form a shape.

[0099] The aluminum paste was purchased from Guangzhou Ruxing Technology Co., Ltd. with the model number of RX8401.

[0100] [Example 2]

[0101] The other steps are the same as those in Example 1, except that in step 5, the total area of ​​all hole openings accounts for 3% of the area of ​​the first passivation layer.

[0102] In step 11: the area of ​​all contact electrodes accounts for 3% of the area of ​​the second polysilicon layer.

[0103] [Example 3]

[0104] The other steps are the same as those in Example 1, except that in step 5, the total area of ​​all hole openings accounts for 1% of the area of ​​the first passivation layer.

[0105] In step 11: the area of ​​all contact electrodes accounts for 1% of the area of ​​the second polysilicon layer.

[0106] [Example 4]

[0107] The other steps are the same as those in Example 1, except that in step 5, the total area of ​​all hole openings accounts for 5% of the area of ​​the first passivation layer.

[0108] In step 11: the area of ​​all contact electrodes accounts for 5% of the area of ​​the second polysilicon layer.

[0109] [Example 5]

[0110] The other steps are the same as those in Example 1, except that, in step 11: a mask layer is printed on the second polysilicon layer according to discrete continuous linear contact electrodes, and then the second tunneling oxide layer 8 and the second polysilicon layer on the front side not covered by the mask layer are removed, and then the mask layer is removed; wherein the continuous linear contact electrodes are the continuity of the discrete contact electrodes in step 11 of Example 1.

[0111] [Example 6]

[0112] The other steps are the same as those in Example 1, except that, in step 5: a laser is used to partially open the first passivation layer to obtain a plurality of linear holes;

[0113] The linear holes are the continuation of the discretely distributed holes in Example 1.

[0114] [Comparative Example 1]

[0115] The other steps are the same as those in Example 1, except that:

[0116] Step 5: Use laser to partially open the first passivation layer to obtain a plurality of linear holes; wherein the linear holes are the continuity of the discretely distributed holes in Example 1.

[0117] Step 11: Print a mask layer on the second polysilicon layer according to discrete and continuous linear contact electrodes, then remove the second tunneling oxide layer 8 and the second polysilicon layer on the front side that are not covered by the mask layer, and then remove the mask layer; wherein the continuous linear contact electrodes are the line segments where the discrete contact electrodes are located in step 11 of Example 1.

[0118]

Test example

[0119] The TOPCon cells of Examples 1 to 6 and Comparative Example 1 were subjected to IV tests. The IV test conditions were a light irradiance of 1000 W / m 2 , temperature is 25℃±10℃, relative humidity: ≤85%,

[0120] The implementation standard is GB / T17683.1-1999, and the test results are shown in Table 1. The amounts of silver paste used in Examples 1 to 6 and Comparative Example 1 are also shown in Table 1.

[0121] Table 1:

[0122]

[0123]

[0124] It can be seen from Table 1 that the filling factor and conversion efficiency of Examples 1 to 6 are limited or even improved compared with Comparative Example 1. At the same time, the short-circuit current of Examples 1 to 6 is improved to varying degrees. The above description shows that the embodiments of the present application use discrete contact electrodes, which reduces the silver paste in terms of materials and helps to improve the short-circuit current. Furthermore, compared with Example 1, the total area of ​​the contact electrodes on the front and back of Example 3 is reduced to 1%, and the amount of silver paste used is further reduced, but the filling factor and conversion efficiency also decrease accordingly. Compared with Example 1, the total area of ​​the contact electrodes on the front and back of Example 4 is increased to 5%, and the filling factor and conversion efficiency are improved to a relatively limited extent, but the amount of silver paste is increased. Furthermore, in Example 3, due to the small opening, some holes do not form silver-silicon contact, resulting in poor filling. In Example 4, the front and back openings are large, the slurry corrodes the substrate more, the open circuit voltage decreases, and the large polysilicon area of ​​the opening increases, the parasitic absorption increases, and the short-circuit current decreases. The larger the opening, the contact slurry forms a sufficient contact resistance area, the contact resistance is small, and the filling factor is high. In Example 5, the corrosion of the substrate by the entire gate line slurry on the back side is greater, and the opening voltage is further reduced. At the same time, the polysilicon area is increased, and the parasitic absorption is increased, resulting in a decrease in short-circuit current. In Example 6, after a continuous electrode is used on the front side, the slurry increases the corrosion of the substrate, the open circuit voltage is reduced, and at the same time, the polysilicon area of ​​the opening is increased, and the parasitic absorption is increased, resulting in a decrease in short-circuit current. In Comparative Example 1, since there is no passivation structure under the front electrode, the composite is larger, and the slurry corrodes more, resulting in a smaller opening voltage, but the resistance of all silver gate lines is smaller and the filling is higher.

[0125] The embodiment of the present application may also provide a photovoltaic module (not shown), the photovoltaic module comprising the TOPCon cell as described above. The TOPCon cell may be connected in series and / or in parallel with one or more other solar cells in a preset manner. Among them, a plurality of cells may form a cell string, and adjacent cells may be connected together by string welding.

[0126] The embodiment of the present application can provide a photovoltaic system, including the photovoltaic components in any of the above embodiments. The advantages of the above photovoltaic components are also possessed by the photovoltaic system, which will not be repeated here. The above photovoltaic system has a wide range of applications, not only limited to photovoltaic power stations, such as ground power stations, rooftop power stations and water power stations, but also includes various equipment and devices that use solar energy to generate electricity, such as user solar power supplies, solar street lights, solar cars and solar buildings. Of course, it can be understood that the application scenarios of the photovoltaic system are not limited to this, that is to say, the photovoltaic system can be used in all fields where solar energy is required for power generation. Taking the photovoltaic power generation system network as an example, the photovoltaic system may include a photovoltaic array, a junction box and an inverter. The photovoltaic array may be an array combination of multiple photovoltaic components. For example, multiple photovoltaic components may form multiple photovoltaic arrays. The photovoltaic array is connected to a junction box. The junction box can converge the current generated by the photovoltaic array. The converged current flows through the inverter and is converted into the alternating current required by the mains power grid, and then connected to the mains network to realize solar power supply.

[0127] It should be noted that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. The orientation words "inside" and "outside" refer to the inside and outside relative to the outline of each component itself. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Therefore, the exemplary term "above..." can include both "above..." and "below..." orientations. The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used here are interpreted accordingly.

[0128] It should also be noted that "one embodiment", "another embodiment", "embodiment", etc. mentioned in this application refer to the specific features, structures or characteristics described in conjunction with the embodiment included in at least one embodiment generally described in this application. The same expression appearing in multiple places in the specification does not necessarily refer to the same embodiment. Further, when describing a specific feature, structure or characteristic in conjunction with any embodiment, it is claimed that the realization of such feature, structure or characteristic in conjunction with other embodiments also falls within the scope of this application.

[0129] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0130] It should also be noted that the above are only preferred embodiments of the present application, and the patent protection scope of the present application is not limited thereto. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A TOPCon battery, characterized in that: It comprises a semiconductor substrate, wherein the front side and the back side of the semiconductor substrate are respectively provided with gate lines; The gate lines all include fine gates, and the fine gates all include contact electrodes for extracting carriers; The contact electrodes of at least one of the front fine grid and the back fine grid are distributed in a discrete manner, and a strip-shaped continuous electrode is provided on the top of the discretely distributed contact electrodes.

2. The TOPCon battery according to claim 1, characterized in that The total area of ​​all the contact electrodes located on the front side accounts for 2% to 4% of the area of ​​the front side of the semiconductor substrate; and / or The total area of ​​all the contact electrodes located on the back side accounts for 2% to 4% of the area of ​​the back side of the semiconductor substrate.

3. The TOPCon battery according to claim 1, characterized in that The contact electrodes of the front fine grid are arranged in a row in a first direction, the first direction being the direction in which the front fine grid is located; and / or The contact electrodes of the fine grid on the back side are arranged in a row in a second direction, and the second direction is the direction in which the fine grid on the back side is located.

4. The TOPCon battery according to claim 3, characterized in that The semiconductor substrate has a front passivation contact region, the front passivation contact region has a front passivation contact structure, the front passivation contact structure is discretely distributed, and the front passivation contact structure comprises a second tunneling oxide layer (8) and a second doped polysilicon layer (9) stacked in sequence; each of the passivation contact structures is provided with a second contact electrode (13); An emitter electrode (10) and a second passivation layer are sequentially stacked in the remaining area of ​​the front surface of the semiconductor substrate, and the remaining area is the area of ​​the front surface of the semiconductor substrate except the area where the front passivation contact structure is located; The tops of each row of second contact electrodes (13) are connected by strip-shaped second electrodes (14); The doping type of the emitter (10) and the doping type of the second doped polysilicon layer (9) are opposite to the doping type of the semiconductor substrate.

5. The TOPCon battery according to claim 4, characterized in that: The second passivation layer comprises a second aluminum oxide layer (11) and a second silicon nitride layer (12) stacked in sequence; and / or The second contact electrode (13) is made of silver paste, and the second electrode (14) is made of copper paste or aluminum paste; and / or The thickness of the second tunnel oxide layer (8) is 0.8 nm to 2 nm; and / or The thickness of the second doped polysilicon layer (9) is 60nm-130nm.

6. The TOPCon battery according to claim 3, characterized in that The semiconductor substrate has a back contact passivation structure, the back contact passivation structure comprises a first tunneling oxide layer (2) and a first doped polysilicon layer (3) stacked in sequence, and a first passivation layer is provided on the back contact passivation structure; The first passivation layer is provided with a plurality of rows of discretely distributed holes, each of the holes being provided with a first contact electrode (6), the top of the first contact electrode (6) being located above the first passivation layer, and the top of each row of the first contact electrodes (6) being connected by a strip-shaped first electrode (7); The doping type of the first doped polysilicon layer (3) is the same as the doping type of the semiconductor substrate.

7. The TOPCon battery according to claim 6, characterized in that The first passivation layer comprises a first aluminum oxide layer (4) and a first silicon nitride layer (5) which are sequentially stacked on the first doped polysilicon layer (3); and / or The first contact electrode (6) is made of silver paste, and the first electrode (7) is made of copper paste or aluminum paste; and / or The thickness of the first tunnel oxide layer (2) is 0.8 nm to 2 nm; and / or The thickness of the first doped polysilicon layer (3) is 60 nm to 130 nm.

8. A method for preparing a TOPCon battery, characterized in that: The following operations are included: A silicon oxide film is prepared on the back side of a semiconductor substrate as a first tunnel oxide layer (2), and a polysilicon layer is grown on the first tunnel oxide layer (2) to obtain a first polysilicon layer; Performing a first doping on the back side to form a first doped polysilicon layer (3) on the first polysilicon layer, and then removing the borosilicate glass or phosphosilicate glass; Preparing a first aluminum oxide layer (4) and a first silicon nitride layer (5) on the first doped polysilicon layer (3) as a first passivation layer; The laser is used to partially open the first passivation layer to obtain discretely distributed holes; Printing a first contact electrode (6) in the hole using silver paste, and then sintering it into shape; Then, a first strip-shaped electrode (7) is printed using copper paste or aluminum paste, wherein the first electrode (7) is used to connect the first contact electrodes (6) in the same row, and then sintered into shape; and / or A silicon oxide film is prepared on the front surface of the semiconductor substrate as a second tunneling oxide layer (8); growing a polysilicon layer on the second tunnel oxide layer (8) to obtain a second polysilicon layer; Printing a mask layer on the second polysilicon layer in the shape of a preset discrete contact electrode, then removing the second tunneling oxide layer (8) and the second polysilicon layer on the front side not covered by the mask layer, and then removing the mask layer; Performing second diffusion doping to form an emitter (10) in a region of the front surface not covered by the mask layer, and forming the second polysilicon layer into a second doped polysilicon layer (9), and then removing the borosilicate glass or phosphosilicate glass; Preparing a second aluminum oxide layer (11) and a second silicon nitride layer (12) on the emitter (10) as a second passivation layer; Printing a second contact electrode (13) on the second doped polysilicon layer (9) using silver paste, and sintering the printed second contact electrode (13) to form the second contact electrode; Then, a strip-shaped second electrode (14) is printed using copper paste or aluminum paste, wherein the second electrode (14) is used to connect the second contact electrodes (13) in the same row, and is sintered after printing.

9. The method for preparing a TOPCon battery according to claim 8, characterized in that: The sintering temperature after silver paste printing is 670℃~700℃; and / or The sintering temperature after copper paste or aluminum paste printing is 140°C to 160°C, and the sintering time is 4min to 6min.

10. The method for preparing a TOPCon battery according to claim 9, characterized in that: The laser is used to partially open the first passivation layer to obtain discretely distributed rectangular holes, wherein the rectangular holes are 25 μm to 30 μm in length and 18 μm to 22 μm in width.

11. A photovoltaic module, characterized in that: The photovoltaic module comprises the TOPCon cell according to any one of claims 1 to 7.

12. A photovoltaic system, characterized in that: The photovoltaic system comprises the photovoltaic assembly according to claim 11.

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