Rectifier

Abstract

A rectifier includes a substrate, a first transistor, a second transistor, a first gate contact socket, a first source contact socket, a first metal wire, and an inductor. The first transistor includes a first gate structure, a first source region, and a first drain region. The second transistor includes a second gate structure, a second source region, and a second drain region. The first gate contact socket is electrically connected to the first gate structure. The first source contact socket is electrically connected to the first source region. The first metal wire is in contact with a top surface of the first gate contact receptacle and a top surface of the first source contact receptacle. The inductor is electrically connected to a first drain region of the first transistor and a second source region of the second transistor.

Description

Technical Field

[0001] The present disclosure relates to a rectifier. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generation after generation of ICs. Each generation has smaller and more complex circuits than the previous generation. However, these advances will increase the complexity of processing and manufacturing ICs. In the process of IC development, functional density (i.e., the number of interconnected devices per chip area) generally increases, while geometric size (i.e., the smallest component (or wiring) that can be produced using a manufacturing process) decreases. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. However, as feature sizes continue to decrease, manufacturing processes continue to become more difficult to perform. Therefore, it is a challenge to form reliable semiconductor devices with smaller and smaller sizes. Utility Model Content

[0003] In some embodiments of the present disclosure, a rectifier includes a substrate, a first transistor, a second transistor, a first gate contact socket, a first source contact socket, a first metal wiring, and an inductor. The first transistor is above the substrate and includes a first gate structure, and a first source region and a first drain region in the substrate and on opposite sides of the first gate structure. The second transistor is above the substrate and includes a second gate structure, and a second source region and a second drain region in the substrate and on opposite sides of the second gate structure. The first gate contact socket is electrically connected to the first gate structure. The first source contact socket is electrically connected to the first source region. The first metal wiring contacts a top surface of the first gate contact socket and a top surface of the first source contact socket. The inductor is electrically connected to the first drain region of the first transistor and the second source region of the second transistor.

[0004] In some embodiments of the present disclosure, a rectifier includes a substrate, a high-side transistor, a low-side transistor, and an inductor. The high-side transistor is above the substrate and includes a first gate structure, a first source region and a first drain region in the substrate and on opposite sides of the first gate structure, and a first pickup region in the substrate and laterally adjacent to the first source region along a first direction. The low-side transistor is above the substrate and includes a second gate structure, a second source region and a second drain region in the substrate and on opposite sides of the second gate structure, and a second pickup region in the substrate and laterally adjacent to the second source region along a second direction perpendicular to the first direction. The inductor is electrically connected to the first source region of the high-side transistor and the second drain region of the low-side transistor.

[0005] In some embodiments of the present disclosure, a rectifier includes a substrate, a high-side transistor, a low-side transistor, and an inductor. The high-side transistor is above the substrate and includes a first gate structure, a first source region and a first drain region in the substrate and on opposite sides of the first gate structure, and a first pickup region in the substrate and laterally adjacent to the first source region along a first direction. The low-side transistor is above the substrate and includes a second gate structure, a second source region and a second drain region in the substrate and on opposite sides of the second gate structure. The inductor is electrically connected to the first source region of the high-side transistor and the second drain region of the low-side transistor. The first gate structure includes a first gate dielectric and a second gate dielectric adjacent to the first gate dielectric, wherein the first gate dielectric is thicker than the second gate dielectric. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of this disclosure are in accordance with the attached Figure 1 The following detailed description is best understood when read together. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a circuit diagram of a rectifier according to some embodiments of the present disclosure;

[0008] Figure 2A and Figure 2B illustrates different operation modes of a rectifier according to some embodiments of the present disclosure;

[0009] Figure 3A FIG. 1 is a top view of a rectifier according to some embodiments of the present disclosure;

[0010] FIG. 3B to FIG. 3E illustrates a cross-sectional view of a rectifier according to some embodiments of the present disclosure;

[0011] Figure 4 FIG. 1 is a top view of a rectifier according to some embodiments of the present disclosure;

[0012] FIG. 5A to FIG. 18E is a schematic diagram of a rectifier at various stages of manufacture according to some embodiments of the present disclosure;

[0013] Fig.19A and Fig.19B FIG. 1 is a cross-sectional view of a rectifier according to some embodiments of the present disclosure.

[0014]

Explanation of symbols

[0015] 10: Rectifier

[0016] 20: Inductor

[0017] 30: Capacitor

[0018] 40: Resistor

[0019] 50:Drive

[0020] 100:Substrate

[0021] 100A: Zone 1

[0022] 100B: Zone 2

[0023] 105: Isolation Structure

[0024] 120:ILD layer

[0025] 202,204: Drift Zone

[0026] 206: Main area

[0027] 210A, 210B: Gate structure

[0028] 211: Gate dielectric layer

[0029] 212: Gate dielectric

[0030] 213: Gate dielectric layer

[0031] 214: Gate dielectric

[0032] 215: Gate electrode layer

[0033] 216: Gate electrode

[0034] 222,224,226,228: Gate spacer

[0035] 232,234: Protective layer

[0036] 240: Silicide layer

[0037] 252,254: Source region

[0038] 262,264: Drain region

[0039] 270: Pickup Area

[0040] 281,282,283,284,285,286,287: Contact socket

[0041] 292,294:Metal wiring

[0042] 302,304: Drift zone

[0043] 306: Main area

[0044] 310A, 310B: Gate structure

[0045] 311: Gate dielectric layer

[0046] 312: Gate dielectric

[0047] 313: Gate dielectric layer

[0048] 314: Gate dielectric

[0049] 315: Gate electrode layer

[0050] 316: Gate electrode

[0051] 322,324,326,328: Gate spacers

[0052] 332,334: Protective layer

[0053] 340: Silicide layer

[0054] 352: Source region

[0055] 352A,352B,352C:Partial

[0056] 362,364: Drain region

[0057] 370: Pickup Area

[0058] 370A,370B: Part 381,382,383,385,386,387: Contact socket 392,393,394: Metal wiring

[0059] B1: Main body

[0060] B2: Main body

[0061] D1: Drain

[0062] D2: Drain

[0063] G1: Gate

[0064] G2: Gate

[0065] I1, I2: Current path

[0066] L1, L2: lateral length

[0067] E1, E2: lateral length

[0068] MA1, MA2, MA3, MA4: patterned mask N1: node

[0069] O1, O2, O3, O4, O5, O6, O7, O8: Open

[0070] S1: Source

[0071] S2: Source

[0072] SW:Node

[0073] BB,CC,DD,EE:Line DETAILED DESCRIPTION

[0074] The following disclosure provides many different embodiments, or examples, for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature is formed in direct contact with the second feature, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0075] Additionally, for ease of description, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used herein to describe the relationship of one element or feature illustrated in the figures to another element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be similarly interpreted accordingly.

[0076] Figure 1 is a circuit diagram of a rectifier according to some embodiments of the present disclosure. An exemplary circuit diagram of a rectifier 10 is shown in the figure. In some embodiments, the rectifier 10 is a synchronous buck rectifier. The synchronous buck rectifier 10 includes a network of active and passive components coupled between an input terminal and an output terminal. The input terminal receives a regulated voltage Vin and generates a modulated voltage Vout at the output terminal.

[0077] Figure 1 The synchronous buck rectifier 10 shown in FIG. 1 includes a high-side (HS) transistor Q1 and a low-side (LS) transistor Q2. In some embodiments, the high-side transistor Q1 and the low-side transistor Q2 may be field-effect transistors (FETs), and thus the high-side transistor Q1 and the low-side transistor Q2 may also be referred to as a high-side field-effect transistor (HS FET) Q1 and a low-side field-effect transistor (LS FET) Q2, respectively.

[0078] The HS transistor Q1 and the LS transistor Q2 are connected in series and are connected across the supply voltage terminal Vin and the ground GND. In more detail, the drain D1 of the HS transistor Q1 is electrically connected to the supply voltage terminal Vin. The source S1 and the body B1 of the HS transistor Q1 are electrically connected to the node SW. In addition, the drain D2 of the LS transistor Q2 is electrically connected to the node SW. That is, the source S1 and the body B1 of the HS transistor Q1 are electrically connected to the drain D2 of the LS transistor Q2. The source S2 and the body B2 of the LS transistor Q2 are electrically connected to the ground GND. In some embodiments, the gate G1 of the HS transistor Q1 is electrically connected to the driver 50. In some embodiments, the driver 50 is used to supply (or stop supplying) a relatively high voltage level to turn on (or turn off) the HS transistor Q1. On the other hand, the gate G2 of the LS transistor Q2 is electrically connected to the source S2 and the body B2 of the LS transistor Q2.

[0079] The synchronous buck rectifier 10 further includes an inductor 20, a capacitor 30, and a resistor 40. In some embodiments, a first side of the inductor 20 is electrically connected to a node SW. That is, a first side of the inductor 20 is electrically connected to a source S1 and a body B1 of the HS transistor Q1 and a drain D2 of the LS transistor Q2. A second side of the inductor 20 is electrically connected to a node N1. In addition, a first side of the capacitor 30 is electrically connected to the node N1, and a second side of the capacitor 30 is electrically connected to the ground GND. Similarly, a first side of the resistor 40 is electrically connected to the node N1, and a second side of the resistor 40 is electrically connected to the ground GND. In some embodiments, the node N1 may also be referred to as an output voltage terminal. In some embodiments, the resistor 40 may simulate a load. The load may be attributed to a device connected to the synchronous buck rectifier 10, such as a commutation device. The combination of the inductor 20 and the capacitor 30 may ensure that the current through the load resistor 40 and the voltage across the load resistor 40 do not change instantaneously.

[0080] In some embodiments, LS transistor Q2 can work synchronously with HS transistor Q1 to controllably switch the inductor network of synchronous buck rectifier 10. For example, driver 50 is used to supply a control signal to gate G1 of HS transistor Q1 to periodically turn on and off HS transistor Q1.

[0081] Figure 2A and Figure 2B The diagrams illustrate different operating modes of a rectifier according to some embodiments of the present disclosure. Figure 2AAs shown in , in the first operation mode of the rectifier 10, the HS transistor Q1 is turned on, and the supply voltage level Vin will be transmitted to the node SW through the HS transistor Q1. For example, the driver 50 can supply a high voltage level to the gate G1 of the HS transistor Q1 to turn on the HS transistor Q1. Therefore, the node SW is at a high voltage level. At the same time, the gate G2 and the source S2 of the LS transistor Q2 are equipotential to 0V and will automatically turn off. In the first operation mode, the current path I1 flows from the supply voltage terminal Vin in the conducting direction through the HS transistor Q1 to the node SW. As shown in the current path I1, the current is blocked by the LS transistor Q2 and flows through the inductor 20.

[0082] When the rectifier 10 is operating in the first operating mode, if the gate-source voltage of the HS transistor Q1 is switched to a low level or OFF (eg, switched to V GS <V TH ), so that the gate G1 of the HS transistor Q1 is biased OFF, and the rectifier 10 is therefore switched to Figure 2B The second operating mode is shown in .

[0083] like Figure 2B As shown in , in the second operation mode of the rectifier 10, when the HS transistor Q1 is turned off, Vin is cut off, and the current at the node SW is also cut off sharply. However, due to the characteristics of the inductor 20, the inductor current of the inductor 20 cannot drop suddenly, so the current path will maintain the inductor current through the LS transistor Q2, as shown by the current path I2. Therefore, the voltage at the node SW can be reduced to a lower level (for example, -0.7V in some embodiments). In this case, the LS transistor Q2 will be turned on because the source and drain of the LS transistor Q2 have been reversed (the physical source acts as the drain, and the physical drain acts as the power supply), so that the LS transistor Q2 will be turned on to conduct the cyclic current from the inductor. In the second operation mode, the LS transistor Q2 can be equivalently referred to as a cyclic diode D W In more detail, because the gate G2 of the LS transistor Q2 is short-circuited with the source S2, the LS transistor Q2 may be automatically turned on without using an external driver to supply a turn-on voltage to the gate G2 of the LS transistor Q2.

[0084] In some embodiments of the present disclosure, electrically connecting the gate G2 of the LS transistor Q2 to the source S2 of the LS transistor Q2 can be advantageous in reducing power consumption. For example, because the gate G2 of the LS transistor Q2 and the source S2 are short-circuited, the LS transistor Q2 can be automatically turned on without using an external driver to supply a turn-on voltage to the gate G2 of the LS transistor Q2. In some embodiments where the gate G2 and the source S2 of the LS transistor Q2 are not electrically connected to each other, an additional driver can be designed to electrically switch the LS transistor Q2 instead of passive diode automatic switching, and thus driver loss problems may occur.

[0085] In addition, in embodiments where the gate G2 and source S2 of the LS transistor Q2 are not electrically connected to each other, it should be avoided that the HS transistor Q1 and the LS transistor Q2 are in the "ON" state at the same time, otherwise the circuit will be directly short-circuited from Vin to the ground GND, and the device may be catastrophically damaged. In this case, it is necessary to set a "dead time" during the switching between "ON" and "OFF" inside the HS transistor Q1 and the LS transistor Q2. For example, there is a time delay between the turn-off of the HS transistor Q1 and the turn-on of the LS transistor Q2. However, during the "dead time", the LS transistor Q2 has not yet turned on (for example, in the OFF state), and current can still pass through the parasitic body diode, which will cause diode reverse recovery loss (Qrr). As the switching frequency reaches MHz, the Qrr loss increases and becomes one of the main problems of power loss after switching loss, accounting for about 20-30% of the total loss.

[0086] Compared with the conventional discrete solution of 500KHz, the rectifier 10 provided in the embodiment of the present disclosure will be beneficial to the high power and high frequency buck rectifier module in the data center application with the load current>20A and the switching frequency>1-2MHz. The higher the current, the larger the parasitic Vsub=I*Rsub, which will make it easier to automatically turn on the LS transistor and bring about a smaller Qrr during the dead time, and finally obtain a higher efficiency (~90% at 2MHz).

[0087] Figure 3A FIG. 1 is a top view of a rectifier according to some embodiments of the present disclosure. FIG. 3B to FIG. 3E A cross-sectional view of a rectifier according to some embodiments of the present disclosure is shown. In more detail, Figure 3B is along Figure 3A A cross-sectional view of line BB, Figure 3C is along Figure 3A A cross-sectional view of line CC, Figure 3D is along Figure 3A A cross-sectional view of line DD, Figure 3E is along Figure 3A It should be noted that for the sake of simplicity, FIG. 3B to FIG. 3E Some of the elements depicted in the cross-sectional views are not shown in Figure 3A is shown in a top view. FIG. 3A to FIG. 3E It can be shown as Figures 1 to 2B The exemplary semiconductor structure of the rectifier 10 described in the drawings is similar to that of the rectifier 10, so some components are labeled the same and the relevant details will not be repeated.

[0088] Shown is a substrate 100. In some embodiments, the substrate 100 can be used to provide mechanical and / or structural support for features or structures that may be components or portions of an integrated circuit (eg, rectifier 10) that may be formed on or over the substrate 100.

[0089] The substrate 100 may include a first region 100A and a second region 100B. In some embodiments, the first region 100A of the substrate 100 may refer to a region in which a high-side (HS) transistor Q1 is formed, and the second region 100B of the substrate 100 may refer to a region in which a low-side (LS) transistor Q2 is formed. In more detail, Figure 3B The cross-sectional view illustrates a cross-sectional view of the LS transistor Q2, FIG. 3C to FIG. 3E The cross-sectional view illustrates a cross-sectional view of the HS transistor Q1.

[0090] Generally, the substrate 100 may include a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulator layer below a thin semiconductor layer, which is an active layer of the SOI substrate. The semiconductor of the active layer and the bulk semiconductor generally include a crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, a silicon-germanium alloy, a compound semiconductor (e.g., GaAs, AlAs, InAs, GaN, AlN, and the like), or an alloy thereof (e.g., Ga x Al 1-x As、Ga x Al 1-x N、In x Ga 1-x As and the like), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, and the like) or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or mixed orientation substrates. In some other embodiments, substrate 100 may include sapphire (e.g., crystalline Al2O3), such as large particles or a single crystal layer of sapphire or a coating of sapphire. As another example, substrate 100 may be a sapphire substrate, such as a transparent sapphire substrate comprising α-Al2O3 (as an example). Other elemental semiconductors like germanium may also be used for substrate 100.

[0091] In some embodiments, the substrate 100 may be a p-type substrate. For example, the substrate 100 may be doped with a p-type dopant. Examples of the p-type dopant may be B, Al, Ga, In, or the like.

[0092] The isolation structure 105 is disposed in the substrate 100. The isolation structure 105 may be referred to as a shallow trench isolation (STI) structure. In some embodiments, the isolation structure 105 is made of silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicon glass (FSG), or other low-K dielectric materials. In some embodiments, the isolation structure 105 may have a multi-layer structure, for example, a thermal oxide liner layer with silicon nitride on top of the liner.

[0093] like Figure 3A As shown in the top view of FIG. 1 , one isolation structure 105 is in the substrate 100 and surrounds the first region 100A of the substrate 100, thereby electrically isolating the electrical components formed above the first region 100A of the substrate 100 from other components outside the first region 100A of the substrate 100. Similarly, another isolation structure 105 is in the substrate 100 and surrounds the second region 100B of the substrate 100, thereby electrically isolating the electrical components formed above the second region 100B of the substrate 100 from other components outside the second region 100B of the substrate 100. In some embodiments, each of the isolation structures 105 may include a rectangular ring-shaped top profile.

[0094] refer to Figure 3A and Figure 3B . The second region 100B of the substrate 100 may include a drift region 202, a drift region 204, and a body region 206 between the drift region 202 and the drift region 204. In some embodiments, the drift regions 202 and 204 may be doped with n-type dopants and may also be referred to as n-type drift regions 202 and 204. On the other hand, the body region 206 may be doped with p-type dopants and may also be referred to as p-type body region 206. Examples of p-type dopants may be B, Al, Ga, In, or the like. Examples of n-type dopants may be P, As, Sb, or the like. In some embodiments, the p-type body region 206 may include a higher dopant concentration than the p-type substrate 100.

[0095] Source regions 252 and 254 are disposed in the body region 206. In some embodiments, the source regions 252 and 254 may be heavily doped n-type regions, and may also be referred to as heavily doped n-type (N+) regions 252 and 254. Drain regions 262 and 264 are disposed in the drift regions 202 and 204, respectively. In some embodiments, the drain regions 262 and 264 may be heavily doped n-type regions, and may also be referred to as heavily doped n-type (N+) regions 262 and 264. A pick-up region 270 is disposed in the body region 206 and laterally between the source regions 252 and 254. In some embodiments, the pick-up region 270 may be in contact with the source regions 252 and 254. In some embodiments, the pick-up region 270 may be heavily doped p-type regions, and may also be referred to as heavily doped p-type (P+) regions 270.

[0096] In some embodiments, source regions 252 / 254 and drain regions 262 / 264 may include a higher dopant concentration (eg, n-type dopant concentration) than drift regions 202 and 204 . On the other hand, pickup region 270 may include a higher dopant concentration (eg, p-type dopant concentration) than body region 206 .

[0097] The gate structures 210A and 210B are disposed over the second region 100B of the substrate 100. In more detail, the gate structure 210A may cover a portion of the drift region 202 and the body region 206. On the other hand, the gate structure 210B may cover a portion of the drift region 204 and the body region 206. Each of the gate structures 210A and 210B may include a first gate dielectric 212, a second gate dielectric 214, and a gate electrode 216 over the first gate dielectric 212 and the second gate dielectric 214.

[0098] In some embodiments, the first gate dielectric 212 and the second gate dielectric 214 may include silicon oxide, silicon nitride, a high-k dielectric material, multiple layers thereof, or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, and / or combinations thereof.

[0099] In some embodiments, the gate electrode 216 may include a conductive material such as doped polysilicon. In other embodiments, the gate electrode 216 may include a metal-containing material such as aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof.

[0100] Gate spacers 222 and 224 are disposed on opposite sidewalls of gate structure 210A. Gate spacers 226 and 228 are disposed on opposite sidewalls of gate structure 210B. In some embodiments, gate spacers 222, 224, 226, and 228 may include silicon nitride-based materials such as SiN, SiON, SiCON, or SiCN, and combinations thereof, or any other suitable insulating material.

[0101] Regarding the gate structure 210A, the first gate dielectric 212 is in lateral contact with the second gate dielectric 214, wherein the gate electrode 216 is in contact with both top surfaces of the first gate dielectric 212 and the second gate dielectric 214. In some embodiments, the first gate dielectric 212 is thicker than the second gate dielectric 214 along a vertical direction (e.g., the Z direction). That is, the top surface of the first gate dielectric 212 is higher than the top surface of the second gate dielectric 214. In some embodiments, the bottom surface of the first gate dielectric 212 can be substantially flush with the bottom surface of the second gate dielectric 214. In some embodiments, the thickness of the first gate dielectric 212 is about 1000 Å. to about On the other hand, the thickness of the second gate dielectric 214 is about to about within the range.

[0102] To obtain a lower threshold voltage (V T ) (e.g., 0.7-0.8V), the second gate dielectric 214 is increased from about to about The original thickness is reduced to to about For lower V T Because the drain voltage remains constant (e.g., 12V in some embodiments), the gate edge will induce a high electric field, resulting in impact ionization and degradation, so a dual gate oxide structure is provided. For example, a thinner second gate dielectric 214 is provided for lower Vt devices, and a thicker first gate dielectric 212 is provided to reduce edge impact ionization.

[0103] In some embodiments, the first gate dielectric 212 and the second gate dielectric 214 each have an asymmetric sidewall profile. For example, the first gate dielectric 212 has a substantially vertical sidewall in contact with the gate spacer 222, and has an inclined sidewall in contact with the second gate dielectric 214. Similarly, the second gate dielectric 212 has a substantially vertical sidewall in contact with the gate spacer 224, and has an inclined sidewall in contact with the first gate dielectric 212. That is, the first gate dielectric 212 and the second gate dielectric 214 may form an inclined interface. In some embodiments, because the first gate dielectric 212 is thicker than the second gate dielectric 214, the inclined sidewall of the first gate dielectric 212 may contact the gate electrode 216. The inclined sidewall of the first gate dielectric 212 may be beneficial to relieve the gate electric field crowding at the top corner of the first gate dielectric 212, thereby possibly turning on the regional channel early. In some embodiments, an angle between the sloped sidewall of the first gate dielectric 212 and the top surface of the substrate 100 (or the top surface of the drift region 202 ) is in a range from about 30 degrees to about 60 degrees.

[0104] The drain region 262 is laterally separated from the gate spacer 222 by a non-zero distance. For example, the drain region 262 is laterally separated from the gate spacer 222 by a portion of the drift region 202. On the other hand, one side of the source region 252 can be vertically aligned with the outer sidewall of the gate spacer 224. That is, the source region 252 is closer to the gate structure 210A than the drain region 262.

[0105] The bottom surface of the first gate dielectric 212 has a lateral length E1. In some embodiments, the length E1 is in a range of about 0.10 μm to about 0.12 μm. The lateral length E2 between the first gate dielectric 212 and the drain region 262 is referred to as the "drift region length". In some embodiments, the lateral length E2 is in a range of about 0.3 μm to about 0.6 μm. The second gate dielectric 214 may cover the body region 206 with a lateral length L1. In some embodiments, the lateral length L1 is in a range of about 0.1 μm to about 0.2 μm. The second gate dielectric 214 may also cover the drift region 202 with a lateral length L2. In some embodiments, the lateral length L2 is in a range of about 0.15 μm to about 0.25 μm. In some embodiments, the lateral length E1 depends on the voltage drops at opposite sides of the first gate dielectric 212. The drain voltage drop at one side of the first gate dielectric 212 near the drain region 262 may be 5V, and the drain voltage drop at the other side of the first gate dielectric 212 near the source region 252 may be 3V. The lateral length E1 is selected to provide good reliability of the first gate dielectric 212.

[0106] Regarding the gate structure 210B, Figure 3BIn the embodiment, the gate structure 210B may include a gate structure 210B having a gate area of ​​210 Figure 3B The center line of the gate structure 210B may be symmetrical to the gate structure 210A. In some embodiments, the gate structure 210B may include a symmetrical profile to the gate structure 210A with respect to the pickup region 270. Therefore, for the sake of brevity, some structural details of the gate structure 210B may not be repeated.

[0107] The drain region 264 is laterally separated from the gate spacer 226 by a non-zero distance. For example, the drain region 264 is laterally separated from the gate spacer 226 by a portion of the drift region 204. On the other hand, one side of the source region 254 can be vertically aligned with the outer sidewall of the gate spacer 228. That is, the source region 254 is closer to the gate structure 210B than the drain region 264.

[0108] The protection layers 232 and 234 are disposed above the substrate 100. The protection layer 232 may extend from the top surface of the gate structure 210A, through the outer sidewalls of the gate spacer 222, to the top surface of the drift region 202. In some embodiments, the protection layer 232 may terminate before reaching the drain region 262. In other embodiments, the protection layer 232 may cover a portion of the drain region 262. Similarly, the protection layer 234 may extend from the top surface of the gate structure 210B, through the outer sidewalls of the gate spacer 226, to the top surface of the drift region 204. In some embodiments, the protection layer 234 may terminate before reaching the drain region 264. In other embodiments, the protection layer 234 may cover a portion of the drain region 264. In some embodiments, the protection layers 232 and 234 may be made of a dielectric material such as silicon oxide, silicon nitride, or the like. In some embodiments where the protection layers 232 and 234 are made of oxide, the protection layers 232 and 234 may also be referred to as resistive protective oxide (RPO).

[0109] The silicide layer 240 is disposed over the top surfaces of the gate structures 210A and 210B, the top surfaces of the source regions 252 and 254, the top surfaces of the drain regions 262 and 264, and the top surface of the pickup region 270. In some embodiments, the silicide layer 240 may also extend to the top surfaces of the drift regions 202 and 204. The silicide layer 240 may include a metal silicide. Examples of metal silicides include tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, platinum silicide, erbium silicide, or a combination thereof. In some embodiments, the silicide layer 240 may be omitted.

[0110] An interlayer dielectric (ILD) layer 120 is disposed over the substrate 100 and covers the gate structures 210A and 210B, the source regions 252 and 254, the drain regions 262 and 264, and the pickup region 270. In some embodiments, the ILD layer 120 may include silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), phospho-silicate glass (PSG), boro-phospho-silicate glass, low-k dielectric materials, and / or other suitable dielectric materials. Examples of low-k dielectric materials include, but are not limited to, fluoro-silicate glass (FSG), carbon-doped silicon oxide, amorphous fluorinated carbon, poly-p-xylene, bis-benzocyclobutene (BCB), or polyimide.

[0111] Contact sockets 281, 282, 283, 284, 285, 286, 287 are disposed in the ILD layer 120. In some embodiments, the contact sockets 281, 282, 283, 284, 285, 286, 287 are made of a conductive material such as a metal. In some embodiments, the conductive material may include W, Ru, Co, Cu, Ti, TiN, Ta, TaN, Mo, Ni, or the like.

[0112] The contact socket 281 is vertically located above the gate structure 210A and is electrically connected to the gate structure 210A via the silicide layer 240. The contact socket 281 may be referred to as a gate contact socket. In some embodiments, the contact socket 281 is laterally arranged along a first direction (eg, X direction). Figure 3B In the cross-sectional view of FIG. 2 , two contact sockets 281 are arranged along the first direction and vertically located above the gate structure 210A. In some embodiments, the number of contact sockets 281 is not limited thereto, and thus more or fewer contact sockets 281 may be used. In some embodiments where the silicide layer 240 is omitted, the contact sockets 281 may contact the top surface of the gate structure 210A.

[0113] The contact socket 282 is vertically located above the gate structure 210B and is electrically connected to the gate structure 210B via the silicide layer 240. The contact socket 282 may be referred to as a gate contact socket. In some embodiments, the contact socket 282 is laterally arranged along a first direction (eg, an X direction). Figure 3B In the cross-sectional view of FIG. 2 , two contact sockets 282 are arranged along the first direction and vertically located above the gate structure 210B. In some embodiments, the number of contact sockets 282 is not limited thereto, and thus more or fewer contact sockets 282 may be used. In some embodiments where the silicide layer 240 is omitted, the contact sockets 282 may contact the top surface of the gate structure 210B.

[0114] The contact socket 283 is vertically located above the source region 252 and is electrically connected to the source region 252 via the silicide layer 240. The contact socket 283 may be referred to as a source contact socket. In some embodiments, the contact socket 283 is laterally arranged along the second direction (eg, the Y direction). Figure 3A In the top view of FIG. 2 , five contact sockets 283 are arranged along the second direction and vertically located above the source region 252. In some embodiments, the number of contact sockets 283 is not limited thereto, and thus more or fewer contact sockets 283 may be used. In some embodiments where the silicide layer 240 is omitted, the contact sockets 283 may contact the top surface of the source region 252.

[0115] The contact socket 284 is vertically located above the source region 254 and is electrically connected to the source region 254 via the silicide layer 240. The contact socket 284 may be referred to as a source contact socket. In some embodiments, the contact socket 284 is laterally arranged along the second direction (eg, the Y direction). Figure 3A In the top view of FIG. 2 , five contact sockets 284 are arranged along the second direction and vertically located above the source region 254. In some embodiments, the number of contact sockets 284 is not limited thereto, and thus more or fewer contact sockets 284 may be used. In some embodiments where the silicide layer 240 is omitted, the contact sockets 284 may contact the top surface of the source region 254.

[0116] The contact socket 285 is vertically located above the drain region 262 and is electrically connected to the drain region 262 via the silicide layer 240. The contact socket 285 may be referred to as a drain contact socket. In some embodiments, the contact socket 285 is laterally arranged along the second direction (eg, the Y direction). Figure 3A In the top view of FIG. 2 , five contact sockets 285 are arranged along the second direction and vertically located above the drain region 262. In some embodiments, the number of contact sockets 285 is not limited thereto, and thus more or fewer contact sockets 285 may be used. In some embodiments where the silicide layer 240 is omitted, the contact sockets 285 may contact the top surface of the drain region 262.

[0117] The contact socket 286 is vertically located above the drain region 264 and is electrically connected to the drain region 264 via the silicide layer 240. The contact socket 286 may be referred to as a drain contact socket. In some embodiments, the contact socket 286 is laterally arranged along the second direction (eg, the Y direction). Figure 3A In the top view of FIG. 2 , five contact sockets 286 are arranged along the second direction and vertically located above the drain region 264. In some embodiments, the number of contact sockets 286 is not limited thereto, and thus more or fewer contact sockets 286 may be used. In some embodiments where the silicide layer 240 is omitted, the contact sockets 286 may contact the top surface of the drain region 264.

[0118] The contact socket 287 is vertically located above the pickup region 270 and is electrically connected to the pickup region 270 via the silicide layer 240. The contact socket 287 may be referred to as a pickup contact socket. In some embodiments, the contact socket 287 is laterally arranged along the second direction (eg, the Y direction). Figure 3A In the top view of FIG. 2 , five contact sockets 287 are arranged along the second direction and vertically located above the pickup region 270. In some embodiments, the number of contact sockets 287 is not limited thereto, and thus more or fewer contact sockets 287 may be used. In some embodiments where the silicide layer 240 is omitted, the contact sockets 287 may contact the top surface of the pickup region 270.

[0119] In some embodiments, the number of contact sockets 281 may be the same as the number of contact sockets 282. On the other hand, the number of contact sockets 283, the number of contact sockets 284, the number of contact sockets 285, the number of contact sockets 286, and the number of contact sockets 287 may be the same. In some embodiments, the number of contact sockets 281 and the number of contact sockets 282 may be smaller than the number of contact sockets 283, the number of contact sockets 284, the number of contact sockets 285, the number of contact sockets 286, and the number of contact sockets 287.

[0120] Metal wirings 292 and 294 are disposed above the ILD layer 120. In some embodiments, the metal wiring 292 contacts the top surfaces of the contact sockets 281, 282, 283, 284, and 287. That is, the metal wiring 292 is electrically connected to the gate structures 210A, 210B, the source regions 252, 254, and the pickup region 270. Therefore, the gate structures 210A, 210B, the source regions 252, 254, and the pickup region 270 are electrically connected to each other. On the other hand, the metal wiring 294 contacts the top surfaces of the contact sockets 285 and 286. That is, the metal wiring 294 is electrically connected to the drain regions 262 and 264. Therefore, the drain regions 262 and 264 are electrically connected to each other. In some embodiments, the metal wirings 292 and 294 are separated from each other. In some embodiments, the metal wirings 292 and 294 are made of a conductive material such as a metal. In some embodiments, the conductive material may include W, Ru, Co, Cu, Ti, TiN, Ta, TaN, Mo, Ni, or the like.

[0121] like Figure 3A and Figure 3BAs shown in , the gate structure 210A, the source region 252, the drain region 262, the pick-up region 270, and the underlying drift region 202 and the body region 206 can be used together as a first transistor (e.g., a field effect transistor). Similarly, the gate structure 210B, the source region 254, the drain region 264, the pick-up region 270, and the underlying drift region 204 and the body region 206 can be used together as a second transistor (e.g., a field effect transistor). The gate structure 210A of the first transistor and the gate structure 210B of the second transistor are electrically connected to each other (e.g., via metal wiring 292), the source region 252 of the first transistor and the source region 254 of the second transistor are electrically connected to each other (e.g., via metal wiring 292), and the drain region 262 of the first transistor and the drain region 264 of the second transistor are electrically connected to each other (e.g., via metal wiring 294). In addition, the first transistor and the second transistor may include substantially the same configuration. The first transistor and the second transistor can operate simultaneously. Therefore, the first transistor and the second transistor can be equivalently used as Figures 1 to 2B LS transistor Q2 is shown in FIG.

[0122] In other words, the LS transistor Q2 formed on the second region 100B of the substrate 100 can be regarded as having gate structures 210A and 210B, source regions 252 and 254, drain regions 262 and 264, and a pickup region 270. Figure 1 , Figure 3A ,and Figure 3B , gate structures 210A and 210B can be used as gate G2 of LS transistor Q2, source regions 252 and 254 can be used as source S2 of LS transistor Q2, drain regions 262 and 264 can be used as drain D2 of LS transistor Q2, and pick-up region 270 (and / or body region 206) can be used as body B2 of LS transistor Q2.

[0123] However, in some other embodiments, one of the first and second transistors may be omitted. In some embodiments where the second transistor is omitted, the first transistor may be used alone, such as Figures 1 to 2B Similarly, if the first transistor is omitted, the second transistor can be used alone as shown in FIG. Figures 1 to 2B LS transistor Q2 is shown in FIG.

[0124] refer to Figure 3A , Figure 3C , Figure 3D and Figure 3E. The first region 100A of the substrate 100 may include a drift region 302, a drift region 304, and a body region 306 between the drift regions 302 and 304. In some embodiments, the drift regions 302 and 304 may be doped with an n-type dopant, and may also be referred to as n-type drift regions 302 and 304. On the other hand, the body region 306 may be doped with a p-type dopant, and may also be referred to as a p-type body region 306. Examples of p-type dopants may be B, Al, Ga, In, or the like. Examples of n-type dopants may be P, As, Sb, or the like. In some embodiments, the p-type body region 306 may include a higher dopant concentration than the p-type substrate 100.

[0125] The source region 352 is disposed in the body region 306 (see Figure 3C and Figure 3E In some embodiments, the source region 352 may be a heavily doped n-type region, and may also be referred to as a heavily doped n-type (N+) region 352. The drain regions 362 and 364 are disposed in the drift regions 302 and 304, respectively. In some embodiments, the drain regions 362 and 364 may be heavily doped n-type regions, and may also be referred to as heavily doped n-type (N+) regions 362, 364.

[0126] The pickup area 370 is disposed in the main body area 306 (see Figure 3D and Figure 3E In some embodiments, the pickup region 370 may be a heavily doped p-type region, and may also be referred to as a heavily doped p-type (P+) region 370 .

[0127] like Figure 3E As shown in the cross-sectional view of , the source region 352 may include several portions 352A, 352B, and 352C, and the pickup region 370 may include several portions 370A and 370B. In some embodiments, the portions 352A, 352B, and 352C of the source region 352 and the portions 370A and 370B of the pickup region 370 are alternately arranged along the second direction (e.g., the Y direction). In other words, the source region 352 and the pickup region 370 are arranged along the second direction (e.g., the Y direction). However, Figure 3A and Figure 3B The source regions 252, 254 and the pickup region 270 are alternately arranged along a first direction (eg, X direction).

[0128] The gate structures 310A and 310B are disposed over the first region 100A of the substrate 100. In more detail, the gate structure 310A may cover a portion of the drift region 302 and the body region 306. On the other hand, the gate structure 310B may cover a portion of the drift region 304 and the body region 306. Each of the gate structures 310A and 310B may include a first gate dielectric 312, a second gate dielectric 314, and a gate electrode 316 over the first gate dielectric 312 and the second gate dielectric 314. Gate spacers 322 and 324 are disposed on opposite sidewalls of the gate structure 310A. Gate spacers 326 and 328 are disposed on opposite sidewalls of the gate structure 310B.

[0129] In some embodiments, the materials of the first gate dielectric 312, the second gate dielectric 314, and the gate electrode 316 may be the same or similar to the first gate dielectric 212, the second gate dielectric 214, and the gate electrode 216 described above, so for the sake of brevity, the relevant details will not be repeated. In some embodiments, the materials of the gate spacers 322, 324, 326, and 328 may be the same or similar to the gate spacers 222, 224, 226, and 228 described above, so for the sake of brevity, the relevant details will not be repeated.

[0130] Regarding the gate structure 310A, the first gate dielectric 312 is in lateral contact with the second gate dielectric 314, wherein the gate electrode 316 is in contact with both top surfaces of the first gate dielectric 312 and the second gate dielectric 314. In some embodiments, the first gate dielectric 312 is thicker than the second gate dielectric 314 along the vertical direction. That is, the top surface of the first gate dielectric 312 is higher than the top surface of the second gate dielectric 314. In some embodiments, the bottom surface of the first gate dielectric 312 can be substantially flush with the bottom surface of the second gate dielectric 314. In some embodiments, the thickness of the first gate dielectric 312 is about 1000 Å. to about On the other hand, the thickness of the second gate dielectric 314 is about to about within the range.

[0131] In some embodiments, the first gate dielectric 312 and the second gate dielectric 314 each have an asymmetric sidewall profile. For example, the first gate dielectric 312 has a substantially vertical sidewall in contact with the gate spacer 322, and has an inclined sidewall in contact with the second gate dielectric 314. Similarly, the second gate dielectric 312 has a substantially vertical sidewall in contact with the gate spacer 324, and has an inclined sidewall in contact with the first gate dielectric 312. That is, the first gate dielectric 312 and the second gate dielectric 312 may form an inclined interface. In some embodiments, because the first gate dielectric 312 is thicker than the second gate dielectric 312, the inclined sidewall of the first gate dielectric 312 may contact the gate electrode 316. The inclined sidewall of the first gate dielectric 312 may be beneficial to alleviate the gate electric field crowding at the top corner of the first gate dielectric 312, which may cause the regional channel to turn on early. In some embodiments, an angle between the sloped sidewall of the first gate dielectric 312 and the top surface of the substrate 100 (or the top surface of the drift region 302 ) is in a range from about 30 degrees to about 60 degrees.

[0132] The drain region 362 is laterally separated from the gate spacer 322 by a non-zero distance. For example, the drain region 362 is laterally separated from the gate spacer 322 by a portion of the drift region 302. On the other hand, one side of the source region 352 can be vertically aligned with the outer sidewall of the gate spacer 324. That is, the source region 352 is closer to the gate structure 310A than the drain region 362.

[0133] Regarding the gate structure 310B, Figure 3C and Figure 3D In the embodiment, the gate structure 310B may include a gate structure 310B having a gate area of ​​?? Figure 3C and Figure 3D The center line of the gate structure 310A is symmetrical to the gate structure 310A. In some embodiments, the gate structure 310B may include a source region 352 (see Figure 3C ) or relative to the pickup area 370 (see Figure 3D ) and the gate structure 310A. Therefore, for the sake of brevity, some structural details of the gate structure 310B may not be repeated.

[0134] The drain region 364 is laterally separated from the gate spacer 326 by a non-zero distance. For example, the drain region 364 is laterally separated from the gate spacer 326 by a portion of the drift region 304. On the other hand, the other side of the source region 352 can be vertically aligned with the outer sidewall of the gate spacer 328. That is, the source region 352 is closer to the gate structure 310B than the drain region 264.

[0135] like Figure 3B , Figure 3C ,and Figure 3DAs shown in FIG. 1 , the distance between gate structures 210A and 210B is greater than the distance between gate structures 310A and 310B. This is because there are source regions 252, 254 and pickup region 270 between gate structures 210A and 210B, while there is only source region 352 between gate structures 310A and 310B (see FIG. 1 ). Figure 3C ) or pick-up area 370 (see Figure 3D ). Similarly, the distance between the gate spacers 224 and 228 is greater than the distance between the gate spacers 324 and 328. As a result, the area of ​​the second region 100B of the substrate 100 may be greater than the area of ​​the first region 100A of the substrate 100. In some embodiments, the area of ​​the second region 100B of the substrate 100 may be 2 to 3 times greater than the area of ​​the first region 100A of the substrate 100. In some embodiments, the distance between the pickup region 270 and the gate structure 210A (or 210B) is greater than the distance between the pickup region 370 and the gate structure 310A (or 310B).

[0136] The protection layers 332 and 334 are disposed above the substrate 100. The protection layer 332 may extend from the top surface of the gate structure 310A, through the outer sidewalls of the gate spacer 322, to the top surface of the drift region 302. In some embodiments, the protection layer 332 may terminate before reaching the drain region 362. In other embodiments, the protection layer 332 may cover a portion of the drain region 362. Similarly, the protection layer 334 may extend from the top surface of the gate structure 310B, through the outer sidewalls of the gate spacer 326, to the top surface of the drift region 304. In some embodiments, the protection layer 334 may terminate before reaching the drain region 364. In other embodiments, the protection layer 334 may cover a portion of the drain region 364.

[0137] The silicide layer 340 is disposed over the top surfaces of the gate structures 310A and 310B, the top surface of the source region 352, the top surfaces of the drain regions 362 and 364, and the top surface of the pickup region 370. In some embodiments, the silicide layer 340 may also extend to the top surfaces of the drift regions 302 and 304. The silicide layer 340 may include a metal silicide. Examples of metal silicides include tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, platinum silicide, erbium silicide, or a combination thereof. In some embodiments, the silicide layer 340 may be omitted.

[0138] An interlayer dielectric (ILD) layer 120 is disposed above the substrate 100 and covers the gate structures 310A and 310B, the source region 352 , the drain regions 362 and 364 , and the pickup region 370 .

[0139] Contact sockets 381, 382, ​​383, 385, 386, 387 are disposed in the ILD layer 120. In some embodiments, the contact sockets 381, 382, ​​383, 385, 386, 387 are made of a conductive material such as a metal. In some embodiments, the conductive material may include W, Ru, Co, Cu, Ti, TiN, Ta, TaN, Mo, Ni, or the like.

[0140] The contact socket 381 is vertically located above the gate structure 310A and is electrically connected to the gate structure 310A via the silicide layer 340. The contact socket 381 may be referred to as a gate contact socket. In some embodiments, the contact socket 381 is laterally arranged along a first direction (eg, an X direction). Figure 3C In the cross-sectional view of FIG. 3 , two contact sockets 381 are arranged along the first direction and vertically located above the gate structure 310A. In some embodiments, the number of contact sockets 381 is not limited thereto, and thus more or fewer contact sockets 381 may be used. In some embodiments where the silicide layer 340 is omitted, the contact sockets 381 may contact the top surface of the gate structure 310A.

[0141] The contact socket 382 is vertically located above the gate structure 310B and is electrically connected to the gate structure 310B via the silicide layer 340. The contact socket 382 may be referred to as a gate contact socket. In some embodiments, the contact socket 382 is laterally arranged along a first direction (eg, an X direction). Figure 3C In the cross-sectional view of FIG. 3 , two contact sockets 382 are arranged along the first direction and vertically located above the gate structure 310B. In some embodiments, the number of contact sockets 382 is not limited thereto, and thus more or fewer contact sockets 382 may be used. In some embodiments where the silicide layer 340 is omitted, the contact sockets 382 may contact the top surface of the gate structure 310B.

[0142] The contact socket 383 is vertically located above the source region 352 and is electrically connected to the source region 352 via the silicide layer 340. The contact socket 383 may be referred to as a source contact socket. In some embodiments, the contact socket 383 is laterally arranged along the second direction (eg, the Y direction). Figure 3A In the top view of FIG. 3 , three contact sockets 383 are arranged along the second direction and vertically located above the source region 352. In some embodiments, the number of contact sockets 383 is not limited thereto, so more or less contact sockets 383 may be used. In some embodiments where the silicide layer 340 is omitted, the contact sockets 383 may contact the top surface of the source region 352.

[0143] The contact socket 385 is vertically located above the drain region 362 and is electrically connected to the drain region 362 via the silicide layer 340. The contact socket 385 may be referred to as a drain contact socket. In some embodiments, the contact socket 385 is laterally arranged along the second direction (eg, the Y direction). Figure 3A In the top view of FIG. 3 , five contact sockets 385 are arranged along the second direction and vertically located above the drain region 362. In some embodiments, the number of contact sockets 385 is not limited thereto, so more or less contact sockets 385 may be used. In some embodiments where the silicide layer 340 is omitted, the contact sockets 385 may contact the top surface of the drain region 362.

[0144] The contact socket 386 is vertically located above the drain region 364 and is electrically connected to the drain region 364 via the silicide layer 340. The contact socket 386 may be referred to as a drain contact socket. In some embodiments, the contact socket 386 is laterally arranged along the second direction (eg, the Y direction). Figure 3A In the top view of FIG. 3 , five contact sockets 386 are arranged along the second direction and vertically located above the drain region 364. In some embodiments, the number of contact sockets 386 is not limited thereto, and thus more or fewer contact sockets 386 may be used. In some embodiments where the silicide layer 340 is omitted, the contact sockets 386 may contact the top surface of the drain region 364.

[0145] The contact socket 387 is vertically located above the pickup region 270 and is electrically connected to the pickup region 370 via the silicide layer 340 (see FIG. Figure 3E ). The contact socket 387 may be referred to as a pickup contact socket. In some embodiments, the contact socket 387 is laterally arranged along the second direction (eg, the Y direction). Figure 3A In the top view of FIG. 3 , two contact sockets 387 are arranged along the second direction and vertically located above the pickup region 370. In some embodiments, the number of contact sockets 387 is not limited thereto, so more or fewer contact sockets 387 may be used. In some embodiments where the silicide layer 340 is omitted, the contact sockets 387 may contact the top surface of the pickup region 370. Figure 3A and Figure 3E In the embodiment, the contact sockets 383 and the contact sockets 387 are alternately arranged along the second direction (eg, the Y direction).

[0146] In some embodiments, the number of contact sockets 381 may be the same as the number of contact sockets 382. On the other hand, the number of contact sockets 385 may be the same as the number of contact sockets 386. In some embodiments, the number of contact sockets 381 and the number of contact sockets 382 may be smaller than the number of contact sockets 385 and the number of contact sockets 386. In some embodiments, the number of contact sockets 383 may be smaller than the number of contact sockets 385 and the number of contact sockets 386. In some embodiments, the number of contact sockets 387 may be smaller than the number of contact sockets 383.

[0147] Metal wirings 392, 393, and 394 are disposed above the ILD layer 120. In some embodiments, the metal wiring 392 contacts the top surfaces of the contact sockets 381 and 382. That is, the metal wiring 392 is electrically connected to the gate structures 310A and 310B. Therefore, the gate structures 310A and 310B are electrically connected to each other. The metal wiring 393 contacts the top surfaces of the contact sockets 383 and 387. That is, the metal wiring 393 is electrically connected to the source region 352 and the pickup region 370. Therefore, the source region 352 and the pickup region 370 are electrically connected to each other. On the other hand, the metal wiring 394 contacts the top surfaces of the contact sockets 385 and 386. That is, the metal wiring 394 is electrically connected to the drain regions 362 and 364. Therefore, the drain regions 362 and 364 are electrically connected to each other. In some embodiments, the metal wirings 392, 393, and 394 are separated from each other. In some embodiments, metal wirings 392, 393, and 394 are made of a conductive material such as a metal. In some embodiments, the conductive material may include W, Ru, Co, Cu, Ti, TiN, Ta, TaN, Mo, Ni, or the like.

[0148] like Figure 3A , Figure 3C , Figure 3D ,and Figure 3EAs shown in , the gate structure 310A, the source region 352, the drain region 362, the pick-up region 370, and the underlying drift region 302 and the body region 306 can be collectively used as a third transistor (e.g., a field effect transistor). Similarly, the gate structure 310B, the source region 352, the drain region 362, the pick-up region 370, and the underlying drift region 304 and the body region 306 can be collectively used as a fourth transistor (e.g., a field effect transistor). The gate structure 310A of the third transistor and the gate structure 310B of the fourth transistor are electrically connected to each other (e.g., via metal wiring 392), and the drain region 362 of the third transistor and the drain region 364 of the fourth transistor are electrically connected to each other (e.g., via metal wiring 394). The third transistor and the fourth transistor can share the same source region 352 and the same pick-up region 370. The third transistor and the fourth transistor may include substantially the same configuration. The third transistor and the fourth transistor may operate simultaneously. Therefore, the third transistor and the fourth transistor can be equivalently used as Figures 1 to 2B HS transistor Q1 is shown in FIG.

[0149] In other words, the HS transistor Q1 formed on the first region 100A of the substrate 100 can be considered to have gate structures 310A and 310B, a source region 352, drain regions 362 and 364, and a pickup region 370. Figure 1 , Figure 3A , Figure 3B , Figure 3D ,and Figure 3E , gate structures 310A and 310B can be used as gate G1 of HS transistor Q1, source region 352 can be used as source S1 of HS transistor Q1, drain regions 362 and 364 can be used as drain D1 of HS transistor Q1, and pick-up region 370 (and / or body region 306) can be used as body B1 of HS transistor Q1.

[0150] However, in some other embodiments, one of the third and fourth transistors may be omitted. In some embodiments where the fourth transistor is omitted, the third transistor may be used alone as Figures 1 to 2B Similarly, if the third transistor is omitted, the fourth transistor can be used alone as shown in FIG. Figures 1 to 2B HS transistor Q1 is shown in FIG.

[0151] In some embodiments of the present disclosure, during operation of the rectifier 10, the on-time of the LS transistor Q2 may be >80% of the duty cycle. To effectively increase the channel area of ​​the LS transistor Q2, the pickup region 270 is configured to be laterally separated from the gate structures 210A and 210 by the source regions 252 and 254, respectively. In addition, by shorting the gate / body / source of the LS transistor Q2 together, the W / L will increase by 10-20%, which means that we will maintain the Cg or Qg of the LS transistor Q2 and reduce the Rsp.

[0152] Figure 4 The figure shows a top view of a rectifier according to some embodiments of the present disclosure. Metal wiring 394 is electrically connected to supply voltage terminal Vin. That is, supply voltage terminal Vin is electrically connected to drain regions 362 and 364. In other words, supply voltage terminal Vin is electrically connected to drain D1 of HS transistor Q1 (see Figure 1 ).

[0153] Metal wiring 392 is electrically connected to driver 50. That is, driver 50 is electrically connected to gate structures 310A and 310B. In other words, driver 50 is electrically connected to the gate of HS transistor Q1.

[0154] Metal wiring 393 and metal wiring 294 are electrically connected to each other. That is, source region 352 and pickup region 370 are electrically connected to drain regions 262 and 264. In other words, source S1 and body B1 of HS transistor Q1 are electrically connected to drain D2 of LS transistor Q2 (see FIG. Figure 1 ).

[0155] In some embodiments, metal wire 393 and metal wire 294 are electrically connected to node SW. Inductor 20 is electrically connected to node SW. That is, inductor 20 is electrically connected to source region 352, pickup region 370, and drain regions 362 and 364. In other words, inductor 20 is electrically connected to source S1 and body B1 of HS transistor Q1 and drain D2 of LS transistor Q2 (see FIG. Figure 1 ).

[0156] The other side of the inductor 20 is electrically connected to the node N1. One side of each of the capacitor 30 and the resistor 40 is electrically connected to the node N1. The other side of each of the capacitor 30 and the resistor 40 is also electrically connected to the metal wiring 292. That is, the capacitor 30 and the resistor 40 are electrically connected to the gate structures 210A, 210B, the source regions 252, 254, and the pickup region 270. In other words, the capacitor 30 and the resistor 40 are electrically connected to the gate G2, the source S2, and the body B2 of the LS transistor Q2.

[0157] FIG. 5A to FIG. 18E is a schematic diagram of a rectifier at different stages of manufacture according to some embodiments of the present disclosure. FIG. 5A to FIG. 18E The views shown in are described with reference to one method, but it should be understood that FIG. 5A to FIG. 18E The structure shown in is not limited to this method, but can be used independently of this method. FIG. 5A to FIG. 18E Although described as a series of actions, it should be understood that these actions are not limiting, because the order of the actions can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some of the actions shown and / or described can be omitted in whole or in part. In some embodiments, FIG. 5A to FIG. 18E Some of the elements described in Figures 1 to 4 Where elements described are similar or identical, such elements are labeled identically and the relevant details will not be repeated for the sake of brevity.

[0158] refer to FIG. 5A to FIG. 5C ,in Figure 5B It is along Figure 5A A cross-sectional view of line BB, Figure 5C It is along Figure 5A A substrate 100 is provided. An isolation structure 105 is formed in the substrate 100. In some embodiments, the isolation structure 105 may be formed by, for example, etching the substrate 100 to form a trench, depositing a dielectric material over the substrate 100 and filling the trench, and then performing a planarization process (e.g., chemical mechanical polishing; CMP) to remove excess dielectric material until the top surface of the substrate 100 is exposed.

[0159] Drift regions 202, 204, 302, and 304 are formed in substrate 100. In more detail, drift regions 302 and 304 are formed in first region 100A of substrate 100, and drift regions 202 and 204 are formed in second region 100B of substrate 100. In some embodiments, drift regions 202, 204, 302, and 304 may be formed by, for example, forming a patterned mask having an opening for exposing substrate 100, performing an ion implantation process on substrate 100 through the opening of the patterned mask, and then removing the patterned mask after performing the ion implantation process. In some embodiments, the ion implantation process may include using an n-type dopant, such as arsenic, phosphorus, or other suitable n-type dopant.

[0160] refer to Fig. 6A and Figure 6B ,in Fig. 6A and Figure 6B Follow Figure 5B and Figure 5C. The gate dielectric layer 311 and the gate dielectric layer 211 are formed over the first area 100A and the second area 100B of the substrate 100, respectively. In some embodiments, the gate dielectric layer 311 and the gate dielectric layer 211 are different parts of a continuous layer, so the gate dielectric layers 211 and 311 may include substantially the same thickness. In some embodiments, the gate dielectric layers 211 and 311 are formed by thermal oxidation, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), epitaxy, or another suitable formation process. In some embodiments, the gate dielectric layers 211 and 311 are formed by dry or wet oxidation at a temperature in the range of about 850° C. to about 950° C.

[0161] A patterned mask MA1 is formed over the substrate 100 and covers the gate dielectric layers 211 and 311. The patterned mask MA1 may include an opening O1 that exposes a portion of the gate dielectric layer 211 and an opening O2 that exposes a portion of the gate dielectric layer 311. In some embodiments, the patterned mask MA1 may include a photoresist and may be patterned using a suitable lithography process.

[0162] refer to Fig. 7A and Figure 7B ,in Fig. 7A and Figure 7B Follow Fig. 6A and Figure 6B . An etching process is performed to remove the exposed portions of the gate dielectric layers 211 and 311, thereby exposing the top surface of the substrate 100. In some embodiments, the etching process may include dry etching, wet etching, or a combination thereof. In some embodiments, the etching process may include an isotropic etching process, such as isotropic wet etching or isotropic dry etching, which will result in the remaining gate dielectric layers 211 and 311 having inclined sidewalls exposed to the openings O1 and O2, respectively.

[0163] refer to Fig. 8A and Figure 8B ,in Fig. 8A and Figure 8B Follow Fig. 7A and Figure 7B. The patterned mask MA1 is removed. The gate dielectric layer 213 and the gate dielectric layer 313 are formed over the exposed surface of the second area 100B and the first area 100A of the substrate 100, respectively. In some embodiments, the gate dielectric layers 213 and 313 are formed by the same deposition process and thus may include substantially the same thickness. In some embodiments, the gate dielectric layers 213 and 313 are formed by thermal oxidation, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), epitaxy, or another suitable formation process.

[0164] In some embodiments where the gate dielectric layers 213 and 313 are formed by thermal oxidation, the gate dielectric layers 213 and 313 may be selectively formed on the exposed surface of the substrate 100, but not formed over the gate dielectric layers 211 and 311. In some embodiments, the gate dielectric layers 213 and 313 are formed by dry or wet oxidation at a temperature in the range of about 750° C. to about 850° C. In some embodiments, the gate dielectric layers 213 and 313 may be deposited at a lower temperature and a shorter deposition duration than the gate dielectric layers 211 and 311, so that the gate dielectric layers 213 and 313 may be thinner than the gate dielectric layers 211 and 311.

[0165] refer to Fig.9A and Fig. 9B ,in Fig.9A and Fig. 9B Follow Fig. 8A and Figure 8B . The gate electrode layer 215 and the gate electrode layer 315 are respectively formed on the substrate 100. In more detail, the gate electrode layer 215 may cover the gate dielectric layers 211 and 213, and the gate electrode layer 315 may cover the gate dielectric layers 311 and 313. In some embodiments, the gate electrode layers 215 and 315 are different parts of a continuous layer. In some embodiments, the gate electrode layers 215 and 315 are formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or another suitable formation process.

[0166] refer to FIG. 10A to FIG. 10C ,in Fig. 10B It is along Fig. 10A A cross-sectional view of line BB, Fig. 10C It is along Fig. 10A. A patterning process is performed on the gate electrode layers 215, 315 and the gate dielectric layers 211, 311, 213, 313 to form gate structures 210A, 210B, 310A, and 310B. In some embodiments, the patterning process can be performed by, for example, forming a patterned mask over the gate electrode layers 215 and 315, and the patterned mask defines the position and shape of the gate structures 210A, 210B, 310A, and 310B. An etching process is performed to remove the useless portions of the gate electrode layers 215, 315 and the gate dielectric layers 211, 311, 213, 313 that are not covered by the patterned mask. The remaining portions of the gate dielectric layer 211, the gate dielectric layer 213, and the gate electrode layer 215 are respectively referred to as the gate dielectric 212, the gate dielectric 214, and the gate electrode 216. The gate dielectric layer 311 , the gate dielectric layer 313 , and the remaining portion of the gate electrode layer 315 are referred to as the gate dielectric 312 , the gate dielectric 314 , and the gate electrode 316 , respectively.

[0167] refer to Fig.11A and Fig. 11B ,in Fig.11A and Fig. 11B Follow Fig. 10B and Fig. 10C A cross-sectional view of FIG. A patterned mask MA2 is formed over the substrate 100. The patterned mask MA2 may include an opening O3 that exposes a portion of the substrate 100 between the gate structures 210A and 210B, and an opening O4 that exposes a portion of the substrate 100 between the gate structures 310A and 310B. An ion implantation process is performed on the substrate 100 through the openings O3 and O4 of the patterned mask MA2, thereby forming body regions 206 and 306 in the second region 100B and the first region 100A of the substrate 100, respectively. In some embodiments, the ion implantation process may include using a p-type dopant, such as boron or BF2, or other suitable p-type dopant. In some embodiments, the patterned mask MA2 may include a photoresist and may be patterned using a suitable lithography process.

[0168] refer to Fig. 12A and Fig. 12B ,in Fig. 12A and Fig. 12B Follow Fig.11A and Fig. 11B. After forming the body regions 206 and 306, the patterned mask MA2 is removed. Gate spacers 222 and 224 are formed on opposite sidewalls of the gate structure 210A. Gate spacers 226 and 228 are formed on opposite sidewalls of the gate structure 210B. Gate spacers 322 and 324 are formed on opposite sidewalls of the gate structure 310A. Gate spacers 326 and 328 are formed on opposite sidewalls of the gate structure 310B. In some embodiments, the gate spacers 222, 224, 226, 228, 322, 324, 326, and 328 may be formed by, for example, depositing a blanket layer of spacers over the substrate 100, performing an anisotropic etching process to remove horizontal portions of the spacer layer, while leaving vertical portions of the spacer layer on the sidewalls of the gate structures 210A, 210B, 310A, and 310B.

[0169] refer to FIG. 13A to FIG. 13C ,in Fig. 13B It is along Fig.13A A cross-sectional view of line BB, Fig. 13C It is along Fig.13A , which is a cross-sectional view of line CC. A patterned mask MA3 is formed over the substrate 100. The patterned mask MA3 may include an opening O5 for exposing a portion of the second area 100B of the substrate 100 and an opening O6 for exposing a portion of the first area 100A of the substrate 100. An ion implantation process is performed on the substrate 100 through the openings O5 and O6 of the patterned mask MA3 to form source regions 252, 254, and 352 and drain regions 262, 264, 362, and 364. In some embodiments, the ion implantation process may include using an n-type dopant, such as arsenic, phosphorus, or other suitable n-type dopant. In some embodiments, the patterned mask MA3 may include a photoresist and may be patterned using a suitable lithography process. It should be noted that for the sake of brevity, the photoresist is not shown in FIG. Fig.13A The patterned mask M3 is shown in the top view of .

[0170] refer to FIG. 14A to FIG. 14E ,in Fig. 14B It is along Fig.14A A cross-sectional view of line BB, Fig. 14C It is along Fig.14A A cross-sectional view of line CC, Fig.14D It is along Fig.14A A cross-sectional view of line DD, Fig.14E It is along Fig.14AEE of the substrate 100. After forming the source regions 252, 254, and 352 and the drain regions 262, 264, 362, and 364, the patterned mask MA3 is removed. A patterned mask MA4 is formed over the substrate 100. The patterned mask MA4 may include an opening O7 that exposes a portion of the second region 100B of the substrate 100, and an opening O8 that exposes a portion of the first region 100A of the substrate 100. In some embodiments, the source regions 252, 254, and 352 and the drain regions 262, 264, 362, and 364 may be covered by the patterned mask MA4. An ion implantation process is performed on the substrate 100 through the openings O7 and O8 of the patterned mask MA4 to form pickup regions 270 and 370. In some embodiments, the ion implantation process may include using a p-type dopant, such as boron or BF2, or other suitable p-type dopant. In some embodiments, the patterned mask MA4 may include a photoresist and may be patterned using a suitable lithography process. Fig.14A The patterned mask M4 is shown in a top view.

[0171] refer to Fig.15A and Fig. 15B ,in Fig.15A and Fig. 15B Follow Fig. 14B and Fig. 14C After forming the pickup regions 270 and 370, the patterned mask MA4 is removed. Protective layers 232 and 234 are formed over the substrate 100. In some embodiments, the protective layers 232 and 234 may be formed by, for example, depositing a dielectric capping layer over the substrate 100 and then performing a lithography process to remove useless portions of the dielectric layer.

[0172] refer to Fig.16A and Fig. 16B ,in Fig.16A and Fig. 16B Follow Fig.15A and Fig. 15B One or more silicide metal deposition processes are performed to form silicide layers 240 and 340 on the upper surfaces of the gate structures 210A, 210B, 310A, and 310B, the source regions 252, 254, and 352, the drain regions 262, 264, 362, and 364, and the pickup regions 270 and 370. In some embodiments, the silicide metal deposition process may be performed by depositing a metal material such as nickel or cobalt, followed by performing a thermal annealing process (e.g., rapid thermal annealing).

[0173] refer to FIG. 17A to FIG. 17E ,in Fig. 17B It is along Fig.17A A cross-sectional view of line BB, Fig. 17CIt is along Fig.17A A cross-sectional view of line CC, Fig.17D It is along Fig.17A A cross-sectional view of line DD, Fig.17E It is along Fig.17A An interlayer dielectric (ILD) layer 120 is formed on the substrate 100. In some embodiments, the ILD layer 120 may be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable formation processes.

[0174] Contact sockets 281, 282, 283, 284, 285, 286, 287 and contact sockets 381, 382, ​​383, 385, 386, 387 are formed in the ILD layer 120. Contact sockets 281, 282, 283, 284, 285, 286, 287, 381, 382, ​​383, 385, 386, and 387 may be formed by selectively etching the ILD layer 120 to form openings (e.g., with a patterned photoresist mask in place), followed by depositing a conductive material within the openings. A planarization process may then be performed to remove excess conductive material outside of the openings. In some embodiments, the planarization process may include a chemical mechanical polishing (CMP) process.

[0175] refer to FIG. 18A to FIG. 18E ,in Fig.18B It is along Fig.18A A cross-sectional view of line BB, Fig.18C It is along Fig.18A A cross-sectional view of line CC, Fig.18D It is along Fig.18A A cross-sectional view of line DD, Fig.18E It is along Fig.18A EE cross-sectional view of the line EE. Metal wiring 292, 294, 392, 393, 394 is formed over the ILD layer 120. In some embodiments, the metal wiring 292, 294, 392, 393, 394 may be formed by, for example, depositing a conductive layer over the ILD layer 120 and then patterning the conductive layer according to a predetermined pattern.

[0176] Return to reference Figure 4After forming metal wirings 292, 294, 392, 393, 394. Driver 50 may be connected to metal wiring 392. Supply voltage terminal Vin may be connected to metal wiring 394. Metal wiring 393 and metal wiring 294 may be connected to each other via, for example, an interconnect structure or wire bonding. Inductor 20 is electrically connected to metal wiring 393 and metal wiring 294. Capacitor 30 and resistor 40 are electrically connected to inductor 20. The other side of each of capacitor 30 and resistor 40 is connected to metal wiring 292. Thus, a rectifier may be formed.

[0177] Fig.19A and Fig.19B A cross-sectional view of a rectifier according to some embodiments of the present disclosure is shown. In some embodiments, Fig.19A and Fig.19B Some of the elements described in Figures 1 to 18E Where elements are similar or identical, those elements are labeled identically and the relevant details will not be repeated for the sake of brevity. Fig.19A and Fig.19B Respectively illustrated and Figure 3B and Figure 3C Same cross-section view. Fig.19A and Fig.19B The structure and Figure 3B and Figure 3C The difference between the structures of FIG. 3 and FIG. 4 is that each of the gate structures 310A and 310B may include a single gate dielectric 312. That is, the gate dielectric 312 is omitted. Figure 3A and Figure 3B 310B. In some embodiments, the gate dielectrics 212 and 214 of the gate structures 210A / 210B may be collectively referred to as the first gate dielectric of the gate structures 210A / 210B, and the gate dielectric 312 of the gate structures 310A / 310B may be referred to as the second gate dielectric of the gate structures 310A / 310B. Fig.19A and Fig.19B In some embodiments, the thickness variation of the first gate dielectric of the gate structure 210A / 210B is greater than the thickness variation of the second gate dielectric of the gate structure 310A / 310B. Fig.19A and Fig.19B The gate dielectric 312 described in the embodiment may be omitted. Figure 6B The opening O2 of the patterned mask MA1 is formed. That is, Figure 6B The patterned mask MA1 may cover Figure 6B The gate dielectric layer 311 is not removed before forming the gate structures 310A and 310B. Figure 6BAny portion of the gate dielectric layer 311. In some embodiments, if the driving voltage of the HS transistor Q1 is high, a single gate dielectric 312 with a greater thickness may be beneficial for reliability.

[0178] Based on the above discussion, it can be seen that the present disclosure provides advantages. However, it should be understood that other embodiments may provide additional advantages, not all advantages must be disclosed herein, and no specific advantages need to be used for all embodiments. The embodiments of the present disclosure provide a rectifier. By short-circuiting the gate / body / source of the low-side transistor of the rectifier together, it is beneficial to reduce power consumption and improve device performance. The gate structure of the low-side transistor is designed to have a dual gate dielectric configuration, which includes a thicker gate dielectric and a thinner gate dielectric. The thicker gate dielectric can be beneficial to device reliability, and the thinner gate dielectric can be beneficial to reduce the threshold voltage. In addition, the pickup region of the low-side transistor is laterally separated from the gate structure of the low-side transistor by the source region of the low-side transistor, which will effectively increase the channel area and will further improve the device performance.

[0179] In some embodiments of the present disclosure, a rectifier includes a substrate, a first transistor, a second transistor, a first gate contact socket, a first source contact socket, a first metal wiring, and an inductor. The first transistor is above the substrate and includes a first gate structure, and a first source region and a first drain region in the substrate and on opposite sides of the first gate structure. The second transistor is above the substrate and includes a second gate structure, and a second source region and a second drain region in the substrate and on opposite sides of the second gate structure. The first gate contact socket is electrically connected to the first gate structure. The first source contact socket is electrically connected to the first source region. The first metal wiring contacts a top surface of the first gate contact socket and a top surface of the first source contact socket. The inductor is electrically connected to the first drain region of the first transistor and the second source region of the second transistor.

[0180] In some embodiments, the first transistor further includes a pick-up region in the substrate, the pick-up region having an opposite conductivity type to the first source region, and the rectifier further includes a pick-up contact socket electrically connected to the pick-up region, wherein the first metal wire also contacts the top surface of the pick-up contact socket.

[0181] In some embodiments, the first transistor further includes a first pickup region, the first pickup region is in the substrate and laterally adjacent to the first source region along a first direction, and the first pickup region and the first source region have opposite conductivity types; the second transistor further includes a second pickup region, the second pickup region is in the substrate and laterally adjacent to the second source region along a second direction perpendicular to the first direction, and the second pickup region and the second source region have opposite conductivity types.

[0182] In some embodiments, a lateral distance between the first pickup region and the first gate structure is greater than a lateral distance between the second pickup region and the second gate structure.

[0183] In some embodiments, the rectifier further includes a second gate contact socket electrically connected to the second gate structure, a second source contact socket electrically connected to the second source region, a second metal wiring in contact with the top surface of the second gate contact socket, and a third metal wiring in contact with the top surface of the second source contact socket, wherein the second metal wiring is laterally separated from the third metal wiring.

[0184] In some embodiments, the first gate structure includes a first gate dielectric, a second gate dielectric adjacent to the first gate dielectric (wherein the first gate dielectric is thicker than the second gate dielectric), and a gate electrode over the first gate dielectric and the second gate dielectric.

[0185] In some embodiments, the first gate dielectric is closer to the first drain region than the second gate dielectric.

[0186] In some embodiments, the first gate dielectric forms a sloped interface with the second gate dielectric.

[0187] In some embodiments of the present disclosure, a rectifier includes a substrate, a high-side transistor, a low-side transistor, and an inductor. The high-side transistor is above the substrate and includes a first gate structure, a first source region and a first drain region in the substrate and on opposite sides of the first gate structure, and a first pickup region in the substrate and laterally adjacent to the first source region along a first direction. The low-side transistor is above the substrate and includes a second gate structure, a second source region and a second drain region in the substrate and on opposite sides of the second gate structure, and a second pickup region in the substrate and laterally adjacent to the second source region along a second direction perpendicular to the first direction. The inductor is electrically connected to the first source region of the high-side transistor and the second drain region of the low-side transistor.

[0188] In some embodiments, the rectifier further includes a first gate contact socket electrically connected to the second gate structure, a first source contact socket electrically connected to the second source region, a first pickup contact socket electrically connected to the second pickup region, and a first metal wiring in contact with a top surface of the first gate contact socket, a top surface of the first source contact socket, and a top surface of the first pickup contact socket.

[0189] In some embodiments, the rectifier further includes first source contact sockets electrically connected to the first source region, and second source contact sockets electrically connected to the second source region, wherein the number of the first source contact sockets is less than the number of the second source contact sockets.

[0190] In some embodiments, the rectifier further comprises first pickup contact sockets electrically connected to the first pickup region, and second pickup contact sockets electrically connected to the second pickup region, wherein the number of the first pickup contact sockets is less than the number of the second pickup contact sockets.

[0191] In some embodiments, the second direction is perpendicular to the length directions of the first and second gate structures.

[0192] In some embodiments, the second gate structure includes a first gate dielectric, a second gate dielectric adjacent to the first gate dielectric (wherein the first gate dielectric and the second gate dielectric form a slanted interface), and a gate electrode over the first gate dielectric and the second gate dielectric.

[0193] In some embodiments, the first gate structure includes a first gate dielectric and the second gate structure includes a second gate dielectric, wherein the second gate dielectric has a greater thickness variation than the first gate dielectric.

[0194] In some embodiments of the present disclosure, a method includes forming a first gate dielectric layer over a substrate; patterning the first gate dielectric layer to expose a portion of the substrate; forming a second gate dielectric layer over the portion of the substrate and in contact with the first gate dielectric layer, wherein the second gate dielectric layer is thinner than the first gate dielectric layer; forming a gate electrode layer over the first gate dielectric layer and the second gate dielectric layer; patterning the gate electrode layer, the first gate dielectric layer, and the second gate dielectric layer to form a first gate structure and a second gate structure, wherein the first gate structure includes a first remaining portion of the gate electrode layer, a first remaining portion of the first gate dielectric layer, and a first remaining portion of the second gate dielectric layer, and the second gate structure includes a second remaining portion of the gate electrode layer and a second portion of the first gate dielectric layer; forming first source and drain regions in the substrate and on opposite sides of the first gate structure; forming second source and drain regions in the substrate and on opposite sides of the second gate structure; and electrically connecting an inductor to the first drain region and the second source region.

[0195] In some embodiments, the method further includes forming a first gate contact socket electrically connected to the first gate structure and a first source contact socket electrically connected to the first source region, and forming a first metal wiring in contact with a top surface of the first gate contact socket and a top surface of the first source contact socket.

[0196] In some embodiments, the method further includes forming a pick-up region in the substrate and laterally adjacent to the first source region, the pick-up region and the first source region having an opposite conductivity type, and forming a pick-up contact socket electrically connected to the pick-up region, wherein the first metal wiring also contacts the top surface of the pick-up contact socket.

[0197] In some embodiments, patterning the first gate dielectric layer to expose a portion of the substrate includes etching the first gate dielectric layer such that the etched first gate dielectric layer has a sloped sidewall.

[0198] In some embodiments, the method further includes forming a first pickup region in the substrate and laterally adjacent to the first source region along the first direction, the first pickup region and the first source region having an opposite conductivity type, and forming a second pickup region in the substrate and laterally adjacent to the second source region along a second direction perpendicular to the first direction, the second pickup region and the second source region having an opposite conductivity type.

[0199] In some embodiments of the present disclosure, a rectifier includes a substrate, a high-side transistor, a low-side transistor, and an inductor. The high-side transistor is above the substrate and includes a first gate structure, a first source region and a first drain region in the substrate and on opposite sides of the first gate structure, and a first pickup region in the substrate and laterally adjacent to the first source region along a first direction. The low-side transistor is above the substrate and includes a second gate structure, a second source region and a second drain region in the substrate and on opposite sides of the second gate structure. The inductor is electrically connected to the first source region of the high-side transistor and the second drain region of the low-side transistor. The first gate structure includes a first gate dielectric and a second gate dielectric adjacent to the first gate dielectric, wherein the first gate dielectric is thicker than the second gate dielectric.

[0200] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and such equivalent constructions may be variously modified, substituted, and replaced herein without departing from the spirit and scope of the present disclosure.

Claims

1. A rectifier, characterized in that: Include: a substrate; A first transistor above the substrate comprises: a first gate structure; and a first source region and a first drain region in the substrate and on opposite sides of the first gate structure; A second transistor above the substrate comprises: a second gate structure; and a second source region and a second drain region in the substrate and on opposite sides of the second gate structure; a first gate contact socket electrically connected to the first gate structure; a first source contact socket electrically connected to the first source region; a first metal wiring contacting a top surface of the first gate contact socket and a top surface of the first source contact socket; and An inductor is electrically connected to the first drain region of the first transistor and the second source region of the second transistor.

2. The rectifier according to claim 1, characterized in that The first transistor further includes a pick-up region in the substrate, the pick-up region and the first source region have opposite conductivity types, and the rectifier further includes a pick-up contact socket electrically connected to the pick-up region, wherein the first metal wiring also contacts a top surface of the pick-up contact socket.

3. The rectifier according to claim 1, characterized in that in, The first transistor further includes a first pickup region in the substrate and laterally adjacent to the first source region along a first direction, The second transistor further includes a second pickup region in the substrate and laterally adjacent to the second source region along a second direction perpendicular to the first direction, the second pickup region and the second source region having opposite conductivity types.

4. The rectifier according to claim 3, characterized in that A lateral distance between the first pickup region and the first gate structure is greater than a lateral distance between the second pickup region and the second gate structure.

5. The rectifier according to claim 1, characterized in that Further including: a second gate contact socket electrically connected to the second gate structure; a second source contact socket electrically connected to the second source region; A second metal wiring in contact with a top surface of the second gate contact socket; and A third metal connection contacts a top surface of the second source contact socket, wherein the second metal connection is laterally separated from the third metal connection.

6. A rectifier, characterized in that: Include: a substrate; A high-side transistor above the substrate includes: a first gate structure; a first source region and a first drain region in the substrate and on opposite sides of the first gate structure; and a first pickup region in the substrate and laterally adjacent to the first source region along a first direction; A low-side transistor above the substrate includes: a second gate structure; a second source region and a second drain region in the substrate and on opposite sides of the second gate structure; and a second pickup region in the substrate and laterally adjacent to the second source region along a second direction perpendicular to the first direction; and An inductor is electrically connected to the first source region of the high-side transistor and the second drain region of the low-side transistor.

7. The rectifier according to claim 6, characterized in that Further including: a first gate contact socket electrically connected to the second gate structure; a first source contact socket electrically connected to the second source region; a first pickup contact socket electrically connected to the second pickup region; and A first metal wire contacts a top surface of the first gate contact socket, a top surface of the first source contact socket, and a top surface of the first pickup contact socket.

8. The rectifier according to claim 6, characterized in that Further including: A plurality of first source contact sockets electrically connected to the first source region; and A plurality of second source contact sockets are electrically connected to the second source region, wherein a number of the first source contact sockets is less than a number of the second source contact sockets.

9. The rectifier according to claim 6, characterized in that Further including: A plurality of first pickup contact sockets electrically connected to the first pickup region; and A plurality of second pickup contact sockets are electrically connected to the second pickup region, wherein a number of the first pickup contact sockets is less than a number of the second pickup contact sockets.

10. A rectifier, characterized in that: Include: a substrate; A high-side transistor above the substrate includes: a first gate structure, wherein the first gate structure comprises a first gate dielectric and a second gate dielectric adjacent to the first gate dielectric, wherein the first gate dielectric is thicker than the second gate dielectric; a first source region and a first drain region in the substrate and on opposite sides of the first gate structure; and a first pickup region in the substrate and laterally adjacent to the first source region along a first direction; A low-side transistor above the substrate includes: a second gate structure; and a second source region and a second drain region in the substrate and on opposite sides of the second gate structure; and An inductor is electrically connected to the first source region of the high-side transistor and the second drain region of the low-side transistor.

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