Camera frame rate monitoring circuit

Abstract

The utility model discloses a camera frame rate monitoring circuit. Comprising a video synchronization signal separation module used for receiving and decomposing video signals of a camera and outputting pulse signals according to the frame rate of the video signals, and a single-chip microcomputer module used for counting the number of the pulse signals and outputting driving signals. According to the utility model, video signals shot by the AHD camera are received, the video signals are decomposed into pulse signals, the number of the received pulse signals is analyzed by using the single-chip microcomputer, and the alarm signal is sent out by using the single-chip microcomputer. And the number of the received pulses is displayed through the nixie tube, so that people can observe the number of frames output by the AHD camera more visually. Meanwhile, the buzzer module is arranged, so that an alarm signal can be sent out under the condition that the frame number is insufficient, and testers can conveniently handle in time.

Description

Technical Field

[0001] The utility model relates to the technical field of camera frame rate detection, in particular to a camera frame rate monitoring circuit. Background Art

[0002] When producing analog high-definition AHD cameras, the video output of the camera is usually connected to a screen to display the image, and the aging tester observes whether the image is normal.

[0003] When a simulated high-definition AHD camera experiences slight frame loss, it will not affect the image observed on the screen, but it is difficult to observe directly with the naked eye, making it difficult to meet the requirement that the vehicle-mounted camera should not experience frame loss during operation. Utility Model Content

[0004] The utility model aims to disclose a camera frame rate monitoring circuit, which solves the problem that it is difficult to see whether the camera has lost frames by naked eyes in the existing vehicle-mounted camera aging test.

[0005] In order to achieve the above purpose, the utility model adopts the following technical solutions:

[0006] A camera frame rate monitoring circuit comprises: a video synchronization signal separation module for receiving and decomposing a video signal of a camera and outputting a pulse signal according to the frame rate of the video signal, a single chip computer module for counting the number of the pulse signals and outputting a driving signal, a digital tube module for displaying the number of pulse signals according to the driving signal, and a buzzer module for issuing an alarm signal;

[0007] The output end of the video synchronization signal separation module is connected to the input end of the single chip microcomputer module;

[0008] The first output terminal of the single chip microcomputer module is connected to the buzzer module;

[0009] The second output end of the single chip microcomputer module is connected to the digital tube module.

[0010] Optionally, the video synchronization signal separation module includes: a video synchronization signal separation chip, a first capacitor, a second capacitor and a first resistor;

[0011] The second pin of the video synchronization signal separation chip is connected to the camera through the first capacitor;

[0012] The third pin of the video synchronization signal separation chip is connected to the single-chip microcomputer module;

[0013] The fourth pin of the video synchronization signal separation chip is grounded;

[0014] The sixth pin of the video synchronization signal separation chip is connected to the ground after passing through the first resistor or the second capacitor;

[0015] The eighth pin of the video synchronization signal separation chip is connected to the VCC voltage terminal.

[0016] Optionally, the single-chip microcomputer module includes: a single-chip microcomputer chip, a third capacitor, a fourth capacitor, a fifth capacitor and a sixth capacitor;

[0017] The ninth pin of the single-chip microcomputer chip is connected to the VDD voltage terminal; the ninth pin of the single-chip microcomputer chip is also connected to the ground after passing through the third capacitor, the fourth capacitor, the fifth capacitor and the sixth capacitor respectively;

[0018] The tenth pin of the single-chip microcomputer chip is connected to the buzzer module;

[0019] The eleventh pin of the single-chip microcomputer chip is connected to the video synchronization signal separation module;

[0020] The 24th, 36th and 48th pins of the single-chip microcomputer chip are all connected to the VDD voltage terminal;

[0021] The eighth pin, the twenty-third pin, the thirty-fifth pin and the forty-seventh pin of the single-chip microcomputer chip are all grounded;

[0022] The 18th pin, 19th pin, 20th pin, 39th pin, 40th pin, 41st pin, 42nd pin, 43rd pin, 45th pin, 46th pin, 21st pin, 22nd pin, 25th pin, 26th pin, 27th pin and 28th pin of the single-chip microcomputer chip are all connected to the digital tube module.

[0023] Optionally, the digital tube module includes: a first digital tube unit for displaying tens digits and a second digital tube unit for displaying ones digits, and the first digital tube unit and the second digital tube unit are respectively connected to the single-chip microcomputer module.

[0024] Optionally, the first digital tube unit includes a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a first digital tube driving chip and a first digital tube chip;

[0025] The first pin and the twentieth pin of the first digital tube driving chip are both connected to the VDD voltage terminal;

[0026] The tenth pin and the nineteenth pin of the first digital tube driving chip are both grounded;

[0027] The second pin, the third pin, the fourth pin, the fifth pin, the sixth pin, the seventh pin, the eighth pin and the ninth pin of the first digital tube driving chip are all connected to the single-chip microcomputer module;

[0028] The eighteenth pin of the first digital tube driving chip is connected to the first pin of the first digital tube chip through a second resistor;

[0029] The seventeenth pin of the first digital tube driving chip is connected to the second pin of the first digital tube chip through a third resistor;

[0030] The sixteenth pin of the first digital tube driving chip is connected to the third pin of the first digital tube chip through a fourth resistor;

[0031] The fifteenth pin of the first digital tube driving chip is connected to the fourth pin of the first digital tube chip through a fifth resistor;

[0032] The fourteenth pin of the first digital tube driving chip is connected to the fifth pin of the first digital tube chip through a sixth resistor;

[0033] The thirteenth pin of the first digital tube driving chip is connected to the sixth pin of the first digital tube chip through the seventh resistor;

[0034] The twelfth pin of the first digital tube driving chip is connected to the seventh pin of the first digital tube chip through an eighth resistor;

[0035] The eleventh pin of the first digital tube driving chip is connected to the eighth pin of the first digital tube chip through a ninth resistor;

[0036] The ninth pin of the first digital tube chip is grounded.

[0037] Optionally, the second digital tube unit includes a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, a second digital tube driving chip and a second digital tube chip;

[0038] The first pin and the twentieth pin of the second digital tube driving chip are both connected to the VDD voltage terminal;

[0039] The tenth pin and the nineteenth pin of the second digital tube driver chip are both grounded;

[0040] The second pin, the third pin, the fourth pin, the fifth pin, the sixth pin, the seventh pin, the eighth pin and the ninth pin of the second digital tube driving chip are all connected to the single chip microcomputer module;

[0041] The eighteenth pin of the second digital tube driving chip is connected to the first pin of the second digital tube chip through the tenth resistor;

[0042] The seventeenth pin of the second digital tube driving chip is connected to the second pin of the second digital tube chip through the eleventh resistor;

[0043] The sixteenth pin of the second digital tube driving chip is connected to the third pin of the second digital tube chip through the twelfth resistor;

[0044] The fifteenth pin of the second digital tube driving chip is connected to the fourth pin of the second digital tube chip through the thirteenth resistor;

[0045] The fourteenth pin of the second digital tube driving chip is connected to the fifth pin of the second digital tube chip through the fourteenth resistor;

[0046] The thirteenth pin of the second digital tube driving chip is connected to the sixth pin of the second digital tube chip through the fifteenth resistor;

[0047] The twelfth pin of the second digital tube driving chip is connected to the seventh pin of the second digital tube chip through the sixteenth resistor;

[0048] The eleventh pin of the second digital tube driving chip is connected to the eighth pin of the second digital tube chip through the seventeenth resistor;

[0049] The ninth pin of the second digital tube chip is grounded.

[0050] Optionally, the buzzer module includes: a buzzer and a triode;

[0051] The base of the transistor is connected to the single-chip microcomputer module; the collector of the transistor is connected to the negative electrode of the buzzer; the emitter of the transistor is grounded; the positive electrode of the buzzer is connected to the VDD voltage terminal

[0052] Optionally, it further includes a voltage regulating module; the voltage regulating module includes: a voltage regulating chip, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, an eighteenth resistor, a nineteenth resistor and a first inductor;

[0053] The first pin of the voltage regulating chip is connected to the sixth pin of the voltage regulating chip after passing through the ninth capacitor;

[0054] The second pin of the voltage regulating chip is grounded;

[0055] The third pin of the voltage regulating chip is grounded after passing through the nineteenth resistor;

[0056] The fourth pin of the voltage regulating chip is connected to the fifth pin of the voltage regulating chip;

[0057] The fifth pin of the voltage regulating chip is connected to the VCC voltage terminal; the fifth pin of the voltage regulating chip is also connected to the ground after passing through the seventh capacitor or the eighth capacitor;

[0058] The sixth pin of the voltage regulating chip is connected to the VDD voltage terminal after passing through the first inductor; the sixth pin of the voltage regulating chip is also connected to the ground after passing through the first inductor and the tenth capacitor in sequence; the sixth pin of the voltage regulating chip is also connected to the ground after passing through the first inductor, the eighteenth resistor and the nineteenth resistor in sequence.

[0059] Optionally, a crystal oscillator module is further included, wherein the crystal oscillator module includes: a crystal oscillator chip, a twentieth resistor, an eleventh inductor and a twelfth inductor;

[0060] The first pin of the crystal oscillator chip is connected to the single-chip microcomputer module;

[0061] The first pin of the crystal oscillator chip is also grounded after passing through an eleventh capacitor;

[0062] The first pin of the crystal oscillator chip is connected to the ground after passing through the twentieth resistor and the twelfth capacitor in sequence;

[0063] The second pin of the crystal oscillator chip is grounded;

[0064] The third pin of the crystal oscillator chip is connected to the single-chip microcomputer module;

[0065] The fourth pin of the crystal oscillator chip is grounded.

[0066] Compared with the prior art, the utility model has the following beneficial effects:

[0067] The utility model provides a camera frame rate monitoring circuit, including: a video synchronization signal separation module for receiving and decomposing a video signal of a camera and outputting a pulse signal according to the frame rate of the video signal, a single-chip computer module for counting the number of the pulse signals and outputting a driving signal, a digital tube module for displaying the number of pulse signals according to the driving signal, and a buzzer module for issuing an alarm signal; the output end of the video synchronization signal separation module is connected to the input end of the single-chip computer module; the first output end of the single-chip computer module is connected to the buzzer module; the second output end of the single-chip computer module is connected to the digital tube module; in summary, the utility model receives the video signal shot by the AHD camera, and decomposes it into a pulse signal, uses the single-chip computer to analyze the number of received pulse signals, and displays the received number of pulses through a digital tube, so that people can more intuitively observe the number of frames output by the AHD camera. At the same time, a buzzer module is provided, which can issue an alarm signal when the number of frames is insufficient, so that the tester can handle it in time. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0069] Figure 1 This is a circuit schematic diagram of a camera frame rate monitoring circuit of the utility model;

[0070] Figure 2 This is the circuit schematic diagram of the voltage regulator module;

[0071] Figure 3 This is the circuit schematic of the crystal oscillator module; DETAILED DESCRIPTION

[0072] In the present utility model, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present utility model can be understood according to the specific circumstances. The terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features.

[0073] In the present invention, unless otherwise clearly specified and limited, the first feature being "above" or "below" the second feature may include the first and second features being in direct contact, or the first and second features being in contact not directly but through another feature between them. Moreover, the first feature being "above", "above" and "above" the second feature includes the first feature being directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. The first feature being "below", "below" and "below" the second feature includes the first feature being directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature. The terms "vertical", "horizontal", "left", "right", "above", "below" and similar expressions are for illustrative purposes only, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0074] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments.

[0075] Embodiment 1

[0076] like Figure 1-3 A camera frame rate monitoring circuit shown includes: a video synchronization signal separation module for receiving and decomposing a video signal of a camera and outputting a pulse signal according to the frame rate of the video signal, a single-chip computer module for counting the number of the pulse signals and outputting a driving signal, a digital tube module for displaying the number of pulse signals according to the driving signal, and a buzzer module for issuing an alarm signal; the output end of the video synchronization signal separation module is connected to the input end of the single-chip computer module; the first output end of the single-chip computer module is connected to the buzzer module; the second output end of the single-chip computer module is connected to the digital tube module.

[0077] Specifically, the video signal is output and displayed by scanning line by line, and to output a frame of video signal, it is necessary to scan the odd and even lines respectively. Therefore, when outputting a frame of video, two pulse signals will be repeatedly generated, corresponding to the odd and even lines respectively. Then the pulse signal is input into the single-chip microcomputer, and the number of received pulse signals is analyzed by the single-chip microcomputer, and the number of received pulses is displayed through the digital tube, which enables people to observe the number of frames output by the AHD camera more intuitively. At the same time, a buzzer module is set up to send out an alarm signal when the number of frames is insufficient, so that the test personnel can handle it in time.

[0078] Furthermore, the video synchronization signal separation module includes: a video synchronization signal separation chip U1, a first capacitor C1, a second capacitor C2 and a first resistor R1; the second pin of the video synchronization signal separation chip U1 is connected to the camera after passing through the first capacitor C1; the third pin of the video synchronization signal separation chip U1 is connected to the single-chip computer module; the fourth pin of the video synchronization signal separation chip U1 is grounded; the sixth pin of the video synchronization signal separation chip U1 is grounded after passing through the first resistor R1 or the second capacitor C2; the eighth pin of the video synchronization signal separation chip U1 is connected to the VCC voltage terminal.

[0079] Video synchronization separation chip (LM1881), pin 2 inputs AHD video signal, and pin 3 outputs pulse waveform of odd and even fields. The AHD signal output mode is interlaced scanning, that is, outputting odd field and then even field, and one frame of image has 2 field signals. LM1881 uses the blank interval between odd field and even field to generate corresponding high and low levels, and finally outputs pulses, that is, 2 pulses are output per frame. NTSC system is 30 frames, 60 pulses are output per second, and PAL system is 25 frames, 50 pulses are output per second.

[0080] Furthermore, the single-chip microcomputer module includes: a single-chip microcomputer chip U2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5 and a sixth capacitor C6; the ninth pin of the single-chip microcomputer chip U2 is connected to the VDD voltage terminal; the ninth pin of the single-chip microcomputer chip U2 is also connected to the ground after passing through the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5 and the sixth capacitor C6; the tenth pin of the single-chip microcomputer chip U2 is connected to the buzzer module; the eleventh pin of the single-chip microcomputer chip U2 is connected to the video synchronization signal separation module; the single-chip microcomputer chip The 24th, 36th and 48th pins of the chip U2 are all connected to the VDD voltage terminal; the 8th, 23rd, 35th and 47th pins of the single-chip microcomputer chip U2 are all grounded; the 18th, 19th, 20th, 39th, 40th, 41st, 42nd, 43rd, 45th, 46th, 21st, 22nd, 25th, 26th, 27th and 28th pins of the single-chip microcomputer chip U2 are all connected to the digital tube module.

[0081] The single-chip microcomputer chip uses the STM32F103 single-chip microcomputer chip, which counts the number of pulses received per second and determines whether the video shot by the HAD camera has lost frames by the number of pulses. In the case of frame loss, an alarm is issued. At the same time, the digital tube is driven to output pulse data. The working principle of the single-chip microcomputer: the single-chip microcomputer initializes the variable Num to 0, starts the interrupt timer for 1s, and the variable Num+1 is interrupted by the rising edge of the pin PA1 pulse until the interrupt is reached after the 1s time of the timer T1, and drives the digital tube to display Num, and judges whether Num is equal to 50 or 60. If it is equal, the count is reinitialized, otherwise the buzzer is driven to alarm.

[0082] Furthermore, the digital tube module includes: a first digital tube unit for displaying tens digits and a second digital tube unit for displaying ones digits, and the first digital tube unit and the second digital tube unit are respectively connected to the single chip microcomputer module.

[0083] Furthermore, the first digital tube unit includes a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a first digital tube driver chip U3 and a first digital tube chip D1; the first pin and the twentieth pin of the first digital tube driver chip U3 are both connected to the VDD voltage terminal; the tenth pin and the nineteenth pin of the first digital tube driver chip U3 are both grounded; the second pin, the third pin, the fourth pin, the fifth pin, the sixth pin, the seventh pin, the eighth pin and the ninth pin of the first digital tube driver chip U3 are all connected to the single-chip microcomputer module; the eighteenth pin of the first digital tube driver chip U3 is connected to the first pin of the first digital tube chip D1 after passing through the second resistor R2; the seventeenth pin of the first digital tube driver chip U3 is connected to the first digital tube chip D1 after passing through the third resistor R3 The second pin of D1 is connected; the sixteenth pin of the first digital tube driver chip U3 is connected to the third pin of the first digital tube chip D1 after passing through the fourth resistor R4; the fifteenth pin of the first digital tube driver chip U3 is connected to the fourth pin of the first digital tube chip D1 after passing through the fifth resistor R5; the fourteenth pin of the first digital tube driver chip U3 is connected to the fifth pin of the first digital tube chip D1 after passing through the sixth resistor R6; the thirteenth pin of the first digital tube driver chip U3 is connected to the sixth pin of the first digital tube chip D1 after passing through the seventh resistor R7; the twelfth pin of the first digital tube driver chip U3 is connected to the seventh pin of the first digital tube chip D1 after passing through the eighth resistor R8; the eleventh pin of the first digital tube driver chip U3 is connected to the eighth pin of the first digital tube chip D1 after passing through the ninth resistor R9; the ninth pin of the first digital tube chip D1 is grounded.

[0084] Further, the second digital tube unit includes a tenth resistor R, an eleventh resistor R, a twelfth resistor R, a thirteenth resistor R, a fourteenth resistor R, a fifteenth resistor R, a sixteenth resistor R, a seventeenth resistor R, a second digital tube driver chip U4 and a second digital tube chip D2; the first pin and the twentieth pin of the second digital tube driver chip U4 are both connected to the VDD voltage terminal; the tenth pin and the nineteenth pin of the second digital tube driver chip U4 are both grounded; the second pin, the third pin, the fourth pin, the fifth pin, the sixth pin, the seventh pin, the eighth pin and the ninth pin of the second digital tube driver chip U4 are all connected to the single-chip microcomputer module; the eighteenth pin of the second digital tube driver chip U4 is connected to the first pin of the second digital tube chip D2 after passing through the tenth resistor R10; the seventeenth pin of the second digital tube driver chip U4 is connected to the second pin of the second digital tube chip D2 after passing through the eleventh resistor R11 The sixteenth pin of the second digital tube driver chip U4 is connected to the third pin of the second digital tube chip D2 after passing through the twelfth resistor R12; the fifteenth pin of the second digital tube driver chip U4 is connected to the fourth pin of the second digital tube chip D2 after passing through the thirteenth resistor R13; the fourteenth pin of the second digital tube driver chip U4 is connected to the fifth pin of the second digital tube chip D2 after passing through the fourteenth resistor R14; the thirteenth pin of the second digital tube driver chip U4 is connected to the sixth pin of the second digital tube chip D2 after passing through the fifteenth resistor R15; the twelfth pin of the second digital tube driver chip U4 is connected to the seventh pin of the second digital tube chip D2 after passing through the sixteenth resistor R16; the eleventh pin of the second digital tube driver chip U4 is connected to the eighth pin of the second digital tube chip D2 after passing through the seventeenth resistor R17; the ninth pin of the second digital tube chip D2 is grounded.

[0085] The first digital tube driver chip and the second digital tube driver chip both use a digital tube driver chip of model: 74HC245. The digital tube chip uses an 8-bit common cathode digital tube, which can correspond to the display frame number.

[0086] Furthermore, the buzzer module includes: a buzzer B1 and a transistor Q1; the base of the transistor Q1 is connected to the single-chip microcomputer module; the collector of the transistor Q1 is connected to the negative electrode of the buzzer B1; the emitter of the transistor Q1 is grounded; and the positive electrode of the buzzer B1 is connected to the VDD voltage terminal.

[0087] The base of the transistor controls whether the transistor Q1 is turned on. When the base is at a high level, the transistor Q1 is turned on, the cathode of the buzzer B1 is grounded, and the buzzer B1 is turned on. When the base is at a low level, the transistor Q1 is turned off, the cathode of the buzzer B1 is not grounded, and therefore the buzzer B1 does not work.

[0088] Furthermore, it also includes a voltage regulating module; the voltage regulating module includes: a voltage regulating chip, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, an eighteenth resistor, a nineteenth resistor and a first inductor; the first pin of the voltage regulating chip is connected to the sixth pin of the voltage regulating chip after passing through the ninth capacitor; the second pin of the voltage regulating chip is grounded; the third pin of the voltage regulating chip is grounded after passing through the nineteenth resistor; the fourth pin of the voltage regulating chip is connected to the fifth pin of the voltage regulating chip; the fifth pin of the voltage regulating chip is connected to the VCC voltage terminal; the fifth pin of the voltage regulating chip is also grounded after passing through the seventh capacitor or the eighth capacitor respectively; the sixth pin of the voltage regulating chip is connected to the VDD voltage terminal after passing through the first inductor; the sixth pin of the voltage regulating chip is also grounded after passing through the first inductor and the tenth capacitor in sequence; the sixth pin of the voltage regulating chip is also grounded after passing through the first inductor, the eighteenth resistor and the nineteenth resistor in sequence.

[0089] Furthermore, it also includes a crystal oscillator module, which includes: a crystal oscillator chip, a twentieth resistor, an eleventh inductor and a twelfth inductor; the first pin of the crystal oscillator chip is connected to the single-chip computer module; the first pin of the crystal oscillator chip is also grounded after passing through the eleventh capacitor; the first pin of the crystal oscillator chip is grounded after passing through the twentieth resistor and the twelfth capacitor in sequence; the second pin of the crystal oscillator chip is grounded; the third pin of the crystal oscillator chip is connected to the single-chip computer module; and the fourth pin of the crystal oscillator chip is grounded.

[0090] In summary, the present application decomposes the video signal captured by the AHD camera, generates a corresponding pulse signal, and then inputs the pulse signal into the single-chip microcomputer, uses the single-chip microcomputer to analyze the number of received pulse signals, and displays the number of received pulses through a digital tube, so that people can more intuitively observe the number of frames output by the AHD camera. At the same time, a buzzer module is set up to send out an alarm signal when the number of frames is insufficient, so that the tester can handle it in time.

[0091] The present invention is not limited to the above-mentioned embodiments. If various changes or modifications to the present invention do not depart from the spirit and scope of the present invention, and if these changes and modifications fall within the claims of the present invention and the scope of equivalent technologies, the present invention is also intended to include these changes and modifications.

Claims

1. A camera frame rate monitoring circuit, characterized in that: include: A video synchronization signal separation module for receiving and decomposing the video signal of the camera and outputting a pulse signal according to the frame rate of the video signal, a single-chip computer module for counting the number of the pulse signals and outputting a driving signal, a digital tube module for displaying the number of pulse signals according to the driving signal, and a buzzer module for issuing an alarm signal; The output end of the video synchronization signal separation module is connected to the input end of the single chip microcomputer module; The first output terminal of the single chip microcomputer module is connected to the buzzer module; The second output end of the single chip microcomputer module is connected to the digital tube module.

2. A camera frame rate monitoring circuit according to claim 1, characterized in that: The video synchronization signal separation module includes: a video synchronization signal separation chip, a first capacitor, a second capacitor and a first resistor; The second pin of the video synchronization signal separation chip is connected to the camera through the first capacitor; The third pin of the video synchronization signal separation chip is connected to the single-chip microcomputer module; The fourth pin of the video synchronization signal separation chip is grounded; The sixth pin of the video synchronization signal separation chip is connected to the ground after passing through the first resistor or the second capacitor; The eighth pin of the video synchronization signal separation chip is connected to the VCC voltage terminal.

3. A camera frame rate monitoring circuit according to claim 1, characterized in that: The single-chip computer module comprises: a single-chip computer chip, a third capacitor, a fourth capacitor, a fifth capacitor and a sixth capacitor; The ninth pin of the single-chip microcomputer chip is connected to the VDD voltage terminal; the ninth pin of the single-chip microcomputer chip is also connected to the ground after passing through the third capacitor, the fourth capacitor, the fifth capacitor and the sixth capacitor respectively; The tenth pin of the single-chip microcomputer chip is connected to the buzzer module; The eleventh pin of the single-chip microcomputer chip is connected to the video synchronization signal separation module; The 24th, 36th and 48th pins of the single-chip microcomputer chip are all connected to the VDD voltage terminal; The eighth pin, the twenty-third pin, the thirty-fifth pin and the forty-seventh pin of the single-chip microcomputer chip are all grounded; The 18th pin, 19th pin, 20th pin, 39th pin, 40th pin, 41st pin, 42nd pin, 43rd pin, 45th pin, 46th pin, 21st pin, 22nd pin, 25th pin, 26th pin, 27th pin and 28th pin of the single-chip microcomputer chip are all connected to the digital tube module.

4. A camera frame rate monitoring circuit according to claim 1, characterized in that: The digital tube module comprises: a first digital tube unit for displaying tens digits and a second digital tube unit for displaying ones digits, and the first digital tube unit and the second digital tube unit are respectively connected to the single chip microcomputer module.

5. A camera frame rate monitoring circuit according to claim 4, characterized in that: The first digital tube unit includes a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a first digital tube driving chip and a first digital tube chip; The first pin and the twentieth pin of the first digital tube driving chip are both connected to the VDD voltage terminal; The tenth pin and the nineteenth pin of the first digital tube driving chip are both grounded; The second pin, the third pin, the fourth pin, the fifth pin, the sixth pin, the seventh pin, the eighth pin and the ninth pin of the first digital tube driving chip are all connected to the single-chip microcomputer module; The eighteenth pin of the first digital tube driving chip is connected to the first pin of the first digital tube chip through a second resistor; The seventeenth pin of the first digital tube driving chip is connected to the second pin of the first digital tube chip through a third resistor; The sixteenth pin of the first digital tube driving chip is connected to the third pin of the first digital tube chip through a fourth resistor; The fifteenth pin of the first digital tube driving chip is connected to the fourth pin of the first digital tube chip through a fifth resistor; The fourteenth pin of the first digital tube driving chip is connected to the fifth pin of the first digital tube chip through a sixth resistor; The thirteenth pin of the first digital tube driving chip is connected to the sixth pin of the first digital tube chip through the seventh resistor; The twelfth pin of the first digital tube driving chip is connected to the seventh pin of the first digital tube chip through an eighth resistor; The eleventh pin of the first digital tube driving chip is connected to the eighth pin of the first digital tube chip through a ninth resistor; The ninth pin of the first digital tube chip is grounded.

6. A camera frame rate monitoring circuit according to claim 4, characterized in that: The second digital tube unit includes a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, a second digital tube driving chip and a second digital tube chip; The first pin and the twentieth pin of the second digital tube driving chip are both connected to the VDD voltage terminal; The tenth pin and the nineteenth pin of the second digital tube driver chip are both grounded; The second pin, the third pin, the fourth pin, the fifth pin, the sixth pin, the seventh pin, the eighth pin and the ninth pin of the second digital tube driving chip are all connected to the single chip microcomputer module; The eighteenth pin of the second digital tube driving chip is connected to the first pin of the second digital tube chip through the tenth resistor; The seventeenth pin of the second digital tube driving chip is connected to the second pin of the second digital tube chip through the eleventh resistor; The sixteenth pin of the second digital tube driving chip is connected to the third pin of the second digital tube chip through the twelfth resistor; The fifteenth pin of the second digital tube driving chip is connected to the fourth pin of the second digital tube chip through the thirteenth resistor; The fourteenth pin of the second digital tube driving chip is connected to the fifth pin of the second digital tube chip through the fourteenth resistor; The thirteenth pin of the second digital tube driving chip is connected to the sixth pin of the second digital tube chip through the fifteenth resistor; The twelfth pin of the second digital tube driving chip is connected to the seventh pin of the second digital tube chip through the sixteenth resistor; The eleventh pin of the second digital tube driving chip is connected to the eighth pin of the second digital tube chip through the seventeenth resistor; The ninth pin of the second digital tube chip is grounded.

7. A camera frame rate monitoring circuit according to claim 1, characterized in that: The buzzer module includes: a buzzer and a triode; The base of the transistor is connected to the single-chip microcomputer module; the collector of the transistor is connected to the negative electrode of the buzzer; the emitter of the transistor is grounded; and the positive electrode of the buzzer is connected to the VDD voltage terminal.

8. A camera frame rate monitoring circuit according to claim 1, characterized in that: It also includes a voltage regulating module; the voltage regulating module includes: a voltage regulating chip, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, an eighteenth resistor, a nineteenth resistor and a first inductor; The first pin of the voltage regulating chip is connected to the sixth pin of the voltage regulating chip after passing through the ninth capacitor; The second pin of the voltage regulating chip is grounded; The third pin of the voltage regulating chip is grounded after passing through the nineteenth resistor; The fourth pin of the voltage regulating chip is connected to the fifth pin of the voltage regulating chip; The fifth pin of the voltage regulating chip is connected to the VCC voltage terminal; the fifth pin of the voltage regulating chip is also connected to the ground after passing through the seventh capacitor or the eighth capacitor; The sixth pin of the voltage regulating chip is connected to the VDD voltage terminal after passing through the first inductor; the sixth pin of the voltage regulating chip is also connected to the ground after passing through the first inductor and the tenth capacitor in sequence; the sixth pin of the voltage regulating chip is also connected to the ground after passing through the first inductor, the eighteenth resistor and the nineteenth resistor in sequence.

9. A camera frame rate monitoring circuit according to claim 1, characterized in that: Also includes a crystal oscillator module, the crystal oscillator module includes: a crystal oscillator chip, a twentieth resistor, an eleventh inductor and a twelfth inductor; The first pin of the crystal oscillator chip is connected to the single-chip microcomputer module; The first pin of the crystal oscillator chip is also grounded after passing through an eleventh capacitor; The first pin of the crystal oscillator chip is connected to the ground after passing through the twentieth resistor and the twelfth capacitor in sequence; The second pin of the crystal oscillator chip is grounded; The third pin of the crystal oscillator chip is connected to the single-chip microcomputer module; The fourth pin of the crystal oscillator chip is grounded.

Images