Delay test circuit and probe structure
By designing parallel testing branch and phase detection circuit, the local mismatch problem of the inability to detect the delay of adjacent ring oscillator gates in the prior art is solved, and the accurate detection of ring oscillator gates is achieved, which improves the test reliability.
Patent Information
- Application Number
- CN202420423762.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-05
- Publication Date
- 2024-12-13
- Estimated Expiration
- 2034-03-05
AI Technical Summary
The prior art cannot effectively test the local mismatch of two adjacent ring oscillator gates, and when testing two ring oscillators separately, it is impossible to accurately detect the local mismatch of delay due to the long distance and other circuits.
A delay detection circuit is designed. By connecting two test branches in parallel, the same vibration signal is received and the phase difference is output to detect relative delays. The phase detector and signal amplification buffer circuit are used to realize the shape of two adjacent rings. Local mismatch detection of oscillator gate delay.
The accuracy of detection of delays of two adjacent ring oscillator gates is improved, and the phase and frequency differences between the two test branches can be directly reflected, which enhances the reliability of electrical testing.
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Figure CN222167160U_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a delay detection circuit and a probe structure. Background Art
[0002] The main function of the ring oscillator in the wafer is to provide a stable oscillation signal. Currently, the test circuit of the ring oscillator in the wafer acceptance test can only test the delay of one ring oscillator, and there is no structure to test the local mismatch of the gate delay of two adjacent ring oscillators. If only two separate ring oscillators are tested, the distance between the two ring oscillators on the wafer is relatively far, and the delay obtained by the test is affected by other circuits such as the ring oscillator and the output circuit. Therefore, the local mismatch of the delay cannot be obtained based on the test results of the two separate ring oscillators.
[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Utility Model Content
[0004] The purpose of the present disclosure is to provide a delay detection circuit and a probe structure, which at least to some extent overcome the problem in the related art that the local mismatch of gate delays of two adjacent ring oscillators cannot be tested.
[0005] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by the practice of the present disclosure.
[0006] According to one aspect of the present disclosure, there is provided a delay detection circuit, comprising: two test branches connected in parallel, one of the two test branches connected in parallel comprising a first input terminal and a first output terminal, the other of the two test branches connected in parallel comprising a second input terminal and a second output terminal, the first input terminal and the second input terminal being used to receive the same oscillation signal, the first output terminal being used to output a first oscillation signal, and the second output terminal being used to output a second oscillation signal; a phase detector, the input terminal of the phase detector being respectively connected to the first output terminal and the second output terminal for receiving the first oscillation signal and the second oscillation signal, the output terminal of the phase detector being used to output a phase difference between the first oscillation signal and the second oscillation signal, the phase difference being used to detect the relative delay between the two test branches connected in parallel.
[0007] In one embodiment of the present disclosure, the test branch includes a first logic gate unit and a second logic gate unit connected in series, and the number of the second logic gate units is an even number.
[0008] In one embodiment of the present disclosure, the first logic gate unit includes one of a NAND gate and a NOR gate, wherein one input end of the first logic gate unit is used to input the start-up signal, and another input end of the first logic gate unit is used to connect to the output end of the corresponding test branch to form a loop.
[0009] In one embodiment of the present disclosure, the second logic gate unit includes one of an inverter, a NAND gate and a NOR gate.
[0010] The input end of the inverter is connected to the output end of the adjacent previous first logic gate unit, or both are connected to the output end of the adjacent previous inverter.
[0011] Both input ends of the NAND gate are connected to the output end of the adjacent previous first logic gate unit, or are connected to the output end of the adjacent previous NAND gate.
[0012] Both input ends of the NOR gate are connected to the output end of the adjacent previous first logic gate unit, or are connected to the output end of the adjacent previous NOR gate.
[0013] In one embodiment of the present disclosure, the second logic gate unit includes an XOR gate, one input end of the XOR gate is used to receive a power supply voltage, and the other input end of the XOR gate is connected to the output end of an adjacent previous first logic gate unit, or is connected to the output end of an adjacent previous XOR gate.
[0014] In one embodiment of the present disclosure, the second logic gate unit includes an XNOR gate, one input end of the XNOR gate is used for grounding, and the other input end of the XNOR gate is connected to the output end of the adjacent previous first logic gate unit, or is connected to the output end of the adjacent previous XNOR gate.
[0015] In one embodiment of the present disclosure, it also includes: a frequency divider, wherein the input end of the frequency divider is connected to the output end of the phase detector, and the output end of the frequency divider is used to output the divided signal of the phase difference; a signal amplifying buffer circuit, wherein the input end of the signal amplifying buffer circuit is connected to the output end of the frequency divider, and the output end of the signal amplifying buffer circuit outputs the relative delay generated based on the divided signal.
[0016] According to another aspect of the present disclosure, a probe structure is provided, comprising: a delay test circuit as described in any one of the above embodiments, the delay test circuit comprising two test branches in parallel, one of the two test branches in parallel comprising a first input terminal, and the other of the two test branches in parallel comprising a second input terminal; a first pin, respectively connected to the first input terminal and the second input terminal, for receiving an input start-up signal.
[0017] In one embodiment of the present disclosure, the delay test circuit further includes a signal amplifying buffer circuit, and the probe structure further includes: a second pin connected to the output end of the amplifying buffer circuit, for outputting the relative delay between the two parallel test branches.
[0018] In one embodiment of the present disclosure, it also includes: a third pin connected to the two parallel test branches and used to receive an input power supply voltage; and a fourth pin connected to the two parallel test branches and used to be grounded.
[0019] The delay detection scheme provided by the embodiments of the present disclosure inputs the same oscillation signal into two parallel test branches respectively, so that the two test branches oscillate synchronously, and respectively output a first oscillation signal and a second oscillation signal based on the same oscillation signal. Furthermore, the first oscillation signal and the second oscillation signal are input into a phase detector to obtain a relative delay that can directly reflect the difference between the two test branches, thereby obtaining the difference in phase and frequency of the AC signals output by the two test branches, so as to realize the detection of local mismatch of gate delays of two adjacent ring oscillators.
[0020] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.
[0022] Figure 1 A schematic block diagram of a delay test circuit in an embodiment of the present disclosure is shown;
[0023] Figure 2 A schematic diagram showing a test branch in an embodiment of the present disclosure is shown;
[0024] Figure 3 A schematic diagram showing another test branch in an embodiment of the present disclosure;
[0025] Figure 4 A schematic diagram showing another test branch in an embodiment of the present disclosure is shown;
[0026] Figure 5 A schematic diagram showing another test branch in an embodiment of the present disclosure;
[0027] Figure 6 A schematic diagram showing another test branch in an embodiment of the present disclosure;
[0028] Figure 7 A schematic block diagram of a delay test circuit in an embodiment of the present disclosure is shown;
[0029] Figure 8 A schematic diagram showing a first oscillation signal and a second oscillation signal in an embodiment of the present disclosure;
[0030] Fig. 9 A schematic diagram showing an output signal of a phase detector in an embodiment of the present disclosure;
[0031] Fig.10 A schematic block diagram showing a probe structure in an embodiment of the present disclosure. DETAILED DESCRIPTION
[0032] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the disclosure will be more comprehensive and complete and to fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
[0033] In addition, the accompanying drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.
[0034] In the current electrical test of wafers, the test structure only tests the delay of one ring oscillator, and does not test the local mismatch of gate delays of two adjacent ring oscillators. The structure of the ring oscillator is relatively complex and the structural area is relatively large. For two separate test structures, the distance between the two ring oscillators is relatively far, and the delay obtained by the test is affected by other circuits such as the ring oscillator and the output circuit. Therefore, testing two separate ring oscillators cannot obtain the local mismatch of delay. Among them, local mismatch refers to the phenomenon that there are differences in parameters, performance or characteristics between different parts in a circuit or system.
[0035] The delay detection scheme in this example implementation will be described in more detail below with reference to the accompanying drawings and embodiments.
[0036] like Figure 1 As shown, a delay detection circuit according to an embodiment of the present disclosure includes: two test branches connected in parallel.
[0037] Two test branches are connected in parallel, namely a first test branch 102 and a second test branch 104. The first test branch 102 includes a first input terminal 1022 and a first output terminal 1024, and the second test branch 104 includes a second input terminal 1042 and a second output terminal 1044. The first input terminal 1022 and the second input terminal 1042 are used to receive the same oscillation signal, the first output terminal 1024 is used to output a first oscillation signal, and the second output terminal 1044 is used to output a second oscillation signal.
[0038] The first test branch and the second test branch may be the same or different. When they are the same, the output result may directly reflect the frequency difference between the two test branches. When they are different, the difference detection of different signal paths may be realized.
[0039] Exemplarily, the two parallel test branches may be two parallel ring oscillators, two LC oscillators, two RC oscillators, two crystal oscillators, or two voltage-controlled oscillators.
[0040] In addition, the two parallel test branches are the same test branches, the two test main circuits are arranged side by side on the circuit board, and the distance between the two test branches is the minimum distance that will not cause any impact.
[0041] The test branch can receive an external input signal as an oscillation start signal. The external input signal can be a square wave signal or a high level signal of a received power supply voltage.
[0042] Exemplarily, the test branch is a ring oscillator, which is used to generate a clock signal of a specific frequency and realize self-oscillation through a positive feedback loop to output an alternating current oscillation signal.
[0043] The same oscillation start signal is input in parallel into the second test branch 104 to ensure that the oscillation signals generated by the two branches have the same phase reference, so as to accurately compare the delay difference between the two branches, thereby improving the measurement accuracy.
[0044] like Figure 1 As shown, the input end of the phase detector 106 is respectively connected to the first output end 1024 and the second output end 1044, for receiving the first oscillation signal and the second oscillation signal, and the output end of the phase detector 106 is used to output the phase difference between the first oscillation signal and the second oscillation signal, and the phase difference is used to detect the relative delay between the first test branch and the second test branch.
[0045] The phase detector may be a multiplication phase detector, a linear phase detector or a digital phase detector.
[0046] By measuring the phase difference between the first oscillation signal and the second oscillation signal through a phase detector, the relative delay between the first test branch and the second test branch can be measured. This is very important for the signal propagation delay between different branches in the test system and can be used to calibrate and adjust the timing of the system.
[0047] The phase detector can test the phase difference between the output first oscillation signal and the second oscillation signal, ignoring the difference in amplitude of the two ring oscillators and starting oscillation at the same time. The phase difference is approximately equal to the frequency difference of the two test branches, and the reciprocal of the frequency difference is the difference between the two gate delays.
[0048] In this embodiment, the same oscillation signal is input into two parallel test branches respectively so that the two test branches oscillate synchronously, and a first oscillation signal and a second oscillation signal based on the same oscillation signal are output respectively. Furthermore, the first oscillation signal and the second oscillation signal are input into a phase detector to detect the local mismatch of the gate delays of two adjacent ring oscillators, and obtain a relative delay that can directly reflect the difference between the two test branches, thereby obtaining the difference in phase and frequency of the AC signals output by the two test branches.
[0049] Furthermore, based on the obtained relative delay, the local variation of the delay device in the test branch, such as the transistor, can be detected, and the correlation between MOS mismatch and delay mismatch can be established, thereby making the reliability of the electrical test higher.
[0050] Among them, technicians in this field can understand that the device area and the test area are respectively set on the same wafer. The test branch in the delay test circuit described in this disclosure is the device in the wafer, so the delay test circuit is prepared by the same process as the same device in the wafer.
[0051] In one embodiment of the present disclosure, the test branch includes a first logic gate unit and a second logic gate unit connected in series, and the number of the second logic gate units is an even number.
[0052] like Figure 2 As shown, the two parallel test branches are two identical parallel ring oscillators, each ring oscillator includes a first logic gate unit 202 and an even number of second logic gate units 204, and the two parallel test branches share the same oscillation start signal.
[0053] Among them, the logic gate unit is the basic building block in the digital circuit, which is used to generate the corresponding output signal according to the logical state of the input signal. The logic gate unit includes AND gate, OR gate, NOT gate, XOR gate, etc.
[0054] In addition, the first logic gate unit and the second logic gate unit may be the same or different.
[0055] By setting an even number of second logic gate units, the test branch is composed of an odd number of logic gate units, which can ensure that the test branch stably outputs an oscillation signal in each cycle.
[0056] In one implementation of the second logic gate unit, Figure 2 As shown, the second logic gate unit includes an inverter 204 , and an input end of the inverter 204 is connected to an output end of an adjacent previous first logic gate unit 202 , or is connected to an output end of an adjacent previous inverter 204 .
[0057] In this embodiment, the logic gate unit is a basic building block in a digital circuit, and generates a corresponding output signal according to the logic state of the input signal. The first logic gate unit and the second logic gate unit can both use inverters. By connecting the first logic gate unit and the second logic gate unit in series, it means that the output of the first logic gate unit will be used as the input of the second logic gate unit. In this way, the signal is transmitted and processed between the logic gate units. Through logical inversion, signal transmission and processing, continuity and integrity, the stable output of the oscillation signal of each test branch is guaranteed to meet specific test purposes and functional requirements.
[0058] In one embodiment of the present disclosure, the first logic gate unit includes one of a NAND gate and a NOR gate, wherein one input terminal in the first logic gate unit is used to input a start-up signal, and another input terminal in the first logic gate unit is used to connect to the output terminal of the corresponding test branch, and the second logic gate unit includes any one of an inverter, a NAND gate, a NOR gate, an XOR gate and an XNOR gate.
[0059] Where, NAND stands for Not AND Gate, i.e., an AND gate followed by a NOT gate, and the output of NAND is the complement of the AND gate, i.e., the output of the NAND gate is 0 (low) only when both the inputs are 1 (high), in all other cases, its output is 1 (high).
[0060] NOR gate stands for NOT-OR gate, which is an OR gate followed by a NOT gate. The output of the NOR gate is 1 (HIGH) if and only if both of its inputs are 0 (LOW), in all other input combinations, the output of the NOR gate is 0 (LOW).
[0061] The XOR gate is equivalent to an XOR gate followed by a NOT gate. If the two inputs of the XNOR Gate are the same, that is, both inputs are 0 (low) or 1 (high), then the output of the XNOR Gate is 1 (high). If the inputs of the XNOR Gate are different, its output is 0 (low).
[0062] The XNOR gate, also known as the XNOR gate, is an XOR gate followed by a NOT gate. It has 2 input terminals and 1 output terminal. When one and only one of the two input terminals is at a low level (logic 0), the output is a low level. That is, when the input levels are the same, the output is a high level (logic 1).
[0063] In another implementation of the second logic gate unit, the second logic gate unit includes a NOR gate, and both input ends of the NOR gate are connected to the output end of the adjacent previous first logic gate unit, or are connected to the output end of the adjacent previous NOR gate.
[0064] like Figure 3As shown, the first logic gate unit includes the first NAND gate 302. Initially, the oscillation start signal is low level, the output end of the first NAND gate 302 outputs a high level signal, and the two input ends of the first NOR gate 304 are both input with high level signals, and the output is a low level signal. After repeating an even number of NOR gates, the output end of the last NOR gate, i.e., the second input end of the first logic gate unit, is high level, and the output end of the first logic gate unit is still high level, and the signal does not oscillate. At this time, a high level signal is input as the oscillation start signal to one input end of the first NAND gate 302, and the other input end maintains the previous high level signal, so the first NAND gate outputs a low level, and the two input ends of the first NOR gate 304 are both input with low level, and the output is a high level. Repeat the above steps, and the last NOR gate outputs a low level signal. At this time, the first input end of the first NAND gate 302 is the oscillation start signal, a high level signal, and the second input end is a low level signal. The first NAND gate 302 outputs a high potential, which is opposite to the signal after the oscillation starts, so as to realize the oscillation start of the ring oscillator until a stable oscillation signal is output.
[0065] Exemplarily, in the ring oscillator, one input end of the first logic gate unit is used to receive an oscillation start signal, and the other input end is connected to the output end of the corresponding test branch to form a closed-loop structure, so that the signal is cyclically transmitted in the test branch.
[0066] In the ring oscillator, both input ends of the NOR gate are connected to the output end of the adjacent previous first logic gate unit, or to the output end of the adjacent previous NOR gate. This connection method ensures that the signal can be further logically processed when passing through the second logic gate unit, and feedback is formed between adjacent first logic gate units to maintain the oscillation state.
[0067] In this embodiment, a closed-loop structure is formed by connecting an input end of the first logic gate unit to the output end of the test branch to which it belongs. This closed-loop structure allows the signal to be circulated in the test branch and maintained in a stable oscillation state after being processed by the logic gate. By way of example, the ring oscillator using the NAND gate and the NOR gate is relatively easy to start. It only needs to input a starting signal to the input end of the NAND gate, and the ring oscillator can start quickly, thereby ensuring the reliability of the relative delay detection between the two test branches.
[0068] In another implementation of the second logic gate unit, the second logic gate unit includes a NAND gate, and both input ends of the NAND gate are connected to the output end of an adjacent previous first logic gate unit, or are connected to the output end of an adjacent previous NAND gate.
[0069] like Figure 4As shown, the test branch includes an odd number of NAND gates 402, wherein the first NAND gate 402 is a first logic gate unit, and the following NAND gates 402 are second logic gate units. A high level signal is input as a start-up signal to an input terminal of the first NAND gate, and the NAND gates work as follows: the first NAND gate generates an output signal according to the logic states of its two inputs. If one of the two inputs is at a low level (0), the output is a high level (1); if both inputs are at a high level (1), the output is a low level (0).
[0070] The output signal of the first NAND gate is connected to the two input terminals of the second NAND gate. Each NAND gate passes the inverted version of its input signal to the next NAND gate. In this way, through the odd number of connected NAND gates, the signal will circulate on the circular path and produce an inversion in each NAND gate. The feedback signal will be continuously inverted and eventually passed back to the other input terminal of the first NAND gate, causing it to produce a continuously changing output signal, thereby obtaining a stable oscillation signal, whose frequency is determined by the delay of the circuit elements and the transmission delay of the logic gates.
[0071] In this embodiment, a ring oscillator composed of an odd number of NAND gates is used, and its circuit is relatively simple. In addition, the ring oscillator composed of NAND gates has an oscillation frequency that is mainly determined by the delay time of the gate circuit and the number of NAND gates and is relatively stable. Therefore, the reliability of the relative delay detection between the two test branches can also be guaranteed.
[0072] In another implementation of the second logic gate unit, the second logic gate unit includes an XOR gate, one input end of the XOR gate is used to receive a high-level signal, and the other input end of the XOR gate is connected to the output end of an adjacent previous first logic gate unit, or to the output end of an adjacent previous XOR gate.
[0073] like Figure 5 As shown, the first logic gate unit is a NAND gate 502, and the second logic gate unit includes an XOR gate 504. Initially, the start-up signal is input to one input end of the NAND gate 502, and the output signal of the last XOR gate is input to the other input end of the NAND gate as a feedback signal.
[0074] When the two input signals of the XOR gate 504 are different, the output is a high level (1), otherwise the output is a low level (0), wherein the high level signal (1) is input to one input terminal of each XOR gate, and the other input terminal is connected to the output terminal of the previous XOR gate.
[0075] The start-up signal is passed through the NAND gate to obtain an output signal, which is connected to one input of the first XOR gate, and a fixed high-level signal is connected to the other input of each XOR gate. The input and output of each XOR gate are connected in turn to form a ring path.
[0076] The signal propagates in a loop on the circular path and is inverted in each XOR gate. Through the connected XOR gates, the signal will continue to invert on the circular path, thereby generating an oscillating output signal with a frequency determined by the delay of the circuit elements and the transmission delay of the logic gates.
[0077] In this embodiment, a ring oscillator is formed by a NAND gate and an even number of XOR gates connected end to end. This ring structure allows the signal to circulate in the ring to generate oscillations. Since the output and input signals of the XOR gates are different, the ring oscillator is asymmetric and can ensure the stability of the signal transmission direction in the ring.
[0078] In another implementation of the second logic gate unit, the second logic gate unit includes an XNOR gate, one input of the XNOR gate is used for grounding, and the other input of the XNOR gate is connected to the output of the adjacent previous first logic gate unit, or to the output of the adjacent previous XNOR gate.
[0079] like Figure 6 As shown, an input terminal of the NAND gate 602 inputs an oscillation start signal, which can be an external input signal or an output signal of other logic gates. The other input terminal of the NAND gate is connected to the output terminal of the last XNOR gate 604, forming a closed-loop structure, thereby forming a feedback mechanism.
[0080] One input terminal of each XNOR gate 604 is grounded, which means that these XNOR gates always receive 0 as input. Since the XNOR gates have the characteristic of outputting 1 when the input is the same, this means that the signal oscillates in the XNOR gates. When the grounded input terminals of all XNOR gates are 0, the input terminal is 1 and the output terminal is 0, and the output of the XNOR gate of the next stage is 1.
[0081] When the oscillation start signal of the first logic gate unit, namely the NAND gate 602, is at a high potential, the output is 0. After passing through an even number of XNOR gates with one input terminal grounded, the output of the last XNOR gate is also 0. At this time, since the output of the NAND gate 602 is 1, which is opposite to the previous signal, the test branch can start to oscillate.
[0082] In this embodiment, the ring oscillator is composed of a NAND gate and an even number of XNOR gates, forming a closed loop, so that the signal is circulated and transmitted therein to generate oscillation, and the reliability of the relative delay detection between the two test branches can also be ensured.
[0083] like Figure 7 As shown, in one embodiment of the present disclosure, the delay test circuit includes: a first test branch 102 and a second test branch 104 connected in parallel, a phase detector 106 , a frequency divider 702 and a signal amplification buffer circuit 704 .
[0084] The input end of the frequency divider 702 is connected to the output end of the phase detector, and the output end of the frequency divider is used to output a frequency-divided signal of the phase difference.
[0085] Among them, in the ring oscillator, the function of the frequency divider is to reduce the frequency of the oscillation signal to the required value to meet the application requirements. The frequency divider is usually composed of some logic gate circuits, such as AND gates, OR gates, NOT gates, etc., and the required frequency division function is achieved through different combinations and connection methods.
[0086] The input end of the signal amplifying buffer circuit 704 is connected to the output end of the frequency divider, and the output end of the signal amplifying buffer circuit outputs the relative delay generated based on the frequency-divided signal.
[0087] Among them, since the signal generated by the ring oscillator is usually weak, it needs to be amplified by a signal amplification buffer circuit for better application. The signal amplification buffer circuit is usually composed of some amplifiers and buffers to enhance the amplitude and stability of the signal while reducing noise and interference in the signal.
[0088] like Figure 8 As shown, the two ring oscillators start oscillating at the same time, generating the first oscillation signal 802 and the second oscillation signal 804 respectively. However, due to local variation, the delay of the two ring oscillators is different, resulting in a difference in the phase of the output signals. As the vibration period increases, the phase difference of the output signals gradually increases. When the phase difference between the two signals is 180°, the output signal amplitude is close to 0.
[0089] like Fig. 9 As shown, after the first oscillation signal and the second oscillation signal are respectively input into the phase detector, the output signal is shown as 902, and the phase difference is approximately equal to the difference between the frequencies of the two ring oscillators. The reciprocal of the frequency 902 is the gate delay.
[0090] For example, Fig. 9 The phase detector output signal V out =Vdd*[sin(2πf out1 t)+sin(2πf out2 t)], the frequency difference f≈|f out1 -f out2 |.
[0091] like Fig.10As shown, a probe structure according to an embodiment of the present disclosure includes: a delay test circuit 12 of any one of the above embodiments, the delay test circuit includes two test branches in parallel, one of the two test branches in parallel includes a first input terminal, and the other of the two test branches in parallel includes a second input terminal; a first pin 14, respectively connected to the first input terminal and the second input terminal, for receiving an input start-up signal.
[0092] Illustratively, the probe structure may be a probe station or a probe card.
[0093] In one embodiment of the present disclosure, the delay test circuit further includes a signal amplifying buffer circuit, and the probe structure further includes: a second pin 16 connected to the output end of the amplifying buffer circuit, for outputting the relative delay between the two parallel test branches.
[0094] In one embodiment of the present disclosure, it further includes: a third pin 18 connected to two test branches in parallel and used to receive an input power supply voltage; and a fourth pin 20 connected to the two test branches in parallel and used to be grounded.
[0095] Exemplarily, the two parallel test branches include a first input terminal and a second input terminal respectively. They are connected in parallel, which means that the signals are processed on the two branches at the same time. The phase detector is used to detect the phase difference between the signals on the two test branches. The phase detector can analyze the waveforms of the two signals and determine the timing phase difference between them. The frequency divider divides the input high-frequency signal to reduce its frequency so that it is more suitable for processing by the phase detector. The signal amplification buffer circuit is used to enhance the signal amplitude output by the two test branches and provide signal stability.
[0096] In addition, the first pin is connected to the first input terminal and the second input terminal respectively, and is used to receive an input oscillation start signal.
[0097] The second pin is connected to the output end of the signal amplifying buffer circuit and is used to output the relative delay between the two parallel test branches.
[0098] The third pin is used to access the power supply voltage to provide power to the entire probe structure, and the fourth pin is used for grounding to provide a reference level for the circuit, which helps to stabilize the signal and accurately measure it.
[0099] In this embodiment, the probe structure is implemented in a manner involving parallel test branches, phase detectors, frequency dividers and signal amplification buffer circuits, and the relative delay of the signal can be measured through the parallel test branches and phase comparison. The pins are connected to power and ground to ensure correct operation.
[0100] In the present disclosure, the terms "first", "second", and "third" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance; the term "plurality" refers to two or more, unless otherwise expressly defined. The terms "installed", "connected", "connected", "fixed", etc. should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; "connected" can be a direct connection or an indirect connection through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above terms in the present disclosure can be understood according to the specific circumstances.
[0101] In the description of the present disclosure, it is necessary to understand that the directions or positional relationships indicated by the terms "up", "down", "left", "right", "front", "back", etc. are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or unit referred to must have a specific direction, be constructed and operated in a specific orientation, and therefore, should not be understood as a limitation on the present disclosure.
[0102] In the description of this specification, the description of the terms "one embodiment", "some embodiments", "specific embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.
[0103] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. For those skilled in the art, the present disclosure may have various changes and variations. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure. After considering the specification and practicing the utility model disclosed herein, those skilled in the art will easily think of other embodiments of the present disclosure. The present disclosure is intended to cover any variation, use or adaptive change of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary technical means in the technical field that are not disclosed in the present disclosure. The description and examples are regarded as exemplary only, and the true scope and spirit of the present disclosure are indicated by the attached claims.
Claims
1. A delay test circuit, characterized in that: include: Two test branches connected in parallel, one of the two test branches connected in parallel comprises a first input end and a first output end, the other of the two test branches connected in parallel comprises a second input end and a second output end, the first input end and the second input end are used to receive the same oscillation signal, the first output end is used to output a first oscillation signal, and the second output end is used to output a second oscillation signal; A phase detector, wherein the input end of the phase detector is respectively connected to the first output end and the second output end, and is used to receive the first oscillation signal and the second oscillation signal; the output end of the phase detector is used to output the phase difference between the first oscillation signal and the second oscillation signal, and the phase difference is used to detect the relative delay between the two parallel test branches.
2. The delay test circuit according to claim 1, characterized in that: The test branch includes a first logic gate unit and a second logic gate unit connected in series, and the number of the second logic gate units is an even number.
3. The delay test circuit according to claim 2, characterized in that: The first logic gate unit includes one of a NAND gate and a NOR gate, Among them, one input end of the first logic gate unit is used to input the oscillation start signal, and the other input end of the first logic gate unit is used to be connected to the output end of the corresponding test branch to form a loop.
4. The delay test circuit according to claim 2, characterized in that: The second logic gate unit includes one of an inverter, a NAND gate and a NOR gate. The input end of the inverter is connected to the output end of the adjacent previous first logic gate unit, or is connected to the output end of the adjacent previous inverter; Both input ends of the NAND gate are connected to the output end of the previous adjacent first logic gate unit, or are connected to the output end of the previous adjacent NAND gate; Both input ends of the NOR gate are connected to the output end of the adjacent previous first logic gate unit, or are connected to the output end of the adjacent previous NOR gate.
5. The delay test circuit according to claim 2, characterized in that: The second logic gate unit includes an XOR gate, one input end of the XOR gate is used to receive a power supply voltage, and the other input end of the XOR gate is connected to the output end of the adjacent previous first logic gate unit, or is connected to the output end of the adjacent previous XOR gate.
6. The delay test circuit according to claim 2, characterized in that: The second logic gate unit includes an XNOR gate, one input end of the XNOR gate is used for grounding, and the other input end of the XNOR gate is connected to the output end of the adjacent previous first logic gate unit, or connected to the output end of the adjacent previous XNOR gate.
7. The delay test circuit according to any one of claims 1 to 6, characterized in that: Also includes: A frequency divider, wherein an input end of the frequency divider is connected to an output end of the phase detector, and an output end of the frequency divider is used to output a frequency-divided signal of the phase difference; A signal amplifying buffer circuit, wherein the input end of the signal amplifying buffer circuit is connected to the output end of the frequency divider, and the output end of the signal amplifying buffer circuit outputs the relative delay generated based on the frequency-divided signal.
8. A probe structure, characterized in that: include: The delay test circuit according to any one of claims 1 to 7, wherein the delay test circuit comprises two test branches connected in parallel, one of the two test branches connected in parallel comprises a first input terminal, and the other of the two test branches connected in parallel comprises a second input terminal; The first pin is connected to the first input terminal and the second input terminal respectively, and is used to receive an input oscillation start signal.
9. The probe structure according to claim 8, characterized in that: The delay test circuit further includes a signal amplification buffer circuit, and the probe structure further includes: The second pin is connected to the output end of the amplifying buffer circuit and is used to output the relative delay between the two parallel test branches.
10. The probe structure according to claim 8, characterized in that: Also includes: A third pin is connected to the two parallel test branches and is used to receive an input power supply voltage; The fourth pin is connected to the two parallel test branches and is used for grounding.