Radar signal simulation equipment capable of controlling distance

Abstract

The utility model discloses radar signal simulation equipment capable of controlling distance. The radar signal simulation equipment comprises a signal simulation module, a communication control module and a distance calculation module which are in communication connection in sequence, the signal simulation module comprises an AD chip, an FPGA register and a DA chip, an input port of the AD chip receives a radar emission simulation signal, and an output port of the AD chip is in communication connection with the communication control module and sends a digital signal; a plurality of PCIE (Peripheral Component Interconnect Express) interfaces are arranged in the communication control module and are respectively in communication connection with the signal simulation module and the distance calculation module; the distance calculation module comprises an ARM processor and a DDR memory which are in communication connection with each other, and an input port of the ARM processor receives a radar target simulation distance issued by an external control terminal; the input port of the DDR memory receives and stores the digital signal; the output port of the DDR memory is in communication connection with the input port of the FPGA register through the PCIE interface; the input port of the DA chip is in communication connection with the output port of the FPGA register, and the output port of the DA chip outputs the converted radar analog signals.

Description

Technical Field

[0001] The utility model relates to the technical field of radar signal simulation, in particular to a radar signal simulation device capable of controlling distance. Background Art

[0002] Radar signal simulation equipment is required to be able to complete large data volume calculations in a very short time, which requires a high-speed real-time signal processing platform with strong general performance. Traditional radar signal simulation equipment uses the internal logic resources of FPGA (Field Programmable Gate Array) for data calculations. Due to the limited internal logic resources, the large data volume calculation capability and real-time processing capability cannot be met.

[0003] The specific manifestations are:

[0004] 1. If the FPGA itself completes the distance calculation of the radar analog signal, a large amount of digital calculation is required, which will consume FPGA hardware resources;

[0005] 2. If the distance calculation of the radar simulation signal is completed by the FPGA soft core, the floating-point computing capability is limited, and the internal delay of the FPGA is controlled through the AXI bus, the speed is slow, and close-range target simulation control cannot be achieved. Utility Model Content

[0006] In order to overcome the defects of the prior art, the technical problem to be solved by the utility model is: how to realize close-range, high-speed radar signal simulation control under the premise of saving FPGA hardware resources.

[0007] In order to solve the above technical problems, the utility model provides a radar signal simulation device capable of controlling distance, comprising: a signal simulation module, a communication control module and a distance calculation module which are sequentially connected for communication; wherein:

[0008] The signal simulation module includes: an AD chip, an FPGA register and a DA chip, wherein the input port of the AD chip receives the radar transmission analog signal and performs analog-to-digital conversion, and the output port communicates with the communication control module and sends the converted digital signal;

[0009] The communication control module is provided with a plurality of PCIE interfaces, and the plurality of PCIE interfaces are respectively connected to the signal simulation module and the distance calculation module for communication;

[0010] The distance calculation module includes an ARM processor and a DDR memory that are communicatively connected to each other, wherein the input port of the ARM processor receives the radar target simulation distance issued by the external control terminal; the input port of the DDR memory receives the digital signal sent by the AD chip via the PCIE interface of the communication control module and stores it; the output port of the DDR memory is communicatively connected to the input port of the FPGA register in the signal simulation module via the PCIE interface of the communication control module;

[0011] The input port of the DA chip is communicatively connected to the output port of the FPGA register, and the output port outputs the converted radar simulation signal.

[0012] On the basis of the above technical solution, the present invention can also be improved as follows.

[0013] Preferably, the radar transmission analog signal is an intermediate frequency signal after down-conversion of the original radar signal.

[0014] Preferably, the ARM processor converts the analog distance into a delay time, and then converts the delay time into a read-write address difference according to the read-write clock frequency of the DDR memory, and then writes the address difference into the DDR memory, and then sends it to the FPGA register.

[0015] Preferably, the DA chip reads the address difference in the FPGA register in real time, performs digital-to-analog conversion, and outputs a delayed radar analog signal.

[0016] Preferably, the signal simulation module is used to convert an analog signal into a digital signal, and the intermediate frequency signal is converted from an analog signal to a digital signal via the AD chip.

[0017] Preferably, the communication control module is used for communication connection and control, and realizes signal transmission between the signal simulation module and the distance calculation module through the PCIE interface.

[0018] Preferably, the distance calculation module is used to calculate the distance of the radar simulation signal, and the distance of the radar simulation signal is achieved by storing and delaying the reading of the received radar transmission simulation signal.

[0019] Compared with the prior art, the utility model can produce the following beneficial technical effects:

[0020] 1. In the present invention, the ARM processor realizes the calculation of distance simulation, and then sends it to the FPGA register through the PCIE interface; the high-speed data transmission is completed through the PCIE interface, the reading and writing speed is fast, and the hardware resources are saved more; the FPGA generates an interrupt through the PCIE interface, and the ARM processor can respond to the FPGA demand status more timely by processing the interrupt event; thereby, the short-range and high-speed radar signal simulation control is realized under the premise of saving FPGA hardware resources;

[0021] 2. In the present invention, the control terminal sends distance control instructions to the ARM processor; the communication method between the control terminal and the radar simulation device is flexible, supporting multiple communication methods such as Ethernet and serial port. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0023] Figure 1 The utility model is a schematic diagram of the structure of the radar signal simulation device capable of controlling distance.

[0024] In the accompanying drawings, the component names represented by the reference numerals are listed as follows:

[0025] 100: signal simulation module, 200: communication control module, 300: distance calculation module;

[0026] 101: AD chip, 102: FPGA register, 103: DA chip;

[0027] 301: ARM processor, 302: DDR memory. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solution and advantages of the embodiment of the utility model clearer, the technical solution in the embodiment of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiment of the utility model. Obviously, the described embodiment is a part of the embodiment of the utility model, not all of the embodiments. Based on the embodiment of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0029] Please refer to Figure 1As shown, it is a schematic diagram of the structure of the distance-controllable radar signal simulation device of the present invention; the radar signal simulation device of the present invention includes: a signal simulation module 100, a communication control module 200 and a distance calculation module 300 which are communicatively connected in sequence.

[0030] The signal simulation module 100 is used to convert an analog signal into a digital signal; specifically, the signal simulation module 100 includes: an AD chip 101, an FPGA register 102 and a DA chip 103, wherein the input port of the AD chip 101 receives the intermediate frequency signal after the original radar signal is down-converted, and the output port is communicatively connected with the communication control module 200; that is, the intermediate frequency signal is converted from an analog signal to a digital signal by the AD chip 101, and then sent to the communication control module 200.

[0031] The communication control module 200 is used for communication connection and control; specifically, the communication control module 200 is provided with multiple PCIE interfaces, and the multiple PCIE interfaces are respectively communicated with the signal simulation module 100 and the distance calculation module 300, so as to realize signal transmission between the signal simulation module 100 and the distance calculation module 300; thus, the signal simulation module 100 receives the radar simulation signal, converts it into a digital signal, and then sends it to the distance calculation module 300 through the PCIE interface in the communication control module 200.

[0032] The distance calculation module 300 is used to calculate the distance of the radar simulation signal; specifically, the distance calculation module 300 includes an ARM processor 301 and a DDR memory 302 that are communicatively connected to each other, wherein:

[0033] The input port of the ARM processor 301 receives the simulated distance of the radar target sent by the external control terminal, and converts the simulated distance into the address difference after delay; specifically, according to the standard speed of light, 1us is 150m relative to the detection distance of the radar, that is, 6.67ns is approximately equal to 1m; therefore, the ARM processor 301 converts the simulated distance into a delay time, and then converts the delay time into a read-write address difference according to the read-write clock frequency of the DDR memory 302, and then writes the address difference into the DDR memory 302; it should be noted here that the module components used in the present utility model are all commercially available products, and the functions implemented are also the functions of the product itself; what the present utility model requests to protect is the combination of these products, that is, the hardware connection relationship.

[0034] The input port of the DDR memory 302 receives the digital signal sent by the AD chip 101 via the PCIE interface of the communication control module 200 and stores it; the output port of the DDR memory 302 sends the address difference to the input port of the FPGA register 102 in the signal simulation module 100 via the PCIE interface of the communication control module 200;

[0035] The input port of the DA chip 103 is communicatively connected with the output port of the FPGA register 102. The DA chip 103 reads the address difference in the FPGA register 102 in real time, performs digital-to-analog conversion, and finally outputs a delayed radar analog signal.

[0036] In summary, in the present invention, the state setting of the signal simulation module is completed by reading and writing registers through PCIE, and multiple address differences can be quickly written to the continuous addresses of the FPGA through DMA (Direct Memory Access), meeting the application scenarios that require rapid control of distance changes; thus, the distance of the radar simulation signal is realized by storing and delaying the reading of the received radar transmission signal.

[0037] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the utility model, rather than to limit it. Although the utility model has been described in detail with reference to the aforementioned embodiments, ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the utility model.

Claims

1. A radar signal simulation device that can control distance, It is characterized in that It includes: a signal simulation module, a communication control module and a distance calculation module which are sequentially connected for communication; wherein, The signal simulation module includes: an AD chip, an FPGA register and a DA chip, wherein the input port of the AD chip receives the radar transmission analog signal and performs analog-to-digital conversion, and the output port communicates with the communication control module and sends the converted digital signal; The communication control module is provided with a plurality of PCIE interfaces, and the plurality of PCIE interfaces are respectively connected to the signal simulation module and the distance calculation module for communication; The distance calculation module includes an ARM processor and a DDR memory that are communicatively connected to each other, wherein the input port of the ARM processor receives the radar target simulation distance issued by the external control terminal; the input port of the DDR memory receives the digital signal sent by the AD chip via the PCIE interface of the communication control module and stores it; the output port of the DDR memory is communicatively connected to the input port of the FPGA register in the signal simulation module via the PCIE interface of the communication control module; The input port of the DA chip is communicatively connected to the output port of the FPGA register, and the output port outputs the converted radar simulation signal.

2. The distance-controllable radar signal simulation device according to claim 1, It is characterized in that The radar transmission analog signal is an intermediate frequency signal after the original radar signal is down-converted.

3. The distance-controllable radar signal simulation device according to claim 2, It is characterized in that The ARM processor converts the simulated distance into a delay time, and then converts the delay time into a read-write address difference according to the read-write clock frequency of the DDR memory, and then writes the address difference into the DDR memory, and then sends it to the FPGA register.

4. The distance-controllable radar signal simulation device according to claim 3, It is characterized in that The DA chip reads the address difference in the FPGA register in real time, performs digital-to-analog conversion, and outputs a delayed radar analog signal.

5. The distance-controllable radar signal simulation device according to claim 2, It is characterized in that The signal simulation module is used to convert an analog signal into a digital signal, and the intermediate frequency signal is converted from an analog signal to a digital signal via the AD chip.

6. The distance-controllable radar signal simulation device according to any one of claims 1 to 5, It is characterized in that The communication control module is used for communication connection and control, and realizes signal transmission between the signal simulation module and the distance calculation module through the PCIE interface.

7. The distance-controllable radar signal simulation device according to any one of claims 1 to 5, It is characterized in that The distance calculation module is used to calculate the distance of the radar simulation signal, and the distance of the radar simulation signal is realized by storing and delaying the reading of the received radar transmission simulation signal.

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