Solid state disk debugging board

Abstract

The utility model relates to the technical field of solid state disks, in particular to a solid state disk debugging board which comprises a main board and an auxiliary board, the main board comprises a controller and a cache chip, and a plurality of nonvolatile memories of different specifications are attached to the auxiliary board. The main board is connected with the auxiliary board through one or more high-speed connectors; the controller comprises a plurality of channels, and the plurality of channels respectively establish connection topology with the plurality of nonvolatile memories through high-speed connectors. According to the utility model, a separated structure of the main board and the auxiliary board is adopted, the main board is only used for placing parts such as the controller and the cache chip, the auxiliary board carries non-volatile memories of different manufacturers, and NAND Flash of different manufacturers and different models can be debugged by replacing the auxiliary board.

Description

Technical Field

[0001] The utility model belongs to the technical field of solid state hard disks, and in particular relates to a solid state hard disk debugging board. Background Art

[0002] Solid State Drive (SSD) is a hard disk made of solid-state electronic storage chip array. Flash-based SSDs are the main category of SSDs. Their internal structure is very simple. The main body of the SSD is actually a PCB board, and the most basic accessories on this PCB board are the control chip, cache chip (some low-end hard disks do not have cache chips) and cache chips for storing data. The more common SSDs on the market include LSISandForce, Indilinx, JMicron, Marvell, Phison, Sandisk, Goldendisk, Samsung and Intel and other main control chips. The main control chip is the brain of the SSD. Its function is to reasonably allocate the load of data on each cache chip, and to undertake the entire data transfer, connecting the cache chip and the external SATA interface. The capabilities of different main controls vary greatly. There will be very large differences in data processing capabilities, algorithms, and read and write control of cache chips, which will directly lead to a performance gap of up to several times between SSD products. Next to the main control chip are cache particles. SSDs, like traditional hard drives, require high-speed cache chips to assist the main control chip in data processing. It should be noted here that some cheap SSD solutions omit this cache chip in order to save costs, which will have a certain impact on the performance during use, especially the read and write performance and service life of small files. In addition to the main control chip and cache chip, most of the rest of the PCB board is NAND Flash memory chips. NAND Flash flash memory chips are divided into four specifications: SLC (Single-Level Cell), MLC (Multi-Level Cell), TLC (Trinary-Level Cell), and QLC (Quad-Level Cell). There is also an eMLC (Enterprise Multi-Level Cell), which is an "enhanced" version of MLC NAND flash memory, which to a certain extent makes up for the performance and durability gap between SLC and MLC.

[0003] Affected by NAND Flash production capacity, performance, and price, SSDs need to be compatible with as many NANDs from different manufacturers as possible without changing other hardware. This requires the adaptation of NAND Flashes from multiple manufacturers during the development phase. Each type of NAND needs to be tested on a board, which results in the large-scale use of controllers, SDRAM, etc., increasing R&D costs. A method is needed to replace only NAND Flash and reuse other devices, which can reduce R&D costs and save time. Utility Model Content

[0004] In view of the above-mentioned deficiencies in the prior art, the utility model provides a solid state hard disk debugging board to solve the above-mentioned technical problems.

[0005] The utility model provides a solid state hard disk debugging board, comprising:

[0006] A main board and a sub-board, wherein the main board includes a controller and a cache chip, and the sub-board is provided with a plurality of non-volatile memories of different specifications;

[0007] The main board is connected to the sub-board via one or more high-speed connectors;

[0008] The controller includes a plurality of channels, and the plurality of channels respectively establish a connection topology with a plurality of non-volatile memories through a high-speed connector.

[0009] In an optional embodiment, the controller includes a first channel group and a second channel group, the first channel group includes 8 channels, and the second channel group includes 8 channels; the main board includes a first high-speed connector and a second high-speed connector; the 8 channels of the first channel group are connected to the first high-speed connector, and the 8 channels of the second channel group are connected to the second high-speed connector; the first high-speed connector and the second high-speed connector are both connected to the sub-board.

[0010] In an optional embodiment, the sub-board includes a first storage group and a second storage group, the first storage group includes 8 non-volatile memories, and the second storage group includes 8 non-volatile memories; the 8 channels in the first channel group are correspondingly connected to the 8 non-volatile memories in the first storage group through the first high-speed connector; the 8 channels in the second channel group are correspondingly connected to the 8 non-volatile memories in the first storage group through the second high-speed connector.

[0011] In an optional embodiment, the channel includes 8 chip select signal pins, and the 8 chip select signal pins are divided into a first pin group and a second pin group. The first pin group is connected to the first port of the first non-volatile memory, and the second pin group is connected to the first port of the second non-volatile memory. The first non-volatile memory and the second non-volatile memory are respectively attached to the TOP layer and the Bottom layer of the backplane.

[0012] In an optional implementation, the non-volatile memory includes two interfaces, and the two interfaces are respectively connected to chip selection signal pins of different channels.

[0013] In an optional embodiment, the main board includes a high-speed connector, and the controller includes 8 channels; the 8 channels adopt a topology structure in which two channels connect 4 non-volatile memories, and the 16 non-volatile memories on the sub-board are connected through the high-speed connector.

[0014] In an optional embodiment, the first channel includes 8 chip select signal pins, of which 4 chip select signal pins belong to a first pin group, and the other 4 chip select signal pins belong to a second pin group; the first pin group is respectively connected to the first port of the first non-volatile memory and the first port of the second non-volatile memory, and the second pin group is respectively connected to the first port of the third non-volatile memory and the first port of the fourth non-volatile memory; the first non-volatile memory and the second non-volatile memory are respectively attached to the TOP layer and the Bottom layer of the backplane; the third non-volatile memory and the fourth non-volatile memory are respectively attached to the TOP layer and the Bottom layer of the backplane.

[0015] In an optional embodiment, the second port of the first non-volatile memory and the second port of the second non-volatile memory are connected to the first pin group of the second channel, and the second port of the third non-volatile memory and the second port of the fourth non-volatile memory are connected to the second pin group of the second channel; the first pin group of the second channel includes 4 chip select signal pins, and the second pin group of the second channel includes 4 chip select signal pins.

[0016] In an optional embodiment, the mainboard includes a backup capacitor, a U.2 connector, a power chip and a plurality of temperature sensors.

[0017] In an optional implementation, the high-speed connector supports 8 NAND Channel signal channels; the pins of the high-speed connector include: 8 groups of channel signal pins, 4 power pins and 2 pull-up and pull-down pins.

[0018] The beneficial effect of the utility model is that the solid state hard disk debugging board provided by the utility model adopts a separation structure of a main board and a sub-board, the main board only places components such as a controller and a cache chip, and the sub-board carries non-volatile memories of different manufacturers. By replacing the sub-board, NAND Flash of different manufacturers and different models can be debugged. It can save the development cost of debugging NAND Flash of different manufacturers and is convenient and fast.

[0019] In addition, the utility model has a reliable design principle, a simple structure and a very broad application prospect. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the utility model or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1 This is a first connection topology diagram of the mainboard of the solid state hard disk debugging board of one embodiment of the utility model.

[0022] Figure 2 This is a first connection topology diagram of the non-volatile memory of the solid state hard disk debugging board of an embodiment of the utility model.

[0023] Figure 3 This is a first connection topology diagram of a sub-board of a solid state hard disk debugging board according to an embodiment of the utility model.

[0024] Figure 4 This is a second connection topology diagram of the mainboard of the solid state hard disk debugging board of an embodiment of the utility model.

[0025] Figure 5 This is a second connection topology diagram of the non-volatile memory of the solid state hard disk debugging board of an embodiment of the utility model.

[0026] Figure 6 This is a second connection topology diagram of the sub-board of the solid state hard disk debugging board of an embodiment of the utility model.

[0027] Figure 7 This is a schematic diagram of the first TOP surface device distribution of the mainboard of the solid state hard disk debugging board according to an embodiment of the utility model.

[0028] Figure 8 This is a schematic diagram of the second TOP surface device distribution of the mainboard of the solid state hard disk debugging board according to an embodiment of the utility model.

[0029] Fig. 9The present invention is a schematic diagram of the distribution of components on the bottom surface of a mainboard of a solid state hard disk debugging board according to an embodiment of the present invention.

[0030] Fig.10 This is a schematic diagram of the first TOP surface device distribution of a sub-board of a solid-state hard disk debugging board according to an embodiment of the utility model.

[0031] Fig.11 This is a schematic diagram of the second TOP surface device distribution of the sub-board of the solid-state hard disk debugging board according to an embodiment of the utility model.

[0032] Fig.12 The present invention is a schematic diagram of the distribution of components on the bottom surface of a sub-board of a solid state hard disk debugging board according to an embodiment of the present invention. DETAILED DESCRIPTION

[0033] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0035] The key terms appearing in the present invention are explained below.

[0036] SSD: Solid State Drive, abbreviated as SSD, is a hard disk made of a solid-state electronic storage chip array.

[0037] NAND Flash: A non-volatile memory based on NAND technology. It is a type of Flash memory that uses a nonlinear macrocell mode internally, providing a cheap and effective solution for the implementation of solid-state large-capacity memory. NandFlash memory has the advantages of large capacity and fast rewrite speed, and is suitable for storing large amounts of data.

[0038] Channel: A channel is a set of physical pins in NAND Flash that is responsible for receiving and transmitting data and commands.

[0039] Target: NAND Flash usually contains one or more Targets. Target has independent chip select units and can be addressed individually. It usually contains one or more LUNs.

[0040] CE: A Target contains one or more LUNs. One or more LUNs on a Target share a set of data signals. Each Target is controlled by a CE pin (chip select), which means that several LUNs on a Target share one CE signal.

[0041] MUX chip: A multiplexer for high-speed memory signals, used to enhance the signal quality of NAND Flash high-speed signal lines.

[0042] SDRAM: Synchronous Dynamic Random-access Memory, referred to as SDRAM, is a dynamic random access memory (DRAM) with a synchronous interface. It waits for a clock signal before responding to control inputs, so that it can be synchronized with the computer's system bus. The clock is used to drive a finite state machine to pipeline incoming instructions. This allows SDRAM to have a more complex operating mode.

[0043] I2C: Inter-Integrated Circuit, I2C bus is a two-wire serial communication bus developed by PHILIPS, using a multi-master-slave architecture to connect microcontrollers and their peripheral low-speed devices. It is a bus standard widely used in the field of microelectronic communication control. It is a special form of synchronous communication with the advantages of fewer interface lines, simple control method, small device package, and higher communication rate.

[0044] Specifically, the solid state drive debugging board includes:

[0045] A main board and a sub-board, wherein the main board includes a controller and a cache chip (SDRAM), and the sub-board is provided with a plurality of non-volatile memories (NAND Flash) of different specifications; the main board is connected to the sub-board via one or more high-speed connectors; the controller includes a plurality of channels, and the plurality of channels respectively establish a connection topology with the plurality of non-volatile memories via high-speed connectors.

[0046] By adding a sub-board, NAND Flash is separated from other devices. NAND Flash is made into a separate sub-board, and the controller and other devices such as SDRAM are made on a main board, and the two are connected through a high-speed connector. During the SSD development stage, when it is necessary to adapt to NAND Flash from different manufacturers, by replacing the NAND Flash sub-board, it is possible to debug and develop NAND Flash from different manufacturers, which can reuse the main board and quickly switch NAND Flash from different manufacturers.

[0047] Compared with conventional SSDs, the main board lacks NAND Flash particles, but the rest of the components are basically the same; the sub-board only has NAND Flash particles, which can be attached to NAND particles from different manufacturers. Both the main board and the sub-board have a high-speed connector, and the sub-board can be connected to the main board through the connector. The two are combined into one piece and used as a whole SSD. The high-speed connector is used for high-speed signal connection between the main board and the NAND Flash sub-board, and can realize data communication between the main board controller and the sub-board NAND Flash. By replacing the NAND sub-board, you can quickly switch NAND Flash from different manufacturers, which is convenient for NAND compatible debugging and development.

[0048] The number of NAND channels of the controller is generally 8 or 16. Depending on the number of channels, the connection topology between the channels and the NAND Flash is also different.

[0049] When the controller has 16 NAND channels, the topology is as follows:

[0050] The controller includes a first channel group and a second channel group, the first channel group includes 8 channels, and the second channel group includes 8 channels; the main board includes a first high-speed connector and a second high-speed connector; the 8 channels of the first channel group are connected to the first high-speed connector, and the 8 channels of the second channel group are connected to the second high-speed connector; the first high-speed connector and the second high-speed connector are both connected to the sub-board.

[0051] Specifically, Figure 1As shown in the figure, the controller itself has 16 NAND channels, namely Channel 0~15. Each channel is independent and will not affect each other. The 16 channels are divided into two parts, Channel 0~7 is the first part, and Channel 8~15 is the second part. There are two high-speed connectors on the main board and the sub-board respectively. Channel 0~7 communicates with the NAND Flash of the sub-board through high-speed connector 1, and Channel 8~15 communicates with the NAND Flash of the sub-board through high-speed connector 2.

[0052] Each channel of the controller has 8 CEs, all of which are connected to the NAND on the sub-board through a high-speed connector to select different targets of the NAND Flash particles.

[0053] In each channel, different targets of NAND Flash particles share IO0~7, WE, CLE, ALE, WP, DQS_P, DQS_N, RE_P, and RE_N signals, and different targets of NAND Flash particles are selected through CE0~7 signals in the channel.

[0054] The sub-board includes a first storage group and a second storage group, the first storage group includes 8 non-volatile memories, and the second storage group includes 8 non-volatile memories; the 8 channels in the first channel group are correspondingly connected to the 8 non-volatile memories in the first storage group through the first high-speed connector; the 8 channels in the second channel group are correspondingly connected to the 8 non-volatile memories in the first storage group through the second high-speed connector. Specifically, there are 16 NAND Flash particles on the sub-board, and CH0~15 are connected to the 16 NAND particles through two high-speed connectors. Each high-speed connector corresponds to 8 channels and connects 8 NAND Flash.

[0055] Each NAND Flash particle has two sets of IO interfaces, which are independent of each other and can be connected to the same channel or to two different channels. Figure 2 As shown in the figure, the connection topology used in this design is that two groups of IO of a NAND Flash are connected to different channels. Channel N is connected to one group of IO of NAND Flash particles U1 and U2 respectively, and Channel N+1 is connected to another group of IO of U1 and U2. U1 and U2 are pasted on the TOP and Bottom layers of the PCB respectively.

[0056] like Figure 3As shown, the channel includes 8 chip select signal pins, which are divided into a first pin group and a second pin group. The first pin group is connected to the first port of the first non-volatile memory, and the second pin group is connected to the first port of the second non-volatile memory. The first non-volatile memory and the second non-volatile memory are respectively attached to the TOP layer and the Bottom layer of the backplane. The non-volatile memory includes two interfaces, and the two interfaces are respectively connected to the chip select signal pins of different channels.

[0057] When the controller has 8 NAND channels, the topology is as follows:

[0058] like Figure 4 As shown in the figure, the main board and the sub-board are connected through a high-speed connector. The controller includes 8 channels; the 8 channels use a topology structure in which two channels connect 4 non-volatile memories, and connect the 16 non-volatile memories on the sub-board through a high-speed connector. That is, the controller has 8 channels Channel0~7, which are connected to the NAND particles on the sub-board through a high-speed connector.

[0059] Each channel of the controller has 8 CEs, which are connected to the NAND of the sub-board through a high-speed connector to select different targets of the NAND Flash particles. In each channel, different targets of the NAND Flash particles share IO0~7, WE, CLE, ALE, WP, DQS_P, DQS_N, RE_P, RE_N signals, and different targets of the NAND Flash particles are selected through the CE0~7 signals in the channel.

[0060] There are 16 NAND Flash chips on the sub-board, and CH0~7 are connected to the 16 NAND chips through high-speed connectors.

[0061] Each NAND Flash particle has two groups of IO interfaces, which are independent of each other and can be connected to the same channel or to two different channels. In this embodiment, the two groups of IO of a NAND Flash are connected to different channels. The topology of 2Channel-4NAND particles is adopted on the NAND Flash sub-board. The topology of 2Channel-4NAND particles includes: the first channel includes 8 chip select signal pins, of which 4 chip select signal pins belong to the first pin group, and the other 4 chip select signal pins belong to the second pin group; the first pin group is respectively connected to the first port of the first non-volatile memory and the first port of the second non-volatile memory, and the second pin group is respectively connected to the first port of the third non-volatile memory and the first port of the fourth non-volatile memory; the first non-volatile memory and the second non-volatile memory are respectively attached to the TOP layer and the Bottom layer of the backplane; the third non-volatile memory and the fourth non-volatile memory are respectively attached to the TOP layer and the Bottom layer of the backplane. The second port of the first non-volatile memory and the second port of the second non-volatile memory are connected to the first pin group of the second channel, and the second port of the third non-volatile memory and the second port of the fourth non-volatile memory are connected to the second pin group of the second channel; the first pin group of the second channel includes 4 chip select signal pins, and the second pin group of the second channel includes 4 chip select signal pins.

[0062] like Figure 5 As shown in the figure, the Nth channel (Channel N) is connected to a group of IOs of NAND Flash particles U1, U2, U3, and U4, and the N+1th channel (Channel N+1) is connected to another group of IOs of U1, U2, U3, and U4. U1 and U3, U2 and U4 are respectively connected in a pair-to-patch manner.

[0063] The connection topology between the NAND Flash chip on the sub-board and the high-speed connector is as follows Figure 6 shown.

[0064] Component distribution on the mainboard:

[0065] like Figure 7 As shown, there are a total of 5 SDRAM particles on the TOP surface of the motherboard, a controller with 16 channels, a U.2 connector, two high-speed connectors, backup capacitors, temperature sensor U2 and temperature sensor U3.

[0066] like Figure 8As shown, there are a total of 5 SDRAM particles, an 8-channel controller, a U.2 connector, two high-speed connectors, a backup capacitor, a temperature sensor U2 and a temperature sensor U3 on the TOP surface of the motherboard. The two temperature sensors U2~U3 monitor the temperature of the SDRAM and the controller respectively. Each device has its own normal working range. When the temperature approaches or exceeds the device temperature threshold, the SSD disk will take corresponding temperature control measures to slow down the business. If the temperature continues to rise, the business will be stopped.

[0067] like Fig. 9 As shown in the figure, there are 4 SDRAM chips, power chip and backup capacitors on the bottom side of the motherboard. In addition to supplying power to the devices on the motherboard, the power chip also supplies power to the devices on the NAND Flash sub-board through a high-speed connector.

[0068] Sub-board part:

[0069] The sub-board mainly has high-speed connectors, NAND Flash particles and MUX chips. The signals of NAND Flash particles are connected to the high-speed connector through the MUX chip to communicate with the mainboard controller. Since the wiring between the sub-board NAND Flash particles and the mainboard controller is too long and passes through the connector, the signal attenuation is relatively large, so a MUX chip is added in the middle to enhance the signal quality between the controller and the NAND Flash particles.

[0070] A maximum of 16 NAND Flash particles can be placed on the sub-board, and each NAND Flash particle uses 1 MUX chip. The sub-board can be filled with 16 NAND Flash particles, or only a few of them, to configure the total capacity of the NAND sub-board, and combine the capacity points of the NAND sub-board to 2T / 4T / 8T / 16T.

[0071] like Fig.10 As shown in the figure, corresponding to the 16-channel mainboard controller, the TOP surface of the sub-board includes 8 NAND Flash particles, each NAND Flash particle uses a MUX chip, and also includes two high-speed connectors and a temperature sensor U1. The temperature sensor U1 is connected to the mainboard controller through the I2C interface and the high-speed connector. The controller can monitor the working temperature of the NAND Flash particles on the sub-board in real time. When the NAND Flash working temperature exceeds the threshold of the SSD disk, the temperature control strategy is implemented to slow down the business. If the temperature continues to rise, the business will be stopped.

[0072] like Fig.11As shown, corresponding to the 8-channel mainboard controller, the TOP surface of the sub-board includes 8 NAND Flash particles, each NAND Flash particle uses 1 MUX chip, and also includes a high-speed connector and temperature sensor U1.

[0073] like Fig.12 As shown, the Bottom side of the sub-board includes 8 NAND Flash particles, each NAND Flash particle uses 1 MUX chip, and also includes a temperature sensor U1.

[0074] Size of the solid-state drive: Considering the size limitations of the slots on the server and the fact that the maximum thickness of a 2.5-inch SSD disk is usually 15mm, the mainboard portion of the SSD disk is designed to be 7mm thick, and the sub-board portion is designed to be 7mm thick. In this way, when the sub-board is buckled onto the mainboard, the overall thickness of the expanded SSD disk will not exceed 15mm.

[0075] The structure of the high-speed connector includes: the high-speed connector supports at least 8 NAND Channel signal channels, as well as the working power supply of the NAND Flash and the pins of other functions. Select 2 of the pins and connect them to the 2 GPIO pins of the controller. On the sub-board, the two pins of the connector are pulled up and down differently to achieve four combinations of 00, 01, 10, and 11, which correspond to different capacity points of the sub-board. 00 represents the 2T capacity of the sub-board, and 01, 10, and 11 correspond to the 4T / 8T / 16T capacity of the sub-board respectively. At power-on startup, the controller identifies the different values ​​of the two GPIO pins 00~11 and switches the corresponding firmware to correspond to the NAND Flash sub-boards with different capacity points.

[0076] The main pin classifications of high-speed connectors are as follows:

[0077] ①8 groups of Channel pins, each group of Channel includes IO0~7, ALE, CLE, WP, RE_P, RE_N, DQS_P, DQS_N, CE0~3 (or CE4~7);

[0078] ②4 power pins, NAND Flash power supply P1V2, P2V5, P12V_VPP, and temperature sensor power supply P3V3;

[0079] ③NAND Flash sub-board capacity identification pin, by pulling up and down 2 pins corresponding to different NAND Flash sub-board capacity points, it is easy for the main board to identify.

[0080] Although the utility model is described in detail by referring to the accompanying drawings and in combination with the preferred embodiments, the utility model is not limited thereto. Without departing from the spirit and essence of the utility model, a person skilled in the art may make various equivalent modifications or substitutions to the embodiments of the utility model, and these modifications or substitutions shall be within the scope of the utility model. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the utility model, and they shall be within the scope of protection of the utility model.

Claims

1. A solid state hard disk debugging board, characterized in that: include: A main board and a sub-board, wherein the main board includes a controller and a cache chip, and the sub-board is provided with a plurality of non-volatile memories of different specifications; The main board is connected to the sub-board via one or more high-speed connectors; The controller includes a plurality of channels, and the plurality of channels respectively establish a connection topology with a plurality of non-volatile memories through a high-speed connector.

2. The solid state hard disk debugging board according to claim 1, characterized in that: The controller includes a first channel group and a second channel group, the first channel group includes 8 channels, and the second channel group includes 8 channels; the main board includes a first high-speed connector and a second high-speed connector; the 8 channels of the first channel group are connected to the first high-speed connector, and the 8 channels of the second channel group are connected to the second high-speed connector; the first high-speed connector and the second high-speed connector are both connected to the sub-board.

3. The solid state hard disk debugging board according to claim 2, characterized in that: The sub-board includes a first storage group and a second storage group, the first storage group includes 8 non-volatile memories, and the second storage group includes 8 non-volatile memories; The 8 channels in the first channel group are correspondingly connected to the 8 non-volatile memories in the first storage group through the first high-speed connector; the 8 channels in the second channel group are correspondingly connected to the 8 non-volatile memories in the first storage group through the second high-speed connector.

4. The solid state hard disk debugging board according to claim 3, characterized in that: The channel includes 8 chip select signal pins, and the 8 chip select signal pins are divided into a first pin group and a second pin group. The first pin group is connected to the first port of the first non-volatile memory, and the second pin group is connected to the first port of the second non-volatile memory. The first non-volatile memory and the second non-volatile memory are respectively attached to the TOP layer and the Bottom layer of the backplane.

5. The solid state hard disk debugging board according to claim 4, characterized in that: The non-volatile memory comprises two interfaces, and the two interfaces are respectively connected to the chip selection signal pins of different channels.

6. The solid state hard disk debugging board according to claim 1, characterized in that: The main board includes a high-speed connector, and the controller includes 8 channels; the 8 channels adopt a topological structure in which two channels connect 4 non-volatile memories, and the 16 non-volatile memories on the sub-board are connected through the high-speed connector.

7. The solid state hard disk debugging board according to claim 6, characterized in that: The first channel includes 8 chip selection signal pins, of which 4 chip selection signal pins belong to the first pin group, and the other 4 chip selection signal pins belong to the second pin group; the first pin group is respectively connected to the first port of the first non-volatile memory and the first port of the second non-volatile memory, and the second pin group is respectively connected to the first port of the third non-volatile memory and the first port of the fourth non-volatile memory; The first non-volatile memory and the second non-volatile memory are respectively attached to the TOP layer and the Bottom layer of the backplane; the third non-volatile memory and the fourth non-volatile memory are respectively attached to the TOP layer and the Bottom layer of the backplane.

8. The solid state hard disk debugging board according to claim 7, characterized in that: The second port of the first non-volatile memory and the second port of the second non-volatile memory are connected to the first pin group of the second channel, and the second port of the third non-volatile memory and the second port of the fourth non-volatile memory are connected to the second pin group of the second channel; the first pin group of the second channel includes 4 chip select signal pins, and the second pin group of the second channel includes 4 chip select signal pins.

9. The solid state hard disk debugging board according to claim 1, characterized in that: The mainboard includes a backup capacitor, a U.2 connector, a power chip and a plurality of temperature sensors.

10. The solid state hard disk debugging board according to claim 1, characterized in that: The high-speed connector supports 8 NANDChannel signal channels; the pins of the high-speed connector include: 8 groups of channel signal pins, 4 power pins and 2 pull-up and pull-down pins.

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