Novel integrator amplitude limiting circuit
By designing a new integrator limiting circuit, the transistor connection of the first and second stage comparison circuits is achieved without functioning until the output reaches the limiting value, and the gain is smaller after the output exceeds the limiting value. The gain problem of traditional limiting circuits in the two-stage integrator structure ensures normal operation and loop stability.
Patent Information
- Application Number
- CN202420490626.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-13
- Publication Date
- 2024-12-13
- Estimated Expiration
- 2034-03-13
AI Technical Summary
In the two-stage integrator structure, the loop gain is large, resulting in the output top-cut waveform oscillation, and the traditional limiting circuit has a gain compromise, which affects normal operation, and cannot effectively avoid the limiting circuit from working in advance or Issues that affect the loop.
Design a new integrator limiting circuit including first-stage and second-stage comparison circuits, through the specific connection and configuration of transistors, to achieve no effect until the output reaches the limiting value, and after the output exceeds the limiting value The gain is small, and the output voltage is limited by using the negative feedback mechanism to avoid gain problems in traditional circuits.
It realizes that the limiting circuit does not work before the output reaches the limiting value, and the gain is small after the output exceeds the limiting value, effectively avoiding the problem of the limiting circuit acting in advance or affecting the loop, ensuring normal operation. and loop stability.
Smart Images
Figure CN222169777U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of integrator limiting circuits, and in particular relates to a novel integrator limiting circuit. Background Art
[0002] For class D chips with a two-stage integrator structure, due to the large loop gain, if the second-stage integrator output does not add a limiting circuit, the output clipped waveform will oscillate. The traditional integrator limiting circuit has a compromise. If the gain is too small, the limiting circuit will take effect prematurely and affect normal operation. If the gain is too large, it will affect the loop.
[0003] Therefore, further improvements are made to the above problems. Utility Model Content
[0004] The main purpose of the utility model is to provide a novel integrator limiting circuit, which can not only realize that the limiting circuit does not work before the integrator output reaches the limiting value, but also realize that the gain of the integrator limiting circuit is small after the integrator output exceeds the limiting value.
[0005] In order to achieve the above object, the utility model provides a novel integrator limiting circuit, including a first-stage comparison circuit and a second-stage comparison circuit, the first-stage comparison circuit and the second-stage comparison circuit are electrically connected, wherein:
[0006] The first stage comparison circuit includes transistors P2, P7, P8, P9, N3-N8, the source of transistor P2 is connected to VDD and the drain of transistor P2 is electrically connected to the source of transistor P7, the source of transistor P8 and the source of transistor P9 respectively, the gate of transistor P7 is connected to the reference voltage Vlim, the gate of transistor P8 is connected to the output terminal OUT+ and the gate of transistor P9 is connected to the output terminal OUT-;
[0007] The sources of transistors N3-N8 are all connected to GND, the drain of transistor N3 and the drain of transistor N4 are all electrically connected to the drain of transistor P7, the drain of transistor N5 and the drain of transistor N6 are all electrically connected to the drain of transistor P8, and the drain of transistor N7 and the drain of transistor N8 are all electrically connected to the drain of transistor P9;
[0008] The second stage comparison circuit includes transistors P3-P6, N9-N12, the source of transistor P3, the source of transistor P4, the source of transistor P5 and the source of transistor P6 are all connected to VDD, the gate of transistor P3 is electrically connected to the gate of transistor P4 and the gate of transistor P5 is electrically connected to the gate of transistor P6, the drain of transistor P4 is connected to the input terminal IN- and the drain of transistor P6 is connected to the input terminal IN+;
[0009] The drain of the transistor N9 is electrically connected to the drain of the transistor P3 , the drain of the transistor N10 is electrically connected to the drain of the transistor P4 , the drain of the transistor N11 is electrically connected to the drain of the transistor P5 , and the drain of the transistor N12 is electrically connected to the drain of the transistor P6 .
[0010] As a further preferred technical solution of the above technical solution, the gate and drain of the transistor P3 are connected, and the gate and drain of the transistor P5 are connected.
[0011] As a further preferred technical solution of the above technical solution, the gate and drain of transistor N4 are connected, the gate and drain of transistor N6 are connected, and the gate and drain of transistor N8 are connected.
[0012] As a further preferred technical solution of the above technical solution, the first-stage comparison circuit also includes a transistor P1, the source of the transistor P1 is connected to VDD and the gate of the transistor P1 is connected to the gate of the transistor P2, and the gate and drain of the transistor P1 are connected (for providing bias current).
[0013] As a further preferred technical solution of the above technical solution, the first-stage comparison circuit also includes a transistor N1 and a transistor N2, the source of the transistor N1 and the source of the transistor N2 are both connected to GND, the drain of the transistor N1 is connected to the bias current terminal Bias and the drain of the transistor N2 is connected to the drain of the transistor P1, and the gate of the transistor N1 and the gate of the transistor N2 are electrically connected (for providing a bias current).
[0014] As a further preferred technical solution of the above technical solution, the gate of the transistor N2 is electrically connected to the gate of the transistor N3, the gate of the transistor N5 and the gate of the transistor N7 respectively;
[0015] The gate of the transistor N6 is electrically connected to the gate of the transistor N10 and the gate of the transistor N11 respectively;
[0016] The gate of the transistor N8 is electrically connected to the gate of the transistor N9 and the gate of the transistor N12 respectively. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 The utility model is a circuit diagram of a novel integrator limiting circuit. DETAILED DESCRIPTION
[0018] The following description is used to disclose the utility model so that those skilled in the art can implement the utility model. The preferred embodiments described below are only examples, and those skilled in the art can think of other obvious variations. The basic principles of the utility model defined in the following description can be applied to other embodiments, variations, improvements, equivalents, and other technical solutions that do not deviate from the spirit and scope of the utility model.
[0019] The utility model discloses a novel integrator limiting circuit. The specific embodiments of the utility model are further described below in conjunction with preferred embodiments.
[0020] In the embodiments of the present invention, those skilled in the art note that the GND and the like involved in the present invention may be regarded as prior art.
[0021] Preferred embodiments.
[0022] The utility model discloses a novel integrator limiting circuit, comprising a first-stage comparison circuit and a second-stage comparison circuit, wherein the first-stage comparison circuit and the second-stage comparison circuit are electrically connected, wherein:
[0023] The first stage comparison circuit includes transistors P2, P7, P8, P9, N3-N8, the source of transistor P2 is connected to VDD and the drain of transistor P2 is electrically connected to the source of transistor P7, the source of transistor P8 and the source of transistor P9 respectively, the gate of transistor P7 is connected to the reference voltage Vlim, the gate of transistor P8 is connected to the output terminal OUT+ and the gate of transistor P9 is connected to the output terminal OUT-;
[0024] The sources of transistors N3-N8 are all connected to GND, the drain of transistor N3 and the drain of transistor N4 are all electrically connected to the drain of transistor P7, the drain of transistor N5 and the drain of transistor N6 are all electrically connected to the drain of transistor P8, and the drain of transistor N7 and the drain of transistor N8 are all electrically connected to the drain of transistor P9;
[0025] The second stage comparison circuit includes transistors P3-P6, N9-N12, the source of transistor P3, the source of transistor P4, the source of transistor P5 and the source of transistor P6 are all connected to VDD, the gate of transistor P3 is electrically connected to the gate of transistor P4 and the gate of transistor P5 is electrically connected to the gate of transistor P6, the drain of transistor P4 is connected to the input terminal IN- and the drain of transistor P6 is connected to the input terminal IN+;
[0026] The drain of the transistor N9 is electrically connected to the drain of the transistor P3 , the drain of the transistor N10 is electrically connected to the drain of the transistor P4 , the drain of the transistor N11 is electrically connected to the drain of the transistor P5 , and the drain of the transistor N12 is electrically connected to the drain of the transistor P6 .
[0027] Specifically, the gate and drain of the transistor P3 are connected, and the gate and drain of the transistor P5 are connected.
[0028] More specifically, the gate and drain of the transistor N4 are connected, the gate and drain of the transistor N6 are connected, and the gate and drain of the transistor N8 are connected.
[0029] Furthermore, the first stage comparison circuit further includes a transistor P1, a source of the transistor P1 is connected to VDD and a gate of the transistor P1 is connected to a gate of the transistor P2, and a gate and a drain of the transistor P1 are connected (for providing a bias current).
[0030] Furthermore, the first-stage comparison circuit also includes a transistor N1 and a transistor N2, the source of the transistor N1 and the source of the transistor N2 are both connected to GND, the drain of the transistor N1 is connected to the bias current terminal Bias and the drain of the transistor N2 is connected to the drain of the transistor P1, and the gate of the transistor N1 and the gate of the transistor N2 are electrically connected (for providing a bias current).
[0031] Preferably, the gate of transistor N2 is electrically connected to the gate of transistor N3, the gate of transistor N5 and the gate of transistor N7 respectively;
[0032] The gate of the transistor N6 is electrically connected to the gate of the transistor N10 and the gate of the transistor N11 respectively;
[0033] The gate of the transistor N8 is electrically connected to the gate of the transistor N9 and the gate of the transistor N12 respectively.
[0034] For this utility model:
[0035] In the figure, P2-P9, N3-N12 form a two-stage comparator. The gate of one input terminal P7 of the comparator is connected to the reference voltage Vlim, which is slightly lower than the valley value of the triangle wave. The gates of the other input terminals P8 and P9 of the comparator are connected to the outputs OUT+ and OUT- of the integrator respectively, and the output of the comparator is connected to the inputs IN+ and IN- of the integrator. When the limiting circuit works, negative feedback is formed. (W / L) P2 =4(W / L) P1 ,(W / L) N3 =(W / L) N5 =(W / L) N7 =2(W / L) N2(The width-to-length ratio between the transistors is set to ultimately ensure that when the output terminal is lower than the reference voltage Vlim, current flows through the transistor N6 or N8 connected to the output terminal, thereby starting negative feedback limiting).
[0036] At zero input, The limiter circuit does not work; when there is input, one of OUT+ and OUT- is higher than Another one below When lower than When the output terminal OUT is close to and lower than Vlim, the limiting circuit starts to work, and the output terminal OUT is raised and limited to Vlim through negative feedback. The traditional structure does not have relevant current mirrors N3, N5, and N7, so the comparator gain must be very large to ensure that the limiting circuit does not work in advance. Too large a comparator gain will affect the integrator loop, which is difficult to design. After adding current mirrors N3, N5, and N7, when OUT is higher than Vlim, N3 is always in the saturation region, half of the current of P2 flows through N3, and the other half flows through N5 and N7 (N5 and N7 are in the linear region). When OUT is exactly equal to Vlim, N3 is still in the saturation region, half of the current of P2 flows through N3, and the other half flows through N5 / N7 (one is in the saturation region and the other is in the cut-off region. The transistor in the saturation region passes current. For example, when out+ is equal to v When out+ is lower than Vlim, N5 is in the saturation region and current flows through it, while N7 is in the cut-off region and no current flows through it), when out+ is lower than Vlim, N3 is in the linear region (the current provided is less than half of P2), and N5 / N7 are in the saturation region (the current provided is equal to half of P2). At this time, current flows through N6 / N8 (for example, when out+ is lower than vlim, N5 is in the saturation region, N7 is in the cut-off region, N6 passes current but N8 has no current), negative feedback starts to work, and OUT is limited to Vlim, so that the comparator gain can be designed to be smaller (when out+ is lower than vlim, current flows through N6 and no current flows through N8, which will pull down in- and raise in+, in- is low and in+ is high, resulting in out+ high and out- low, thus forming a negative feedback, which ultimately limits out+ to vlim; the same principle applies to out- low).
[0037] It is worth mentioning that the technical features such as GND involved in this utility model patent application should be regarded as prior art. The specific structure, working principle and possible control method and spatial layout method of these technical features can be selected by conventional methods in the field and should not be regarded as the invention point of this utility model patent. This utility model patent will not be further elaborated.
[0038] For those skilled in the art, it is still possible to modify the technical solutions described in the aforementioned embodiments, or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present utility model should be included in the protection scope of the present utility model.
Claims
1. A novel integrator limiting circuit, characterized in that: The first-stage comparison circuit and the second-stage comparison circuit are electrically connected, wherein: The first stage comparison circuit includes transistors P2, P7, P8, P9, N3-N8, the source of transistor P2 is connected to VDD and the drain of transistor P2 is electrically connected to the source of transistor P7, the source of transistor P8 and the source of transistor P9 respectively, the gate of transistor P7 is connected to the reference voltage Vlim, the gate of transistor P8 is connected to the output terminal OUT+ and the gate of transistor P9 is connected to the output terminal OUT-; The sources of transistors N3-N8 are all connected to GND, the drain of transistor N3 and the drain of transistor N4 are all electrically connected to the drain of transistor P7, the drain of transistor N5 and the drain of transistor N6 are all electrically connected to the drain of transistor P8, and the drain of transistor N7 and the drain of transistor N8 are all electrically connected to the drain of transistor P9; The second stage comparison circuit includes transistors P3-P6, N9-N12, the source of transistor P3, the source of transistor P4, the source of transistor P5 and the source of transistor P6 are all connected to VDD, the gate of transistor P3 is electrically connected to the gate of transistor P4 and the gate of transistor P5 is electrically connected to the gate of transistor P6, the drain of transistor P4 is connected to the input terminal IN- and the drain of transistor P6 is connected to the input terminal IN+; The drain of the transistor N9 is electrically connected to the drain of the transistor P3 , the drain of the transistor N10 is electrically connected to the drain of the transistor P4 , the drain of the transistor N11 is electrically connected to the drain of the transistor P5 , and the drain of the transistor N12 is electrically connected to the drain of the transistor P6 .
2. A novel integrator limiting circuit according to claim 1, characterized in that: The gate and drain of the transistor P3 are connected, and the gate and drain of the transistor P5 are connected.
3. A novel integrator limiting circuit according to claim 2, characterized in that: The gate and drain of the transistor N4 are connected, the gate and drain of the transistor N6 are connected, and the gate and drain of the transistor N8 are connected.
4. A novel integrator limiting circuit according to claim 3, characterized in that: The first stage comparison circuit further includes a transistor P1 , a source of the transistor P1 is connected to VDD, a gate of the transistor P1 is connected to a gate of the transistor P2 , and a gate and a drain of the transistor P1 are connected.
5. A novel integrator limiting circuit according to claim 4, characterized in that: The first stage comparison circuit also includes a transistor N1 and a transistor N2, the source of the transistor N1 and the source of the transistor N2 are both connected to GND, the drain of the transistor N1 is connected to the bias current terminal Bias and the drain of the transistor N2 is connected to the drain of the transistor P1, and the gate of the transistor N1 is electrically connected to the gate of the transistor N2.
6. A novel integrator limiting circuit according to claim 5, characterized in that: The gate of the transistor N2 is electrically connected to the gate of the transistor N3, the gate of the transistor N5 and the gate of the transistor N7 respectively; The gate of the transistor N6 is electrically connected to the gate of the transistor N10 and the gate of the transistor N11 respectively; The gate of the transistor N8 is electrically connected to the gate of the transistor N9 and the gate of the transistor N12 respectively.