Wafer test circuit and wafer test system

Abstract

The utility model discloses a wafer test circuit and a wafer test system, and relates to the technical field of wafer test. The wafer test circuit comprises a gating control module, a scanning voltage module, a current sampling module and an energy storage and discharge module, and the energy storage and discharge module can discharge capacitor charges in a target wafer chip so as to ensure that the charges on a capacitor in the target wafer chip are not left. According to the wafer test circuit provided by the embodiment of the invention, the charge on the capacitor in the target wafer chip can be removed, so that the output test current is ensured not to be influenced by the residual charge of the capacitor, and the accuracy of judging the quality of the target wafer chip is further improved.

Description

Technical Field

[0001] The utility model relates to the technical field of wafer testing, in particular to a wafer testing circuit and a wafer testing system. Background Art

[0002] At present, LED display adopts active drive (AM) mode, which is realized by 2T1C wafer chip. Among them, 2T1C wafer chip is composed of at least one group of transistors, and each group of transistors is composed of two transistors (select transistor and drive transistor) and a storage capacitor.

[0003] In the related art, in the wafer testing link after the 2T1C wafer chip is completed, it is necessary to sample the test current output by the 2T1C wafer chip to determine the quality of the 2T1C wafer chip. However, during the above test process, there is a residual charge on the storage capacitor in the 2T1C wafer chip, which affects the test current output by the 2T1C wafer chip, resulting in a deviation between the output test current and the actual value, thereby reducing the accuracy of the quality judgment of the 2T1C wafer chip. Therefore, how to provide a wafer testing circuit to improve the accuracy of the quality judgment of the 2T1C wafer chip has become a technical problem that needs to be solved urgently. Utility Model Content

[0004] The utility model aims to solve at least one of the technical problems existing in the prior art. To this end, the utility model proposes a wafer testing circuit, which can improve the accuracy of determining the quality of 2T1C wafer chips.

[0005] The utility model also provides a wafer testing system having the wafer testing circuit.

[0006] According to the wafer test circuit of the first aspect of the present utility model, the wafer test circuit is applied to a wafer test system, wherein the wafer test system includes a host computer; the wafer test circuit includes:

[0007] A gating control module, the gating control module is electrically connected to the host computer and the target wafer chip respectively; wherein the host computer is used to provide a gating control signal, and the gating control module is used to generate a target gating signal according to the gating control signal;

[0008] A scanning voltage module, the scanning voltage module is electrically connected to the host computer and the target wafer chip respectively; wherein the host computer is used to generate a scanning control signal according to a preset scanning timing, the scanning voltage module is used to generate a scanning voltage according to the scanning control signal, and the target wafer chip is used to generate a test current according to the target selection signal and the scanning voltage;

[0009] A current sampling module, the current sampling module is electrically connected to the host computer and the target wafer chip respectively, and the current sampling module is used to sample the test current to obtain a test sampling signal; wherein the host computer is used to calculate the target current data of the target wafer chip according to the test sampling signal;

[0010] An energy storage discharge module, the energy storage discharge module is electrically connected to the host computer and the target wafer chip respectively; wherein the host computer is also used to provide a discharge control signal, and the energy storage discharge module is used to control the discharge of the capacitor charge in the target wafer chip according to the discharge control signal.

[0011] According to the wafer test circuit of the embodiment of the utility model, at least the following beneficial effects are achieved: the gating control module generates a target gating signal to control the gating transistors to be turned on in the target wafer chip; the scanning voltage module generates a scanning voltage to control the target wafer chip to adjust the output test current in real time according to the scanning voltage; the current sampling module samples the test current output by the target wafer chip, and outputs the obtained test sampling signal to the host computer, and the host computer calculates the target current data of the target wafer chip according to the test sampling signal, so as to test the quality of the target wafer chip; the energy storage discharge module can discharge the capacitor charge in the target wafer chip, so as to ensure that there is no residual charge on the capacitor in the target wafer chip. The wafer test circuit of this embodiment can clear the charge on the capacitor in the target wafer chip, thereby ensuring that the output test current is not affected by the residual charge of the capacitor, thereby improving the accuracy of the quality judgment of the target wafer chip.

[0012] According to some embodiments of the present utility model, the target wafer chip includes: a first voltage-controlled flow element, a second voltage-controlled flow element, and a target capacitor, wherein the gate of the first voltage-controlled flow element is electrically connected to the selection control module, the source of the first voltage-controlled flow element is electrically connected to the scanning voltage module, the drain of the first voltage-controlled flow element is electrically connected to the gate of the second voltage-controlled flow element, the source of the second voltage-controlled flow element is grounded, the drain of the second voltage-controlled flow element is electrically connected to the current sampling module, one end of the target capacitor is electrically connected to the gate of the second voltage-controlled flow element, and the other end of the target capacitor is electrically connected to the source of the second voltage-controlled flow element; wherein the first voltage-controlled flow element is used to be turned on according to the target selection signal so that the gate of the second voltage-controlled flow element receives the scanning voltage; the second voltage-controlled flow element is used to adjust the test current output by the drain of the second voltage-controlled flow element according to the scanning voltage;

[0013] The energy storage discharge module comprises:

[0014] a discharge resistor, one end of which is electrically connected to a connection node between the target capacitor and a ground terminal;

[0015] A first relay, wherein the first relay is respectively electrically connected to a connection node between the target capacitor and the gate of the second voltage-controlled current element, the other end of the discharge resistor, and the host computer, and the first relay is used to be turned on according to the discharge control signal to discharge the target capacitor to the ground.

[0016] According to some embodiments of the present utility model, the gating control signal includes a voltage amplitude adjustment signal and a first conduction control signal, and the gating control module includes:

[0017] a first operational amplifier, the first operational amplifier being electrically connected to the host computer, and the first operational amplifier being used for performing a voltage amplitude adjustment operation according to the voltage amplitude adjustment signal to generate the target selection signal;

[0018] A second relay, wherein the second relay is electrically connected to the host computer, the first operational amplifier and the gate of the first voltage-controlled current element respectively, and the second relay is used to be turned on according to the first conduction control signal so that the gate of the first voltage-controlled current element receives the target selection signal.

[0019] According to some embodiments of the present utility model, the scanning control signal includes a scanning timing adjustment signal and a second conduction control signal, and the scanning voltage module includes:

[0020] a second operational amplifier, the second operational amplifier being electrically connected to the host computer, and the second operational amplifier being used for performing a timing maintenance operation according to the scan timing adjustment signal to generate the scan voltage;

[0021] A third relay, wherein the third relay is electrically connected to the host computer, the second operational amplifier and the source of the first voltage-controlled current element respectively, and the third relay is used to be turned on according to the second conduction control signal so that the source of the first voltage-controlled current element receives the scanning voltage.

[0022] According to some embodiments of the present utility model, the current sampling module includes:

[0023] a sampling resistor, one end of which is electrically connected to the drain of the second voltage-controlled current element, and the other end of which is electrically connected to a preset reference voltage source;

[0024] a third operational amplifier, wherein an input end of the third operational amplifier is electrically connected to one end of the sampling resistor, and the third operational amplifier is used to amplify a first test voltage at one end of the sampling resistor;

[0025] a fourth operational amplifier, wherein an input end of the fourth operational amplifier is electrically connected to the other end of the sampling resistor, and the fourth operational amplifier is used to amplify the second test voltage at the other end of the sampling resistor;

[0026] A fifth operational amplifier, wherein the input end of the fifth operational amplifier is electrically connected to the output end of the third operational amplifier and the output end of the fourth operational amplifier respectively, the output end of the fifth operational amplifier is electrically connected to the host computer, and the fifth operational amplifier is used to generate the test sampling signal according to the first test voltage after the amplification operation and the second test voltage after the amplification operation.

[0027] According to some embodiments of the present utility model, the wafer testing circuit further includes:

[0028] A monitoring voltage module is electrically connected to the scanning voltage module, the connection node of the target wafer chip and the host computer respectively, and the monitoring voltage module is used to sample the scanning voltage.

[0029] According to some embodiments of the present utility model, the wafer testing circuit further includes:

[0030] A power control module, wherein the power control module is electrically connected to an external power supply, the target wafer chip, the gating control module, the scanning voltage module, the current sampling module, the energy storage discharge module and the monitoring voltage module respectively; wherein the external power supply is used to provide a mains power supply signal, and the power control module is used to generate a target power supply signal according to preset power supply parameters and the mains power supply signal, so as to respectively power the target wafer chip, the gating control module, the scanning voltage module, the current sampling module, the energy storage discharge module and the monitoring voltage module.

[0031] According to the second aspect of the present invention, a wafer testing system includes:

[0032] The wafer testing circuit according to the first aspect of the present utility model;

[0033] A host computer is electrically connected to the gating control module, the scanning voltage module, the current sampling module and the energy storage discharge module respectively.

[0034] The wafer testing system according to the embodiment of the utility model has at least the following beneficial effects: the wafer testing system can improve the accuracy of quality judgment of 2T1C wafer chips by adopting the above-mentioned wafer testing circuit.

[0035] Additional aspects and advantages of the present invention will be given in part in the following description, and in part will become apparent from the following description, or will be learned through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The present invention is further described below with reference to the accompanying drawings and embodiments, wherein:

[0037] Figure 1 A module block diagram of a specific embodiment of the wafer test circuit of the utility model;

[0038] Figure 2 A circuit schematic diagram of a specific embodiment of the target wafer chip of the utility model;

[0039] Figure 3 It is a schematic diagram of a specific embodiment of the wafer testing circuit of the utility model;

[0040] Figure 4 The schematic diagram is a circuit diagram of a specific embodiment of the wafer testing circuit part of the utility model.

[0041] Reference numerals:

[0042] A gating control module 100 , a scanning voltage module 200 , a current sampling module 300 , an energy storage discharge module 400 , a host computer 500 , a target wafer chip 600 , a monitoring voltage module 700 , a leakage protection module 800 , and a power control module 900 . DETAILED DESCRIPTION

[0043] The embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0044] In the description of the present invention, it should be understood that descriptions involving orientation, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0045] In the description of the present utility model, "several" means more than one, "many" means more than two, "greater than", "less than", "exceed" etc. are understood to exclude the number itself, and "above", "below", "within" etc. are understood to include the number itself. If there is a description of "first" or "second", it is only used to distinguish the technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0046] In the description of the present invention, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in the present invention based on the specific content of the technical solution.

[0047] In the description of the utility model, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the utility model. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0048] At present, LED display adopts active drive (AM) mode, which is realized by 2T1C wafer chip. Among them, 2T1C wafer chip is composed of at least one group of transistors, and each group of transistors is composed of two transistors (select transistor and drive transistor) and a storage capacitor.

[0049] In the related art, in the wafer testing link after the 2T1C wafer chip is completed, it is necessary to sample the test current output by the 2T1C wafer chip to determine the quality of the 2T1C wafer chip. However, during the above test process, there is a residual charge on the storage capacitor in the 2T1C wafer chip, which affects the test current output by the 2T1C wafer chip, resulting in a deviation between the output test current and the actual value, thereby reducing the accuracy of the quality judgment of the 2T1C wafer chip. Therefore, how to provide a wafer testing circuit to improve the accuracy of the quality judgment of the 2T1C wafer chip has become a technical problem that needs to be solved urgently.

[0050] Based on this, the embodiments of the present utility model provide a wafer testing circuit and a wafer testing system, which can improve the accuracy of quality judgment on 2T1C wafer chips.

[0051] like Figure 1As shown, an embodiment of the utility model provides a wafer test circuit, which includes: a gating control module 100, a scanning voltage module 200, a current sampling module 300 and an energy storage discharge module 400. The wafer test circuit is applied to a wafer test system, and the wafer test system includes a host computer 500. The gating control module 100 is electrically connected to the host computer 500 and the target wafer chip 600 respectively; wherein the host computer 500 is used to provide a gating control signal, and the gating control module 100 is used to generate a target gating signal according to the gating control signal; the scanning voltage module 200 is electrically connected to the host computer 500 and the target wafer chip 600 respectively; wherein the host computer 500 is used to generate a scanning control signal according to a preset scanning timing, the scanning voltage module 200 is used to generate a scanning voltage according to the scanning control signal, and the target wafer chip 600 is used to generate a test current according to the target gating signal and the scanning voltage; The current sampling module 300 is electrically connected to the host computer 500 and the target wafer chip 600 respectively, and the current sampling module 300 is used to sample the test current to obtain a test sampling signal; wherein, the host computer 500 is used to calculate the target current data of the target wafer chip 600 according to the test sampling signal; the energy storage discharge module 400 is electrically connected to the host computer 500 and the target wafer chip 600 respectively; wherein, the host computer 500 is also used to provide a discharge control signal, and the energy storage discharge module 400 is used to control the discharge of the capacitor charge in the target wafer chip 600 according to the discharge control signal.

[0052] Specifically, the target wafer chip 600 is a 2T1C wafer chip to be tested. The host computer 500 can be a control device such as an IPC industrial control microcomputer, and the host computer 500 is electrically connected to the gating control module 100, the scanning voltage module 200, the current sampling module 300 and the energy storage discharge module 400.

[0053] The host computer 500 provides a gating control signal to the gating control module 100, and the gating control module 100 adjusts the voltage amplitude of the output signal according to the gating control signal to output the target gating signal to the target wafer chip 600. The host computer 500 provides a scanning control signal to the scanning voltage module 200, and the scanning control signal is adjusted in real time by the host computer 500 according to a preset scanning timing, wherein the scanning timing includes digital signal adjustment parameters such as voltage amplitude, trigger duration, etc. After receiving the scanning control signal, the scanning voltage module 200 outputs a scanning voltage to the target wafer chip 600.

[0054] The gating control module 100 and the scanning voltage module 200 are both electrically connected to the target wafer chip 600 by a probe contact method. The target wafer chip 600 receives the target gating signal output by the gating control module 100 and the scanning voltage output by the scanning voltage module 200, respectively, wherein the target gating signal can control the gating transistor required to be turned on in the target wafer chip 600 to be turned on, and the scanning voltage can control the conduction current of the driving transistor in the target wafer chip 600, so that the target wafer chip 600 outputs the corresponding test current.

[0055] The current sampling module 300 is electrically connected to the target wafer chip 600 by a probe contact method. The current sampling module 300 samples the test current output by the target wafer chip 600 to obtain a test sampling signal, that is, the test sampling signal contains the information of the above test current. After receiving the test sampling signal, the host computer 500 calculates the target current data according to the test sampling signal through relevant calculation software. Among them, the target current data can reflect the quality of the target wafer chip 600.

[0056] The energy storage discharge module 400 is electrically connected to the target wafer chip 600 , receives a discharge control signal provided by the host computer 500 , and discharges the capacitor charge in the target wafer chip 600 according to the discharge control signal to clear the charge on the capacitor in the target wafer chip 600 .

[0057] According to the wafer test circuit of the embodiment of the utility model, the charge on the capacitor in the target wafer chip 600 can be cleared, thereby ensuring that the output test current is not affected by the residual charge on the capacitor, thereby improving the accuracy of the quality judgment of the target wafer chip 600.

[0058] like Figure 2 , Figure 3As shown, in some specific embodiments of the present utility model, the target wafer chip 600 includes: a first voltage-controlled flow element T1, a second voltage-controlled flow element T2, and a target capacitor C, and the energy storage discharge module 400 includes: a discharge resistor R1 and a first relay K1. The gate of the first voltage-controlled flow element T1 is electrically connected to the selection control module 100, the source of the first voltage-controlled flow element T1 is electrically connected to the scanning voltage module 200, the drain of the first voltage-controlled flow element T1 is electrically connected to the gate of the second voltage-controlled flow element T2, the source of the second voltage-controlled flow element T2 is grounded, the drain of the second voltage-controlled flow element T2 is electrically connected to the current sampling module 300, one end of the target capacitor C is electrically connected to the gate of the second voltage-controlled flow element T2, and the other end of the target capacitor C is electrically connected to the source of the second voltage-controlled flow element T2; wherein, the first voltage-controlled flow element T1 is electrically connected to the gate of the second voltage-controlled flow element T2, and the second voltage-controlled flow element T2 is electrically connected to the gate of the second voltage-controlled flow element T2. The first relay K1 is respectively electrically connected to the target capacitor C and the connection node of the gate of the second controlled voltage current element T2, the other end of the discharge resistor R1, and the host computer 500, and the first relay K1 is used to be turned on according to the discharge control signal to discharge the target capacitor C to the ground.

[0059] Specifically, the target wafer chip 600 is composed of at least one group of transistor combinations, each of which is composed of a gate transistor, a drive transistor and a storage capacitor, wherein the gate transistor is the first voltage control current element T1, and the drive transistor is the second voltage control current element T2. Figure 2 , Figure 4 , three groups of transistor combinations are arranged in the target wafer chip 600, and each group of transistor combinations has three signal ports, namely, Vsel port, Vdata port and Vdd port. Among them, the gating control module 100 inputs the target gating signal to the gate of the first voltage-controlled current element T1 in each group of transistor combinations through the Vsel port, the scanning voltage module 200 inputs the scanning voltage to the source of the first voltage-controlled current element T1 in each group of transistor combinations through the Vdata port, and the second voltage-controlled current element T2 in each group of transistor combinations outputs the test current to the current sampling module 300 through the Vdd port.

[0060] In different transistor combinations, the gate voltage amplitude required for the first voltage-controlled flow element T1 to be turned on is different. Since the gating control module 100 can adjust the voltage amplitude of the output target gating signal according to the gating control signal provided by the host computer 500, the voltage amplitude of the target gating signal is changed by adjusting the gating control signal provided by the host computer 500, thereby selecting the first voltage-controlled flow element T1 to be turned on from the three transistor combinations. After the first voltage-controlled flow element T1 is turned on according to the target gating signal, the gate of the second voltage-controlled flow element T2 can receive the scanning voltage provided by the scanning voltage module 200.

[0061] Each transistor combination is electrically connected to a different scan voltage module 200, for example, Figure 2 , the three transistor combinations are electrically connected to three different scanning voltage modules 200 through their corresponding Vdata ports, that is, the wafer test circuit needs to be provided with three scanning voltage modules 200. After the first voltage control current element T1 is turned on, the second voltage control current element T2 adjusts the conduction current according to the scanning voltage, so that the target wafer chip 600 outputs the corresponding test current. Since the scanning voltage module 200 can adjust the scanning timing of the output scanning voltage according to the scanning control signal provided by the host computer 500, and the scanning timings of the scanning voltages provided by different scanning voltage modules 200 are different from each other, the current test of each transistor combination in the target wafer chip 600 can be realized respectively.

[0062] A target capacitor C is also provided between the gate and source of the second voltage-controlled current element T2, and the target capacitor C is the storage capacitor introduced in the above embodiment. Since there is charge left on the target capacitor C in the target wafer chip 600 during the above test, there is an uncontrolled charge voltage between the gate and source of the second voltage-controlled current element T2, thereby affecting the test current output by the target wafer chip 600.

[0063] The energy storage discharge module 400 is connected in parallel to both ends of the target capacitor C. The first switch end of the first relay K1 in the energy storage discharge module 400 is connected in series with the discharge resistor R1 and grounded. The second switch end of the first relay K1 is electrically connected to one end of the target capacitor C. The connection node between the discharge resistor R1 and the ground end is electrically connected to the other end of the target capacitor C. The trigger end of the first relay K1 is electrically connected to the host computer 500. When the first relay K1 receives the discharge control signal provided by the host computer 500, the first relay K1 is turned on, so that a current loop is formed between the target capacitor C, the first relay K1, the discharge resistor R1, and the ground end, that is, the target capacitor C can be discharged to the ground end through the first relay K1 and the discharge resistor R1, so as to clear the residual charge on the target capacitor C.

[0064] In some specific embodiments, when the host computer 500 controls the scanning voltage module 200 to stop providing the scanning voltage, the host computer 500 controls the gating control module 100 to delay providing the target gating signal by about 10us. During the delay period, the host computer 500 controls the first relay K1 to turn on through the discharge control signal, thereby clearing the residual charge on the target capacitor C, ensuring that the target capacitor C does not affect the gate voltage of the second voltage-controlled flow element T2, thereby eliminating the interference of the subsequent second voltage-controlled flow element T2 when adjusting the conduction current according to the scanning voltage.

[0065] like Figure 3 As shown, in some specific embodiments of the present invention, the gating control signal includes a voltage amplitude adjustment signal and a first conduction control signal, and the gating control module 100 includes: a first operational amplifier A1 and a second relay K2. The first operational amplifier A1 is electrically connected to the host computer 500, and the first operational amplifier A1 is used to perform a voltage amplitude adjustment operation according to the voltage amplitude adjustment signal to generate a target gating signal; the second relay K2 is electrically connected to the host computer 500, the first operational amplifier A1 and the gate of the first voltage-controlled current element T1 respectively, and the second relay K2 is used to conduct according to the first conduction control signal so that the gate of the first voltage-controlled current element T1 receives the target gating signal.

[0066] Specifically, the first operational amplifier A1 and the second relay K2 are connected in series, and the first operational amplifier A1 and the second relay K2 are both electrically connected to the host computer 500. The host computer 500 outputs a voltage amplitude adjustment signal to the first operational amplifier A1, and the first operational amplifier A1 adjusts the voltage amplitude of the generated target selection signal according to the voltage amplitude adjustment signal. The host computer 500 outputs a first conduction control signal to the second relay K2, so that the second relay K2 is turned on, so that the target wafer chip 600 can receive the target selection signal.

[0067] like Figure 3 As shown, in some specific embodiments of the present invention, the scan control signal includes a scan timing adjustment signal and a second conduction control signal, and the scan voltage module 200 includes: a second operational amplifier A2 and a third relay K3. The second operational amplifier A2 is electrically connected to the host computer 500, and the second operational amplifier A2 is used to perform a timing maintenance operation according to the scan timing adjustment signal to generate a scan voltage; the third relay K3 is electrically connected to the host computer 500, the second operational amplifier A2 and the source of the first voltage-controlled current element T1, respectively, and the third relay K3 is used to conduct according to the second conduction control signal so that the source of the first voltage-controlled current element T1 receives the scan voltage.

[0068] Specifically, the second operational amplifier A2 and the third relay K3 are connected in series, and the second operational amplifier A2 and the third relay K3 are both electrically connected to the host computer 500. The host computer 500 adjusts the voltage amplitude, trigger duration and other parameters of the output signal in real time according to the preset scanning timing, so as to output the scanning timing adjustment signal to the second operational amplifier A2. The second operational amplifier A2 is an operational amplifier follower, and the second operational amplifier A2 performs a timing maintenance operation according to the scanning timing adjustment signal to ensure that the scanning timing of the output scanning voltage meets the scanning timing preset by the host computer 500. The host computer 500 outputs a second conduction control signal to the third relay K3, so that the third relay K3 is turned on to output the scanning voltage to the target wafer chip 600.

[0069] like Figure 3 As shown, in some specific embodiments of the present utility model, the current sampling module 300 includes: a sampling resistor Rs, a third operational amplifier A3, a fourth operational amplifier A4 and a fifth operational amplifier A5. One end of the sampling resistor Rs is electrically connected to the drain of the second voltage control current element T2, and the other end of the sampling resistor Rs is electrically connected to the preset reference voltage source VDM; the input end of the third operational amplifier A3 is electrically connected to one end of the sampling resistor Rs, and the third operational amplifier A3 is used to amplify the first test voltage at one end of the sampling resistor Rs; the input end of the fourth operational amplifier A4 is electrically connected to the other end of the sampling resistor Rs, and the fourth operational amplifier A4 is used to amplify the second test voltage at the other end of the sampling resistor Rs; the input end of the fifth operational amplifier A5 is electrically connected to the output end of the third operational amplifier A3 and the output end of the fourth operational amplifier A4 respectively, and the output end of the fifth operational amplifier A5 is electrically connected to the host computer 500, and the fifth operational amplifier A5 is used to generate a test sampling signal according to the first test voltage after the amplification operation and the second test voltage after the amplification operation.

[0070] Specifically, the sampling resistor Rs is electrically connected to the preset reference voltage source VDM and the drain of the second voltage-controlled flow element T2 in the target wafer chip 600, respectively, wherein the voltage of the reference voltage source VDM can be set as required. Since the second voltage-controlled flow element T2 adjusts the conduction current according to the scan voltage, the voltage of the drain of the second voltage-controlled flow element T2 changes accordingly. Since the voltage value of the reference voltage source VDM is fixed, there is a potential difference between the reference voltage source VDM and the drain of the second voltage-controlled flow element T2, that is, there is a test current, which flows through the sampling resistor Rs.

[0071] The sampling resistor Rs is also electrically connected to the third operational amplifier A3 and the fourth operational amplifier A4, respectively, and the third operational amplifier A3 and the fourth operational amplifier A4 both have high impedance and high common mode characteristics. The third operational amplifier A3 and the fourth operational amplifier A4 are respectively arranged at both ends of the sampling resistor Rs, so as to isolate the potentials at both ends of the sampling resistor Rs, and the third operational amplifier A3 amplifies the first test voltage at one end of the sampling resistor Rs, and the fourth operational amplifier A4 amplifies the second test voltage at the other end of the sampling resistor Rs. The output ends of the third operational amplifier A3 and the fourth operational amplifier A4 are both electrically connected to the input end of the fifth operational amplifier A5, and the fifth operational amplifier A5 further amplifies the first test voltage and the second test voltage after the signal amplification, thereby obtaining a test sampling signal.

[0072] In some specific embodiments, referring to Figure 4 , the target wafer chip 600 is provided with three transistor combinations, each transistor combination is electrically connected to a different current sampling module 300, that is, the wafer test circuit needs to be provided with three current sampling modules 300. The three transistor combinations are electrically connected to three different current sampling modules 300 through their corresponding Vout ports, and the three sampling resistors Rs1, Rs2, and Rs3 are the sampling resistors Rs in different current sampling modules 300. The connection relationship and functions of other components in the current sampling module 300 can refer to the description of the above embodiment.

[0073] like Figure 3 As shown, in some specific embodiments of the present invention, the wafer test circuit further includes a monitoring voltage module 700. The monitoring voltage module 700 is electrically connected to the connection nodes of the scanning voltage module 200 and the target wafer chip 600 and the host computer 500, and the monitoring voltage module 700 is used to sample the scanning voltage.

[0074] Specifically, the monitoring voltage module 700 can sample the scanning voltage from the connection node between the scanning voltage module 200 and the target wafer chip 600, and feed back the sampled scanning voltage to the host computer 500 in real time, so that the host computer 500 can make corresponding adjustments to the scanning timing of the scanning voltage in time.

[0075] like Figure 3 As shown, in some specific embodiments of the present invention, the wafer test circuit further includes a leakage protection module 800. The leakage protection module 800 is electrically connected to the connection node of the current sampling module 300 and the target wafer chip 600, and the leakage protection module 800 is used to perform leakage protection on the test current.

[0076] Specifically, the leakage protection module 800 is set at the connection node between the current sampling module 300 and the target wafer chip 600. Since the current value of the test current generated by the second voltage control current element T2 ranges from 1 to 120uA, the current value is relatively weak, in order to reduce circuit losses, especially uncontrolled leakage, a corresponding leakage protection module 800 needs to be set. Figure 3 As shown, the leakage protection module 800 is mainly composed of an operational amplifier follower, which generates a potential equal to the connection node between the sampling resistor Rs and the drain of the second voltage-controlled current element T2. Since the drain pin of the second voltage-controlled current element T2 and the connection end of the sampling resistor Rs are at the same potential, the test current will not leak.

[0077] like Figure 3 As shown, in some specific embodiments of the utility model, the wafer test circuit also includes a power control module 900. The power control module 900 is electrically connected to the external power supply, the target wafer chip 600, the gating control module 100, the scanning voltage module 200, the current sampling module 300, and the energy storage discharge module 400 respectively; wherein the external power supply is used to provide a mains power supply signal, and the power control module 900 is used to generate a target power supply signal according to preset power supply parameters and the mains power supply signal, so as to respectively power the target wafer chip 600, the gating control module 100, the scanning voltage module 200, the current sampling module 300, and the energy storage discharge module 400.

[0078] Specifically, the external power supply is a mains power supply, and the input mains AC voltage range is 85-264V, which is universal worldwide. After receiving the AC mains power supply signal, the power control module 900 outputs a DC target power supply signal to the target wafer chip 600, the gating control module 100, the scanning voltage module 200, the current sampling module 300, and the energy storage discharge module 400 according to the preset power supply parameters. The preset power supply parameters represent the power supply voltage flow data required by each of the above-mentioned power supply modules. For example, the power control module 900 outputs three sets of DC low-voltage target power supply signals: 5V1000mA 2%, +12V200mA10%, -12V200mA 10%. Among them, the former forms a 5VDC that meets the power supply requirements after a simple filter capacitor and a Π-type LC filter circuit, and the latter two are then stabilized to +10V230mA 1% and -12V230mA1% respectively through their respective LDOs with higher requirements. Since the target wafer chip requires the highest test power accuracy, the power control module 900 also sets a 2.5V±Δ1.5mV standard reference power chip. The electronic relay can be controlled by the host computer 500 software to switch the operational amplifier feedback link ratio to 2 times and 3 times, so as to output a more stable and accurate target power supply signal for the target wafer chip 600: 5VDC30mA0.1%, 7.5VDC 30mA 0.1%.

[0079] The embodiment of the utility model further provides a wafer testing system, which includes: a host computer and a wafer testing circuit as described in any of the above embodiments. The host computer is electrically connected to the gating control module, the scanning voltage module, the current sampling module and the energy storage discharge module.

[0080] It can be seen that the contents of the above-mentioned wafer test circuit embodiment are all applicable to the embodiment of this host computer. The functions specifically implemented by this host computer embodiment are the same as those of the above-mentioned wafer test circuit embodiment, and the beneficial effects achieved are also the same as those achieved by the above-mentioned wafer test circuit embodiment.

[0081] The embodiments of the utility model are described in detail above in conjunction with the accompanying drawings, but the utility model is not limited to the above embodiments. Various changes can be made within the knowledge of ordinary technicians in the relevant technical field without departing from the purpose of the utility model. In addition, the embodiments of the utility model and the features in the embodiments can be combined with each other without conflict.

Claims

1. Wafer test circuit, It is characterized in that Applied to a wafer testing system, the wafer testing system includes a host computer; the wafer testing circuit includes: A gating control module, the gating control module is electrically connected to the host computer and the target wafer chip respectively; wherein the host computer is used to provide a gating control signal, and the gating control module is used to generate a target gating signal according to the gating control signal; A scanning voltage module, the scanning voltage module is electrically connected to the host computer and the target wafer chip respectively; wherein the host computer is used to generate a scanning control signal according to a preset scanning timing, the scanning voltage module is used to generate a scanning voltage according to the scanning control signal, and the target wafer chip is used to generate a test current according to the target selection signal and the scanning voltage; A current sampling module, the current sampling module is electrically connected to the host computer and the target wafer chip respectively, and the current sampling module is used to sample the test current to obtain a test sampling signal; wherein the host computer is used to calculate the target current data of the target wafer chip according to the test sampling signal; An energy storage discharge module, the energy storage discharge module is electrically connected to the host computer and the target wafer chip respectively; wherein the host computer is also used to provide a discharge control signal, and the energy storage discharge module is used to control the discharge of the capacitor charge in the target wafer chip according to the discharge control signal.

2. The wafer test circuit according to claim 1, It is characterized in that The target wafer chip includes: a first voltage-controlled flow element, a second voltage-controlled flow element, and a target capacitor, wherein the gate of the first voltage-controlled flow element is electrically connected to the selection control module, the source of the first voltage-controlled flow element is electrically connected to the scanning voltage module, the drain of the first voltage-controlled flow element is electrically connected to the gate of the second voltage-controlled flow element, the source of the second voltage-controlled flow element is grounded, the drain of the second voltage-controlled flow element is electrically connected to the current sampling module, one end of the target capacitor is electrically connected to the gate of the second voltage-controlled flow element, and the other end of the target capacitor is electrically connected to the source of the second voltage-controlled flow element; wherein the first voltage-controlled flow element is used to be turned on according to the target selection signal so that the gate of the second voltage-controlled flow element receives the scanning voltage; and the second voltage-controlled flow element is used to adjust the test current output by the drain of the second voltage-controlled flow element according to the scanning voltage; The energy storage discharge module comprises: a discharge resistor, one end of which is electrically connected to a connection node between the target capacitor and a ground terminal; A first relay, wherein the first relay is respectively electrically connected to a connection node between the target capacitor and the gate of the second voltage-controlled current element, the other end of the discharge resistor, and the host computer, and the first relay is used to be turned on according to the discharge control signal to discharge the target capacitor to the ground.

3. The wafer test circuit according to claim 2, It is characterized in that The gating control signal includes a voltage amplitude adjustment signal and a first conduction control signal, and the gating control module includes: a first operational amplifier, the first operational amplifier being electrically connected to the host computer, and the first operational amplifier being used for performing a voltage amplitude adjustment operation according to the voltage amplitude adjustment signal to generate the target selection signal; A second relay, wherein the second relay is electrically connected to the host computer, the first operational amplifier and the gate of the first voltage-controlled current element respectively, and the second relay is used to be turned on according to the first conduction control signal so that the gate of the first voltage-controlled current element receives the target selection signal.

4. The wafer test circuit according to claim 3, It is characterized in that The scanning control signal includes a scanning timing adjustment signal and a second conduction control signal, and the scanning voltage module includes: a second operational amplifier, the second operational amplifier being electrically connected to the host computer, and the second operational amplifier being used for performing a timing maintenance operation according to the scan timing adjustment signal to generate the scan voltage; A third relay, wherein the third relay is electrically connected to the host computer, the second operational amplifier and the source of the first voltage-controlled current element respectively, and the third relay is used to be turned on according to the second conduction control signal so that the source of the first voltage-controlled current element receives the scanning voltage.

5. The wafer test circuit according to claim 4, It is characterized in that The current sampling module comprises: a sampling resistor, one end of which is electrically connected to the drain of the second voltage-controlled current element, and the other end of which is electrically connected to a preset reference voltage source; a third operational amplifier, wherein an input end of the third operational amplifier is electrically connected to one end of the sampling resistor, and the third operational amplifier is used to amplify a first test voltage at one end of the sampling resistor; a fourth operational amplifier, wherein an input end of the fourth operational amplifier is electrically connected to the other end of the sampling resistor, and the fourth operational amplifier is used to amplify the second test voltage at the other end of the sampling resistor; A fifth operational amplifier, wherein the input end of the fifth operational amplifier is electrically connected to the output end of the third operational amplifier and the output end of the fourth operational amplifier respectively, the output end of the fifth operational amplifier is electrically connected to the host computer, and the fifth operational amplifier is used to generate the test sampling signal according to the first test voltage after the amplification operation and the second test voltage after the amplification operation.

6. The wafer test circuit according to claim 5, It is characterized in that Also includes: A monitoring voltage module is electrically connected to the scanning voltage module, the connection node of the target wafer chip and the host computer respectively, and the monitoring voltage module is used to sample the scanning voltage.

7. The wafer test circuit according to any one of claims 1 to 6, It is characterized in that Also includes: A leakage protection module is electrically connected to a connection node between the current sampling module and the target wafer chip, and is used to perform leakage protection on the test current.

8. The wafer testing circuit according to claim 6, It is characterized in that Also includes: A power control module, wherein the power control module is electrically connected to an external power supply, the target wafer chip, the gating control module, the scanning voltage module, the current sampling module, and the energy storage discharge module, respectively; wherein the external power supply is used to provide a mains power supply signal, and the power control module is used to generate a target power supply signal according to preset power supply parameters and the mains power supply signal, so as to respectively power the target wafer chip, the gating control module, the scanning voltage module, the current sampling module, and the energy storage discharge module.

9. Wafer test system, It is characterized in that include: The wafer test circuit according to any one of claims 1 to 7; A host computer is electrically connected to the gating control module, the scanning voltage module, the current sampling module and the energy storage discharge module respectively.

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