Image sensor

Abstract

The utility model provides a trench for a back side deep trench isolation (BDTI) structure. The trench is formed by using two etching methods: high aspect ratio etching and mouth etching. The trench has a wider upper portion (mouth) and a lower portion of the trench. The lower portion is narrower than the upper portion and has a higher aspect ratio. The trench exhibits a stepped change in width between the upper portion and the lower portion. The depth of the lower portion may be fixed to provide a high aspect ratio, but the aspect ratio is limited to an aspect ratio that may always fill the lower portion without creating voids. The overall depth of the groove may be varied by adjusting the depth of the mouth region. The resulting BDTI structure provides better optical performance characteristics to the image sensor than can be achieved using a single trench etch.

Description

Technical Field

[0001] The embodiment of the utility model relates to an image sensor. Background Art

[0002] Integrated circuits (ICs) including image sensors are widely used in modern electronic devices, such as cameras and cellular phones. Complementary metal-oxide semiconductor (CMOS) image sensors (CIS) have become common. Compared to charge-coupled devices (CCDs), CISs are increasingly advantageous due to low power consumption, small pixel size, fast data processing, and low manufacturing costs. As pixel size becomes smaller, manufacturing becomes increasingly difficult because it limits crosstalk between pixels. These are ongoing challenges for which only solutions can provide improved performance. Utility Model Content

[0003] In some embodiments, an image sensor includes: a semiconductor substrate having a front side and a back side; a photodetector located in the semiconductor substrate; one or more passivation layers located on the back side; and a backside deep trench isolation (BDTI) structure extending into the back side to laterally surround the photodetector, wherein in a first region, the BDTI structure exhibits an abrupt narrowing corresponding to a discontinuous change in a width of the BDTI structure relative to a depth of the BDTI structure at a height within the semiconductor substrate and above a bottom of the BDTI structure.

[0004] In some embodiments, an image sensor includes a semiconductor substrate including a front side and a back side; photodetectors arrayed in the semiconductor substrate; and a backside isolation structure extending into the back side between the photodetectors, wherein in a first region, the backside isolation structure has an upper portion and a lower portion both located in the semiconductor substrate; wherein the lower portion is narrower than the upper portion and has a higher aspect ratio; and the semiconductor substrate forms a protrusion at a junction between the upper portion and the lower portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The aspects of the present invention will be best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0006] Figures 1 to 4 An image sensor according to various embodiments of the present invention is shown.

[0007] Figures 5 to 17 A series of views illustrating a method for forming an image sensor according to some embodiments of the present invention.

[0008] FIG. 18A to FIG. 18B According to some embodiments Figures 5 to 17 changes in the process.

[0009] Figure 19 to Figure 20 According to some other embodiments Figures 5 to 17 changes in the process.

[0010] Figure 21 to Figure 22 According to some other embodiments Figures 5 to 17 changes in the process.

[0011] Figure 23 to Figure 24 is a flow chart of a manufacturing process according to some embodiments of the present invention. DETAILED DESCRIPTION

[0012] The utility model provides many different embodiments or examples for implementing the different features of the utility model. The following describes specific examples of components and configurations to simplify the content of the utility model. Of course, these examples are only examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are directly contacted, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be directly contacted. In addition, the utility model may repeat the figure numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0013] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0014] Some CIS designs are for back side illumination (BSI) and include an array of photodetectors within a semiconductor substrate. The photodetectors may be separated by a back side deep trench isolation (BDTI) structure, which is an isolation structure extending from its back side into the semiconductor substrate. The BDTI structure may include a square or ring-shaped component that laterally surrounds and separates the photodetectors. Forming the BDTI structure includes etching a BDTI trench in the back side of the semiconductor substrate and filling the BDTI trench with a material that provides the BDTI structure. As the photodetector pitch becomes smaller, the BDTI structure occupies a progressively larger proportion of the image sensor area. The tendency may be to make the BDTI structure narrower to offset this. As attempts are made to make the BDTI structure narrower, the BDTI trench becomes susceptible to pinching off at the top during backfill, leaving voids within the BDTI structure. These voids degrade optical performance characteristics.

[0015] According to the present invention, a BDTI trench is formed in a first region using a high-aspect ratio etch and a mouth etch. The mouth etch uses a mask having a layout similar to that of the mask used for the high-aspect ratio etch, but the mask used for the mouth etch has a wider opening. Due to these two etches, the BDTI trench has a wider upper portion (mouth) and a narrower lower portion with a higher aspect ratio. The BDTI trench exhibits a step change in width between the upper portion and the lower portion. The step change in width is a sharp narrowing of the type that produces a discontinuity in a graph of width relative to depth. The BDTI trench will form a horizontal lower surface at the height where the sudden narrowing occurs. The depth and width of the lower portion can be fixed to provide a high aspect ratio where the lower portion can always be filled without generating voids. The depth of the upper portion can be varied to achieve the desired total depth of the BDTI trench. The resulting BDTI structure can provide better optical performance characteristics for image sensors than can be achieved using a single trench etch.

[0016] Some aspects of the present invention are directed to an image sensor of the type formed by the method of the present invention. The image sensor includes a BDTI structure extending into the back side of a semiconductor substrate to laterally surround a photodetector. In a first region, the BDTI structure exhibits a step change in width within the semiconductor substrate. In some embodiments, the semiconductor substrate forms a ledge corresponding to the step change in width. In the first region, the BDTI structure includes an upper portion within the semiconductor substrate and above a level at which the step change occurs, and a lower portion within the semiconductor substrate and below the level at which the step change occurs. In some embodiments, the lower portion has a greater height (vertical extent) than the upper portion. In some embodiments, the lower portion has an aspect ratio that is greater than the aspect ratio of the upper portion. In some embodiments, the lower portion has a width that remains constant or decreases with increasing depth. The upper portion may also have a width that remains constant or decreases with increasing depth.

[0017] In some embodiments, there is a second region in which the BDTI structure does not exhibit a step change in width. In some embodiments, the floating diffusion region is formed close to the front side directly below the BDTI structure in the second region. The BDTI groove is shallower in the second region than in the first region. In the first region, the depth of the BDTI structure includes contributions from the upper portion and the lower portion. In some embodiments, the depth of the BDTI structure in the second region is equal to only the height (vertical extent) of the lower portion. Considering the horizontal lower surface of the BDTI structure to be the bottom surface, the BDTI structure may have a bottom surface at three different depths. The first depth corresponds to the depth of the mouth etch and is the depth of the protruding portion. The second depth corresponds to the depth of the high aspect ratio etch and is the depth of the BDTI structure in the second region. The third depth corresponds to the combined depth of the mouth etch and the high aspect ratio etch and is the depth of the BDTI structure in the first region. In the second region, the BDTI structure may have a depth limit set to accommodate the floating diffusion region. In the first region, the BDTI structure may have a depth that exceeds the limit.

[0018] In some embodiments, the cut street is formed in combination with the mouth etching. The cut street thus formed may have the same height as the upper portion and may have the same depth as the protruding portion. Forming the cut street in combination with the mouth etching may eliminate the mask.

[0019] In some embodiments, an upper passivation layer is formed on the back side. The upper passivation layer may be silicon oxide (SiO) or some other transparent material with a relatively low refractive index. In some embodiments, an intermediate passivation layer is disposed between the upper passivation layer and the back side. The intermediate passivation layer is transparent and has a refractive index between the refractive index of the semiconductor substrate and the refractive index of the upper passivation layer. In some embodiments, the intermediate passivation is tantalum oxide (TaO). The intermediate passivation layer and the upper passivation layer are disposed between the light detector and the corresponding lens on the back side. One or both of the intermediate passivation layer and the upper passivation layer may enter the semiconductor substrate to form part of the BDTI structure. In some embodiments, the upper passivation layer provides a core fill for the BDTI structure. In some embodiments, a substrate-embedded metal grid is at the core of the BDTI structure.

[0020] In some embodiments, a high aspect ratio etch is performed first. In some embodiments, the high aspect ratio etch is of a type that forms a trench that narrows at the top to form a neck. The type of etch may allow the trench to have a higher aspect ratio than another type of etch that does not leave a neck at the top of the trench. The mouth etch removes the top of the BDTI trench, where the neck may otherwise remain. In such embodiments, the mouth etch may increase the depth of the BDTI trench to a limited extent.

[0021] In some embodiments, the mouth etch is performed first. Performing the mouth etch first makes the high aspect ratio etch and the mouth etch more additive in depth and produces a deeper BDTI trench. The high aspect ratio etch can be set to the highest aspect ratio at which the lower portion can be backfilled without voids. The depth of the mouth etch can then be adjusted so that the depth of the mouth etch plus the depth of the high aspect ratio etch reaches the desired overall BDTI trench depth. In some embodiments, a cut street is formed in conjunction with the mouth etch. If the mouth etch is performed first, the resulting cut street can be used to align the high aspect ratio etch. In some embodiments, a second region of the area directly above the floating diffusion region can be masked during the mouth etch, whereby the BDTI trench is shallower in the second region compared to the first region.

[0022] After forming the BDTI trench, the BDTI trench may be lined with a dielectric material. In some embodiments, the dielectric material is of a type that exhibits a fixed negative charge. One or more passivation layers may then be formed on the backside. The passivation layer may be much thicker than the dielectric liner. In some embodiments, each of the passivation layers has a thickness on the backside that is greater than the width of the BDTI trench. The passivation layer may be deposited using a non-conformal deposition process, whereby it is deposited thinner in the trench than it is deposited on the backside. In some embodiments, the passivation layer fills the trench. In some embodiments, the passivation layer is deposited without filling the trench. In the latter case, a metal may be subsequently deposited to complete the BDTI trench fill. Such a metal may provide a substrate-embedded metal grid that provides improved optical performance characteristics such as increased quantum efficiency and reduced crosstalk between photodetectors.

[0023] Figure 1 1 shows a cross section of an image sensor 100A according to some aspects of the present invention. Image sensor 100A can include a first semiconductor substrate 107 bonded to a second semiconductor substrate 111. First semiconductor substrate 107 has a front side 108, a back side 101, an image sensor region 114, and a peripheral region 112. Various structures such as scribe lines 103 and ground bars 141A can be formed in peripheral region 112. Photodetectors 126 and floating diffusion regions 123 can be disposed in image sensor region 114.

[0024] Photodetectors 126 may include photodiodes or the like and may be coupled to floating diffusion region 123 via transfer gate 122 formed on front side 108. There may be one floating diffusion region 123 for every four photodetectors 126. Alternatively, there may be one floating diffusion region 123 for each individual photodetector 126 of each pair of photodetectors 126. In addition to transfer gate 122, additional transistors may be associated with photodetectors 126. These additional transistors may include select gates, reset gates, and the like, and may be on first semiconductor substrate 107, on second semiconductor substrate 111, or on both.

[0025] Microlens 147 may be disposed directly above photodetector 126. When light travels from microlens 147 to photodetector 126, it passes through color filter 146, upper passivation layer 138, and middle passivation layer 137. Upper passivation layer 138 and middle passivation layer 137 suppress reflections. Composite grid 149 at the height of the color filter helps divide the light among photodetector 126. Composite grid 149 may include backside metal grid 141, dielectric grid 142, and hard mask grid 143. Encapsulation layer 145 may extend over composite grid 149.

[0026] BDTI structure 134A is disposed directly below composite grid 149 and extends through backside 101 into first semiconductor substrate 107 to laterally surround photodetector 126. BDTI structure 134A includes segments 135 disposed between adjacent photodetectors 126. Dielectric liner 136 separates core 139A of BDTI structure 134A from first semiconductor substrate 107. All or part of core 139A may be provided by portions of intermediate passivation layer 137 and / or upper passivation layer 138 that descend into first semiconductor substrate 107 within segments 135. It should be appreciated that the illustration exaggerates the size of BDTI structure 134A compared to the size of photodetector 126 in order to depict the details of BDTI structure 134A. In some embodiments, the size of BDTI structure 134A is about 120 nanometers or less.

[0027] BDTI structure 134A extends into first semiconductor substrate 107 within a distance D1 to front side 108. In some embodiments, distance D1 is in a range from zero to about 1.5 microns. In some embodiments, distance D1 is in a range from 0.5 microns to about 1 micron. Having BDTI structure 134A close to front side 108 reduces crosstalk between photodetectors 126. Spacing BDTI structure 134A apart from front side 108 allows structures such as floating diffusion region 123 to be formed directly below segment 135.

[0028] First semiconductor substrate 107 has a thickness T1 suitable for light detector 126. In some embodiments, thickness T1 is in a range of about 2 microns to about 5 microns. In some embodiments, thickness T1 is in a range of about 3 microns to about 3.5 microns. In some embodiments, BDTI structure 134A extends into first semiconductor substrate 107 to a depth D2 in a range of about 2 microns to about 5 microns. In some embodiments, depth D2 is in a range of about 2.5 microns to about 4 microns.

[0029] Segment 135 includes an upper portion 132 and a lower portion 133. The step change from width W1 to width W2 occurs between upper portion 132 and lower portion 133. In some embodiments, width W2 is in a range of about 50 nanometers to about 200 nanometers. In some embodiments, width W2 is in a range of about 80 nanometers to about 120 nanometers. In some embodiments, width W1 is at least about 50% greater than width W2. In some embodiments, width W1 is at least about twice as great as width W2.

[0030] The first semiconductor substrate 107 forms a protruding portion 131 in which a step change in width occurs. The lower portion 133 has a higher aspect ratio than the upper portion 132. In some embodiments, the aspect ratio of the lower portion 133 is in a range from about 10:1 to about 25:1. In some embodiments, the aspect ratio of the lower portion 133 is not more than about 16:1. If the aspect ratio of the lower portion 133 is greater than about 16:1, it may be difficult to fill the lower portion 133 without leaving a void therein. For example, if the width W2 is 120 nanometers and the height H1 of the lower portion is about 2 micrometers or greater than 2 micrometers, it may be difficult to fill the lower portion 133.

[0031] In some embodiments, the height H1 of the lower portion 133 is in the range of about 1 micron to about 3 microns. In some embodiments, the height H1 is in the range of about 1.5 microns to about 2.5 microns. In some embodiments, the height H2 of the upper portion is in the range of about 0.4 microns to about 2 microns. In some embodiments, the height H2 is in the range of about 0.5 microns to about 1.5 microns.

[0032] The dielectric liner 136 is transparent and includes one or more any suitable dielectric layers. In some embodiments, the dielectric liner 136 includes one or more dielectric layers that exhibit a fixed negative charge. Examples of dielectrics that exhibit a fixed negative charge include hafnium oxide (HfO), aluminum oxide (AlO), and the like. In some embodiments, the dielectric liner 136 includes a first dielectric layer and a second dielectric layer. For example, the first dielectric layer may be aluminum oxide (AlO) or the like, and the second dielectric layer may be hafnium oxide (HfO) or the like. In some embodiments, the first dielectric layer has a thickness in a range of about 20 angstroms to about 100 angstroms, such as about 40 angstroms. In some embodiments, the second dielectric layer has a thickness in a range of about 30 angstroms to about 200 angstroms, such as about 60 angstroms. In some embodiments, the dielectric liner 136 as a whole has a thickness in a range of about 50 angstroms to about 200 angstroms, such as about 100 angstroms.

[0033] The middle passivation layer 137 and the upper passivation layer 138 are much thicker than the dielectric liner 136. In some embodiments, their thicknesses are each greater than the width W2. In some embodiments, their thicknesses are each greater than the width W1. The upper passivation layer 138 can be any suitable material that is transparent and has a relatively low refractive index. Suitable materials include silicon oxide (SiO), silicon nitride (SiN), hafnium oxide (HfO), titanium oxide (TiO), and the like. In some embodiments, the upper passivation layer 138 is or includes silicon oxide (SiO) or the like. In some embodiments, the upper passivation layer 138 has a thickness in the range of about 300 angstroms to about 2500 angstroms, for example, about 500 angstroms.

[0034] Intermediate passivation layer 137 is a transparent material having a refractive index between the refractive index of upper passivation layer 138 and the refractive index of first semiconductor substrate 107. Suitable materials include silicon nitride (SiN), hafnium oxide (HfO), aluminum oxide (AlO), titanium oxide (TiO), and the like. In some embodiments, intermediate passivation layer 137 is tantalum oxide (TaO) or the like. In some embodiments, intermediate passivation layer 137 has a thickness in a range of about 300 angstroms to about 2500 angstroms, for example, about 500 angstroms. The thickness of intermediate passivation layer 137 and upper passivation layer 138 may vary in relation to the wavelength of light targeted by image sensor 100A.

[0035] Figure 2 FIG. 1 shows a cross-sectional view of an image sensor 100B including a BDTI structure 134B. The image sensor 100B is similar to Figure 1 100B, except that image sensor 100B has a BDTI structure 134B including substrate-embedded metal grid 201 as part of its core 139B. Dielectric layer 203 separates substrate-embedded metal grid 201 from backside metal grid 141. Dielectric layer 203 is transparent and may be directly above upper passivation layer 138. In some embodiments, dielectric layer 203 has the same composition as upper passivation layer 138. In some embodiments, substrate-embedded metal grid 201 is biased to a negative voltage. The negative voltage may be applied from a source within image sensor 100B or from an external source using a contact pad. Alternatively, substrate-embedded metal grid 201 may be grounded.

[0036] The substrate embedded metal grid 201 can be any suitable metal. In some embodiments, the substrate embedded metal grid 201 is or includes aluminum (Al), tungsten (W), or the like. Aluminum and tungsten have the advantage of being able to be deposited in high aspect ratio openings. In some embodiments, the substrate embedded metal grid 201 includes tungsten (W) or the like. Tungsten (W) is particularly suitable for deposition in high aspect ratio openings. In some embodiments, the substrate embedded metal grid 201 includes aluminum (Al) or the like. Aluminum (Al) has the advantage of high electrical conductivity.

[0037] Figure 3 Shows something like Figure 1FIG. 1 is a cross-sectional view of image sensor 100C of image sensor 100A, except that scribe line 103 has a depth D2 that is the same as height H2 of upper portion 132 and scribe line 103 has the same composition as BDTI structure 134A. The composition includes dielectric liner 136 and core 139A. In this example, core 139A includes middle passivation layer 137 and upper passivation layer 138. These layers may have different thicknesses in scribe line 103 than in BDTI structure 134A due to the trench width affecting the deposition rate.

[0038] Figure 4 Shown to be similar in most respects to Figure 3 The image sensor 100D has a cross-sectional view of the image sensor 100C. The image sensor 100D has a similar Figure 3 134D of the BDTI structure 134C, except that in the first region 401, the BDTI structure 134D is located within a distance D3 of the front side 108 and maintains a larger distance D4 from the front side 108 in the second region 403. The floating diffusion region 123 is in the second region 403, and the BDTI structure 134D lacks the upper portion 132 in the second region 403. The difference between the distance D4 and the distance D3 is substantially equal to the height H2 of the upper portion 132.

[0039] Figure 4A Show focus on Figure 4 A plan view of the image sensor 100D on the plane AA'. Figure 4A As shown, the BDTI structure 134D is located in the first region 401 of the image sensor region 114 (see Figure 4 ) but not in second regions 403. One of second regions 403 is marked to the right of image sensor region 114. In second region 403, BDTI structure 134D is too shallow to reach plane AA'. The locations of four transfer gates 122 associated with one floating diffusion region 123 and respective photodetectors 126 are marked to the left of image sensor region 114. Slice streets 103 are depicted as rectangles.

[0040] Figures 5 to 17 FIG. 1 is a cross-sectional view illustrating a method of forming an image sensor 100A according to the present invention. Figures 5 to 17 The method is described with reference to various embodiments, but it should be understood that Figures 5 to 17 The structures depicted in the diagram are not limited to the method but can be separated from the method. Figures 5 to 17 Although described as a series of actions, it should be understood that in other embodiments, the order of the actions may be changed. Figures 5 to 17Although a particular set of actions are shown and described, in other embodiments, some of the actions shown and / or described may be omitted. Additionally, actions not shown and / or described may be included in other embodiments. Figures 5 to 17 The method is described in terms of forming image sensor 100A, but the method and its variations may be used to form other image sensors according to the present invention.

[0041] As Figure 5 5. As shown in cross-sectional view 500 of , the method may begin by bonding together a partially fabricated image sensor 501 and a second IC device 503. Each of image sensor 501 and second IC device 503 may have been subjected to front-end-of-line (FEOL) and back-end-of-line (BEOL) processing. In image sensor 501, FEOL processing provides photodetector 126, floating diffusion region 123, and transfer gate 122. BEOL processing provides first metal interconnect 109. In second IC device 503, FEOL processing provides logic gate 113 and similar structures, and BEOL processing provides second metal interconnect 110. Bonding occurs between first metal interconnect 109 and second metal interconnect 110. The bonding process may be fusion bonding, hybrid bonding, the like, or some other suitable bonding process.

[0042] Each of the first semiconductor substrate 107 and the second semiconductor substrate 111 may be or include a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, the like, or some other suitable semiconductor substrate. Each of the first interlayer dielectric 120 and the second interlayer dielectric 117 may be or include silicon dioxide (SiO2), a low-K dielectric, an ultra-low-K dielectric, or the like. The first conductive line 121, the first via 119, the second conductive line 115, and the second via 118 may be or include copper (Cu), aluminum (Al), the like, or some other suitable metal. The light detector 126 may be any type of light detector. In some embodiments, the light detector 126 includes a photodiode. In some embodiments, light detector 126 is an active pixel sensor having a fixed photodiode.

[0043] Figure 6 The cross-sectional view 600 of FIG. 5 shows the partially fabricated image sensor 501 and the second IC device 503 after bonding. The method may continue by thinning the first semiconductor substrate 105, such as by Figure 7 is shown in cross-sectional view 700 .

[0044] As Figure 8 As shown in the cross-sectional view 800 of FIG. 8 , a mask 801 may be formed in the back side 101 of the first semiconductor substrate 107 and used to etch the scribe line 103 (see FIG. 8 ). Figure 1 ) of the cutting groove 803. Fig. 8A A mask 801 is shown. Fig. 8A As shown in FIG. 8 , the mask 801 has a gap 805 corresponding to the saw groove 803. Fig. 9 As shown in cross-sectional view 900 of , mask 801 may be stripped and street trenches 803 may be filled to provide street 103. Filling may involve depositing a fill material followed by planarization. The deposition process may be, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), the like, or some other suitable process. The planarization process may be chemical mechanical polishing (CMP), the like, of some other suitable process. The fill material may be silicon oxide (SiO), the like, or some other suitable material.

[0045] As Fig.10 As shown in the cross-sectional view 1000 of , a mask 1001 may be formed in the first semiconductor substrate 107 and used to etch a high aspect ratio trench 1003 . Fig. 10A A plan view of a mask 1001 is shown. The mask 1001 has slits 1007 forming a grid pattern corresponding to high aspect ratio trenches 1003. The high aspect ratio trenches 1003 may have a neck 1005 close to the back side 101. Due to the neck 1005, the width W4 of the high aspect ratio trench 1003 at the top is smaller than the width W2 a short distance below the top. In some embodiments, the etching process includes plasma etching or the like.

[0046] In some embodiments, the etching process is a multi-step etching process in which trenches are formed in segments. Forming a segment includes etching to a first depth followed by depositing a protective layer on the trench sidewalls. The protective layer may be, for example, an oxide or carbide. The etching for the next segment breaks through the protective layer at the bottom of the trench. The protective layer reduces lateral etching and trench widening in the upper segment as the lower segment is formed. This type of etching process can form a higher aspect ratio trench than a single step etching process, but the etching conditions tend to leave a neck 1005 at the top.

[0047] As Fig.11 As shown in the cross-sectional view 1100 of , the mask 1101 is formed to etch the trench mouth 1103 adjacent to the high aspect ratio trench 1003 . Fig.11A1 shows a plan view of mask 1101. Mask 1101 has slits 1107. Slits 1107 have the same Fig. 10A ) has the same grid pattern but wider. Etching the groove mouth 1103 removes the neck 1005 (see Fig.10 ). Etching the trench mouth 1103 may also slightly deepen the high aspect ratio trench 1003. The etching process may be plasma etching, the like, or any other suitable etching process.

[0048] As Fig.12 As shown in the cross-sectional view 1200 of FIG. 1 , the dielectric liner 136, the middle passivation layer 137, and the upper passivation layer 138 may be deposited in sequence. These layers may fill the high aspect ratio trench 1003 and the trench mouth 1103 to form the BDTI structure 134A. The dielectric liner 136 may include one or more layers that may be deposited by a conformal deposition process. The conformal deposition process may be PVD, CVD, atomic layer deposition (ALD), the like, or other suitable processes.

[0049] The middle passivation layer 137 and the upper passivation layer 138 may be deposited by a non-conformal deposition process, whereby these layers are deposited thicker on the back side 101 than in the high aspect ratio trench 1003. The deposition process may include PVD, CVD, the like, or any other suitable process. In some embodiments, the upper passivation layer 138 is deposited to a thickness in a range of about 500 angstroms to about 2000 angstroms, for example about 1000 angstroms.

[0050] As Fig.13 As shown in the cross-sectional view 1300 of , a planarization process may be performed to thin and planarize the upper passivation layer 138. The planarization process may be CMP, the like, or some other suitable process.

[0051] As Fig.14 As shown in the cross-sectional view 1400 of FIG. 1 , a mask 1401 may be formed in the first semiconductor substrate 107 within the peripheral region 112 and used to etch the grounding bar openings 1403. The etching process may be plasma etching or the like. After etching, the mask 1401 may be stripped.

[0052] As Fig.15 As shown in cross-sectional view 1500 of FIG. 1 , the composite grid stack 1509 may be deposited on a Fig.141400 . Composite grid stack 1509 may include metal layer 1501, dielectric layer 1503, and hard mask layer 1505. Metal layer 1501 fills ground bar opening 141A to form ground bar 141A. Metal layer 1501 may include any suitable metal or combination of metals. In some embodiments, metal layer 1501 is or includes tungsten (W) or the like. In some embodiments, metal layer 1501 includes a liner of titanium nitride (TiN), tantalum nitride (TaN), or the like. Dielectric layer 1503 may be silicon oxide (SiO), the like, or any suitable dielectric. Hard mask layer 1505 may be a nitride, a carbide, the like, a combination thereof, or any other suitable hard mask material. These layers may be deposited by ALD, CVD, PVD, electroplating, electroless plating, the like, or any other suitable process combination.

[0053] As Fig.16 16, mask 1601 may be formed to etch composite grid 149 from composite grid stack 1509. The etch removes the composite grid from above photodetector 126. The etch forms backside metal grid 141 from metal layer 1501, dielectric grid 142 from dielectric layer 1503, and hard mask grid 143 from hard mask layer 1505. After this etch, mask 1601 may be stripped.

[0054] As Fig.17 As shown in the cross-sectional view 1700 of FIG. 1 , the encapsulation layer 145 may be formed on a Fig.16 1600. Encapsulation layer 145 may be an oxide, the like, or some other suitable dielectric. Color filters 146 may then be formed within composite grid 149 above photodetectors 126. Microlenses 147 may be formed above color filters 146 to create an image sensor, such as Figure 1 Image sensor 100A.

[0055] FIG. 18A to FIG. 18B Show Figures 5 to 17 can be used to generate Figure 2 A variation of the process of the image sensor 100B. Fig.18A 1800, in this variation, the process of depositing the middle passivation layer 137 and the upper passivation layer is performed in such a way that the high aspect ratio trench 1003 and the trench mouth 1103 are not filled by these layers. The filling process is completed by depositing metal 1801. The metal 1801 can be deposited by PVD, CVD, ALD, electroplating, electroless plating, the like, or any other suitable process. The process can be suitable for filling the high aspect ratio opening without creating voids.

[0056] As Fig.18B As shown in the cross-sectional view 1820 of , a planarization process may be performed to define the substrate embedded metal grid 201 from the metal 1801. The planarization process may be CMP, the like, or some other suitable process. The planarization process may thin the upper passivation layer 138 and produce the BDTI structure 134B. After planarization, the dielectric layer 203 may be formed by CVD, PVD, ALD, the like, or some other suitable deposition process.

[0057] Figure 19 to Figure 20 Show Figures 5 to 17 can be used to generate Figure 3 A variation of the process of image sensor 100C. Fig.19 and Fig. 20 Process replacement Figures 8 to 11 process. Fig.19 As shown in the cross-sectional view 1900 of , the mask 1901 is formed to etch the trench mouth 1103 and the scribe line trench 803 . Fig.19A A plan view of mask 1901 is shown.

[0058] As Fig. 20 As shown in the cross-sectional view 2000 of , after the mask 1901 is stripped, the mask 2001 is formed to etch the high aspect ratio trench 1003 through the trench mouth 1103 . Fig. 20A A plan view of mask 2001 is shown. The etching process may be selected so as not to form a neck 1005 at the top of high aspect ratio trench 1003 (see Fig.10 After the mask 2001 is stripped, the process steps may be continued, such as Figures 12 to 17 As shown in the figure, Figure 3 Image sensor 100C.

[0059] Figure 21 to Figure 22 Show Figure 19 to Figure 20 can be used to generate Figure 4 A variant of the image sensor 100D process. This variant uses Fig.21A The mask 2101 shown in FIG. 1 etches the groove opening 1103. The mask 2101 is similar to Fig.19A , except that mask 2101 includes block 2103. Fig.21 As shown in the cross-sectional view 2100 of , the block 2103 prevents the groove mouth 1103 from being formed in the second region 403 .

[0060] As Fig. 22 As shown in the cross-sectional view 2200 of FIG. Fig. 20A), the high aspect ratio trench 1003A formed in the first region 401 is deeper than the high aspect ratio trench 1003B formed in the second region 403. Figures 12 to 17 The process shown in the figure continues to produce Figure 4 Image sensor 100D.

[0061] Fig.23 A flow chart of a process 2300 for forming an image sensor according to the present invention is presented. Fig.23 The process 2300 is shown and described as a series of actions or events, it will be appreciated that the illustrated order of such actions or events should not be interpreted in a limiting sense. For example, in addition to the actions or events shown and / or described herein, some actions may occur in a different order and / or simultaneously with other actions or events. In addition, not all of the illustrated actions are required to implement one or more aspects or embodiments described herein, and one or more of the actions depicted herein may be performed in one or more separate actions and / or stages.

[0062] The process 2300 begins with act 2301, which is FEOL processing and BEOL processing. The FEOL processing forms a photodetector in a first semiconductor substrate. The BEOL processing forms a metal interconnect on the first semiconductor substrate. Figure 5 Image sensor 501 provides an example of the resulting structure.

[0063] Action 2303 is to bond the first semiconductor substrate to the second semiconductor substrate. Figure 5 and Figure 6 This process is shown. The process continues with act 2305 by thinning the first semiconductor substrate from the back side. Figure 7 An example is provided. The second semiconductor substrate is provided with structural integrity through a thinning process.

[0064] Action 2307 is etching a high aspect ratio trench in the backside of the BDTI structure. Fig.10 An example is provided in cross-sectional view 1000 of FIG. 1. A trench extends into the semiconductor substrate in the image sensor region to laterally surround the light detector.

[0065] Action 2309 is etching to create a trench mouth. At the top of the high aspect ratio trench formed in action 2307, the trench mouth is a widened area. Fig.11 An example is provided in cross-sectional view 1100 .

[0066] Action 2311 is to form a dielectric liner of the BDTI trench. Action 2313 is to fill the BDTI trench. Fig.12 An example is provided in cross-sectional view 1200 . Fig.18AAnother example is provided by the cross-sectional view 1800 of . The trench fill may include one or more passivation layers and optionally a metal layer that forms a metal grid embedded in the substrate and forming part of the BDTI structure.

[0067] Action 2315 is flattening. Fig.13 A cross-sectional view 1300 and Fig.18B An example is provided in the cross-sectional view 1820 of FIG. 2317 . The composite grid, color filters, and lenses are formed on the back side. Figures 15 to 17 The cross-sectional views 1500 to 1700 together with Figure 1 Provide examples.

[0068] Fig.24 Provides similar Fig.23 Flowchart of process 2400 of process 2300, except that act 2309 (etching the trench mouth) is performed before act 2311 (etching the high aspect ratio trench). The trenches for the saw streets can be formed by etching that forms the trench mouths. Fig.19 and Fig.21 Cross-sectional views 1900 and 2100 of FIG. 1 provide examples. The trench mouth may be formed only in a portion of the region where the BDTI structure is formed. Fig.21 An example is provided in the cross-sectional view 2100 of FIG. The BDTI structure will be shallower in the region where the mouth of the trench is not formed. Fig. 22 An example is provided in cross-sectional view 2200 .

[0069] Some aspects of the present invention are directed to an image sensor including a photodetector within a semiconductor substrate. A backside deep trench isolation structure extends into the backside of the semiconductor substrate to laterally surround the photodetector. In a first region, the backside deep trench isolation structure exhibits a step change in width within the semiconductor substrate. In some embodiments, in a second region, the backside deep trench isolation structure is shallower than in the first region and does not exhibit a step change in width. In some embodiments, the image sensor includes a scribe line having a depth corresponding to a depth at which the step change in width occurs. In some embodiments, one or more passivation layers include an upper passivation layer and an intermediate passivation layer. The intermediate passivation layer is located between the upper passivation layer and the backside and has a refractive index between the refractive index of the semiconductor substrate and the refractive index of the upper passivation layer. In some embodiments, the upper passivation layer descends into the semiconductor substrate to form a portion of the backside deep trench isolation structure. In some embodiments, a dielectric liner for the backside deep trench isolation structure includes one or more material layers exhibiting a fixed negative charge. In some embodiments, the upper passivation layer descends into the semiconductor substrate to form a core of the backside deep trench isolation structure. In some embodiments, the intermediate passivation layer includes tantalum oxide (TaO). In some embodiments, the backside deep trench isolation structure includes a substrate-embedded metal grid.

[0070] Some aspects of the present invention are directed to an image sensor including a photodetector in a semiconductor substrate. A backside deep trench isolation structure extends into the backside of the semiconductor substrate to laterally surround the photodetector. In a first region, the backside deep trench isolation structure exhibits an abrupt narrowing including a discontinuous variation in the width of a BDTI structure relative to the depth of the BDTI structure within the semiconductor substrate and at a height above the bottom of the BDTI structure.

[0071] Some aspects of the present invention are directed to an image sensor comprising photodetectors within a semiconductor substrate and a backside deep trench isolation structure extending into the backside between the photodetectors. In a first region, the backside deep trench isolation structure has an upper portion and a lower portion both within the semiconductor substrate. The lower portion is narrower than the upper portion and has a higher aspect ratio. The semiconductor substrate forms a protruding portion at a junction between the upper portion and the lower portion. In some embodiments, within the first region, the backside isolation structure continuously narrows into the semiconductor substrate at a greater depth. In some embodiments, an upper passivation layer and an intermediate passivation layer are on the backside. The intermediate passivation layer has a refractive index between the refractive index of the semiconductor substrate and the refractive index of the upper passivation layer. The upper passivation layer descends within the backside isolation structure to a depth below the upper portion. In some embodiments, the image sensor comprises a scribe line having a depth equal to the depth of the protruding portion.

[0072] Some aspects of the present invention are directed to a method comprising providing a semiconductor substrate comprising an array of photodetectors in an image sensor region. A trench is formed in a back side of the semiconductor substrate using both a high aspect ratio etch and a mouth etch. The high aspect ratio etch comprises etching through a first gap having a first width. The mouth etch comprises etching through a corresponding second gap having a second width. The second width is greater than the first width. The trench is filled to form a back side deep trench isolation structure. In some embodiments, there is an area shielded during the mouth etch, and the trench is formed in the area by the high aspect ratio etch. In some embodiments, the mouth etch forms trenches in the peripheral area and fills these peripheral area trenches to provide a cutting path. In some embodiments, the high aspect ratio etch is performed before the mouth etch. In some embodiments, the mouth etch is performed before the high aspect ratio etch. In some embodiments, filling the trench comprises depositing an intermediate passivation layer and an upper passivation layer both above the intermediate passivation. The intermediate passivation has a refractive index between the refractive index of the semiconductor substrate and the refractive index of the upper passivation layer. In some embodiments, filling the trench comprises depositing a metal.

[0073] In some embodiments, an image sensor includes: a semiconductor substrate having a front side and a back side; a photodetector located in the semiconductor substrate; one or more passivation layers located on the back side; and a backside deep trench isolation (BDTI) structure extending into the back side to laterally surround the photodetector, wherein in a first region, the BDTI structure exhibits an abrupt narrowing corresponding to a discontinuous change in a width of the BDTI structure relative to a depth of the BDTI structure at a height within the semiconductor substrate and above a bottom of the BDTI structure.

[0074] In some embodiments, in the second region, the BDTI structure is shallower than in the first region and does not exhibit the abrupt narrowing. In some embodiments, a scribe line having a depth is also included, wherein the abrupt narrowing of the width occurs at the depth. In some embodiments, the one or more passivation layers include an upper passivation layer and an intermediate passivation layer; and the intermediate passivation layer is located between the upper passivation layer and the back side and has a refractive index between the refractive index of the semiconductor substrate and the refractive index of the upper passivation layer. In some embodiments, the upper passivation layer descends into the semiconductor substrate to form a portion of the BDTI structure. In some embodiments, a dielectric liner for the BDTI structure is also included, wherein the dielectric liner is one or more material layers exhibiting a fixed negative charge. In some embodiments, the upper passivation layer descends into the semiconductor substrate to form a core of the BDTI structure. In some embodiments, the intermediate passivation layer includes tantalum oxide (TaO). In some embodiments, the BDTI structure includes a substrate-embedded metal grid.

[0075] In some embodiments, an image sensor includes a semiconductor substrate including a front side and a back side; photodetectors arrayed in the semiconductor substrate; and a backside isolation structure extending into the back side between the photodetectors, wherein in a first region, the backside isolation structure has an upper portion and a lower portion both located in the semiconductor substrate; wherein the lower portion is narrower than the upper portion and has a higher aspect ratio; and the semiconductor substrate forms a protrusion at a junction between the upper portion and the lower portion.

[0076] In some embodiments, within the first region, the backside isolation structure continuously narrows into the semiconductor substrate at a greater depth. In some embodiments, it also includes: an upper passivation layer located on the backside; and an intermediate passivation layer located between the upper passivation layer and the backside, wherein the intermediate passivation layer has a refractive index between the refractive index of the semiconductor substrate and the refractive index of the upper passivation layer; wherein the upper passivation layer descends to a depth below the upper portion within the backside isolation structure. In some embodiments, it also includes a scribe line having a depth equal to the depth of the protruding portion.

[0077] In some embodiments, a method of forming an image sensor includes: providing a semiconductor substrate, the semiconductor substrate including a front side, a back side, an image sensor region, a peripheral region, and light detectors arrayed in the image sensor region; forming a trench, wherein in a first region, the trench is formed by both a high aspect ratio etch and a mouth etch, the high aspect ratio etch comprising etching through a first gap having a first width, and the mouth etch comprising etching through a second gap having a second width, wherein the second width is greater than the first width; and filling the trench to form a backside isolation structure.

[0078] In some embodiments, in the second region, the trench is formed by the high aspect ratio etch and shields the second region during the mouth etch. In some embodiments, the mouth etch forms a trench in the peripheral region, and the trench is filled to provide a saw road. In some embodiments, the high aspect ratio etch is performed before the mouth etch. In some embodiments, the mouth etch is performed before the high aspect ratio etch. In some embodiments, filling the trench includes depositing an intermediate passivation layer; filling the trench also includes depositing an upper passivation layer above the intermediate passivation layer; and the intermediate passivation layer has a refractive index between the refractive index of the semiconductor substrate and the refractive index of the upper passivation layer. In some embodiments, filling the trench also includes depositing a metal.

[0079] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present invention. Those skilled in the art will appreciate that they can readily use the present invention as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present invention, and that those skilled in the art may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. An image sensor, It is characterized in that include: A semiconductor substrate having a front side and a back side; a light detector located in the semiconductor substrate; one or more passivation layers on the back side; as well as a backside deep trench isolation structure extending into the back side to laterally surround the photodetector, wherein in a first region, the backside deep trench isolation structure exhibits an abrupt narrowing corresponding to a discontinuous variation in a width of the backside deep trench isolation structure relative to a depth of the backside deep trench isolation structure at a height within the semiconductor substrate and above a bottom of the backside deep trench isolation structure.

2. The image sensor according to claim 1, It is characterized in that In the second region, the backside deep trench isolation structure is shallower than in the first region and does not exhibit the abrupt narrowing.

3. The image sensor according to claim 1, It is characterized in that Also included is a scribe line having a depth, wherein the abrupt narrowing of the width occurs at the depth.

4. The image sensor according to claim 1, Features: The one or more passivation layers include an upper passivation layer and an intermediate passivation layer; and The intermediate passivation layer is located between the upper passivation layer and the back side and has a refractive index between a refractive index of the semiconductor substrate and a refractive index of the upper passivation layer.

5. The image sensor according to claim 4, It is characterized in that The upper passivation layer is lowered into the semiconductor substrate to form a portion of the backside deep trench isolation structure.

6. The image sensor according to claim 4, It is characterized in that The upper passivation layer is lowered into the semiconductor substrate to form a core of the backside deep trench isolation structure.

7. The image sensor according to claim 1, It is characterized in that The backside deep trench isolation structure includes a substrate embedded metal grid.

8. An image sensor, It is characterized in that include: A semiconductor substrate including a front side and a back side; Photodetectors are arrayed in the semiconductor substrate; as well as a backside isolation structure extending into the backside between the photodetectors, wherein in a first region, the backside isolation structure has an upper portion and a lower portion both located within the semiconductor substrate; wherein the lower portion is narrower and has a higher aspect ratio than the upper portion; as well as The semiconductor substrate forms a protruding portion at a junction between the upper portion and the lower portion.

9. The image sensor according to claim 8, It is characterized in that In the first region, the backside isolation structure continuously narrows into the semiconductor substrate at a greater depth.

10. The image sensor according to claim 8, It is characterized in that Also included is a scribe line having a depth equal to the depth of the protruding portion.

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