Gate driver, sealing chip and control system

Abstract

The utility model provides a gate driver, a sealing chip and a control system, the gate driver comprises a voltage division driving circuit, the voltage division driving circuit comprises at least one voltage division driving module, and the voltage division driving module comprises a voltage division sampling unit and an output driving unit; the partial voltage sampling unit is used for sampling a back electromotive force signal from a rear-stage bridge type structure to obtain a primary sampling signal; and the output driving unit is connected with the output end of the voltage-dividing sampling unit and is used for increasing the driving capability of the primary sampling signal to obtain a secondary sampling signal. According to the utility model, the problem that the conversion rate of the ADC is limited when the counter electromotive force of the motor is sampled through the ADC in the prior art is solved.

Description

Technical Field

[0001] The utility model relates to the technical field of power electronics, in particular to a gate driver, a sealed chip and a control system. Background Art

[0002] In high-voltage applications of motors, a high back-electromotive force is generated when the motor is running. When the high back-electromotive force is sampled by the ADC (analog-to-digital converter) of the MCU (microprocessing unit), an external voltage divider circuit is usually required to match the voltage specification of the ADC. Since the voltage divider resistor is at the KΩ level and has a large impedance, the current in the circuit after voltage division is low, and the driving ability to the load is reduced, resulting in a slower charging and discharging speed of the ADC sampling capacitor, which limits the ADC conversion rate and makes it impossible to fully exert its performance. Therefore, how to solve the limited ADC conversion rate is a technical problem that technicians in this field are eager to solve.

[0003] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Utility Model Content

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a gate driver, a sealed chip and a control system, which solve the problem of limited ADC conversion rate when sampling the back electromotive force of the motor through ADC in the prior art.

[0005] In order to achieve the above-mentioned object and other related objects, the utility model provides a gate driver, the gate driver comprising:

[0006] A voltage-dividing driving circuit, wherein the voltage-dividing driving circuit comprises at least one voltage-dividing driving module, and the voltage-dividing driving module comprises a voltage-dividing sampling unit and an output driving unit;

[0007] The voltage-dividing sampling unit is used to sample the back electromotive force signal from the subsequent bridge structure to obtain a primary sampling signal;

[0008] The output driving unit is connected to the output end of the voltage-dividing sampling unit, and is used to increase the driving capability of the primary sampling signal to obtain a secondary sampling signal.

[0009] Optionally, the voltage-dividing driving circuit includes three voltage-dividing driving modules, which correspond one-to-one to the U-phase bridge structure, the V-phase bridge structure and the W-phase bridge structure of the subsequent stage respectively.

[0010] Optionally, the voltage division sampling unit includes a first resistor and a second resistor, the first end of the first resistor is connected to the back electromotive force signal, the second end is connected to the first end of the second resistor and outputs the primary sampling signal, and the second end of the second resistor is connected to the reference ground.

[0011] Optionally, the output driving unit comprises an operational amplifier, a non-inverting input terminal is connected to the primary sampling signal, an inverting input terminal is connected to its output terminal, and the output terminal outputs the secondary sampling signal.

[0012] Optionally, the gate driver further includes:

[0013] A gate driving circuit, wherein the gate driving circuit comprises at least one gate driving module, and the gate driving module comprises a signal input unit, a high-side driving unit, and a low-side driving unit;

[0014] The signal input unit is used to obtain a first intermediate signal according to a received high-side input signal and to obtain a second intermediate signal according to a received low-side input signal;

[0015] The high-side driving unit is connected to the signal input unit, and is used to obtain a floating power supply signal, a floating ground signal and a high-side gate driving signal according to the first intermediate signal;

[0016] The low-side driving unit is connected to the signal input unit, and is used to obtain a low-side gate driving signal according to the second intermediate signal;

[0017] The voltage-dividing sampling unit and the high-side driving unit time-share a floating ground signal port, and the voltage-dividing sampling unit samples the back electromotive force signal through the floating ground signal port.

[0018] Optionally, when the voltage-dividing driving circuit includes three voltage-dividing driving modules, the gate driving circuit includes three gate driving modules, which correspond one-to-one to the U-phase bridge structure, the V-phase bridge structure and the W-phase bridge structure of the subsequent stage respectively.

[0019] The utility model also provides a sealed chip, the sealed chip comprising:

[0020] The gate driver and microprocessor unit as described above;

[0021] The gate driver is used to obtain a secondary sampling signal according to the sampled back electromotive force signal;

[0022] The microprocessing unit comprises an analog-to-digital converter, and the analog-to-digital converter is used to sample the secondary sampling signal to obtain a detection signal.

[0023] Optionally, when the gate driver also includes a gate drive circuit, the gate driver is also used to obtain a floating power supply signal, a floating ground signal, a high-side gate drive signal and a low-side gate drive signal according to the high-side input signal and the low-side input signal. At this time, the microprocessing unit also includes a microprocessor for obtaining the high-side input signal and the low-side input signal according to the detection signal.

[0024] The utility model also provides a control system, the control system comprising:

[0025] As described above, the packaged chip, bridge structure and load, the packaged chip is connected to the load through the bridge structure, the load is driven to operate by controlling the on-off of the power tube in the bridge structure, and the back electromotive force signal is sampled during the operation of the load to feedback control the load.

[0026] Optionally, in the sealed chip, the voltage divider drive circuit in the gate driver includes three voltage divider drive modules and the gate drive circuit includes three gate drive modules; the bridge structure includes a U-phase bridge structure, a V-phase bridge structure and a W-phase bridge structure; and the load includes a motor.

[0027] As described above, the utility model provides a gate driver, a sealed chip and a control system, wherein a voltage divider driving circuit is integrated in the gate driver, and a higher back electromotive force signal is sampled through a resistor voltage divider, so that the voltage-divided signal can meet the voltage specification of the ADC in the subsequent MCU, and the driving capability of the voltage-divided signal is improved through a voltage follower formed by an operational amplifier, thereby accelerating the charging and discharging speed of the ADC sampling capacitor, and improving the conversion rate of the ADC, so that the full performance can be exerted, fast and accurate back electromotive force detection can be achieved, and the stability of load operation can be improved; compared with existing gate drivers, the gate driver of the utility model has stronger market competitiveness. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a schematic diagram of the structure of the gate driver in the first embodiment.

[0029] Figure 2 It is a schematic diagram of the structure of the voltage-dividing driving module in the first embodiment.

[0030] Figure 3 It is a schematic diagram of the structure of the gate driver in the second embodiment.

[0031] Figure 4 It is a schematic diagram of the structure of the voltage-dividing driving module in the second embodiment.

[0032] Figure 5 It is a schematic diagram of the structure of the sealed chip in the third embodiment.

[0033] Figure 6 It is a schematic diagram of the structure of the micro-processing unit in the third embodiment.

[0034] Figure 7 It is a schematic diagram of the structure of the sealed chip in the fourth embodiment.

[0035] Figure 8 It is a schematic diagram of the structure of the micro-processing unit in the fourth embodiment.

[0036] Fig. 9 It shows a schematic diagram of the structure of the control system in the fifth embodiment.

[0037] Fig.10 It shows a schematic diagram of the structure of the control system in the sixth embodiment.

[0038] Component number description

[0039] 10. Chip Sealing

[0040] 100 Gate Driver

[0041] 110 voltage divider drive circuit

[0042] 111 voltage divider drive module

[0043] 111a Voltage Divider Sampling Unit

[0044] 111b Output driver unit

[0045] 120 Gate drive circuit

[0046] 121 Gate drive module

[0047] 121a Signal input unit

[0048] 121b High-side driver

[0049] 121c Low-side driver

[0050] 200 microprocessor units

[0051] 210 Analog-to-digital converter

[0052] 220 microprocessor

[0053] 20 Bridge structure

[0054] 20a U-phase bridge structure

[0055] 20b V-phase bridge structure

[0056] 20c W-phase bridge structure

[0057] 30 Load DETAILED DESCRIPTION

[0058] The following is an explanation of the implementation of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0059] See also Figures 1 to 10 It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings in this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the utility model, so they have no substantial technical significance. Any modification of the structure, change in the proportion relationship, or adjustment of the size should still fall within the scope of the technical content disclosed by the utility model without affecting the effects and purposes that can be achieved by the utility model. At the same time, the terms such as "upper", "lower", "left", "right", "middle" and "one" quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the utility model. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of the utility model without substantially changing the technical content.

[0060] Embodiment 1

[0061] like Figure 1 and Figure 2 As shown, this embodiment provides a gate driver 100 , including a voltage-dividing driving circuit 110 , and further including a gate driving circuit 120 .

[0062] The voltage-dividing driving circuit 110 includes at least one voltage-dividing driving module 111. In this embodiment, the voltage-dividing driving circuit 110 includes a voltage-dividing driving module 111, such as Figure 1 The voltage division driving module 111 includes a voltage division sampling unit 111a and an output driving unit 111b.

[0063] The voltage-dividing sampling unit 111 a is used to sample the back electromotive force signal of the load in the subsequent bridge structure to obtain a primary sampling signal.

[0064] In one embodiment, the voltage-dividing sampling unit 111a includes a first resistor R1 and a second resistor R2, wherein a first end of the first resistor R1 is connected to the back electromotive force signal, a second end of the first resistor R1 is connected to a first end of the second resistor R2 and outputs a primary sampling signal, and a second end of the second resistor R2 is connected to a reference ground.

[0065] In practical applications, the first resistor R1 and the second resistor R2 can be implemented by a single resistor, or by at least two resistors connected in series, in parallel, or in series-parallel. This has no substantial impact on this implementation, so no limitation is imposed on this.

[0066] The output driving unit 111 b is connected to the output end of the voltage-dividing sampling unit 111 a and is used to increase the driving capability of the primary sampling signal to obtain a secondary sampling signal.

[0067] In one embodiment, the output driving unit 111b includes an operational amplifier OPA. The in-phase input terminal of the operational amplifier OPA is connected to the primary sampling signal, the inverting input terminal of the operational amplifier OPA is connected to its output terminal, and the output terminal of the operational amplifier OPA outputs the secondary sampling signal; the operational amplifier OPA is used as a voltage follower, has a lower output impedance and a higher output current capability, can maintain the stability of the output signal, and increase the driving capability of the output signal.

[0068] In this embodiment, the higher back electromotive force signal is sampled by resistor voltage division, so that the voltage-divided signal can meet the voltage specification of the ADC in the subsequent MCU; the driving ability of the voltage-divided signal is improved by the voltage follower, the charging and discharging speed of the ADC sampling capacitor is accelerated, and the conversion rate of the ADC is improved, so that it can exert its full performance. In addition, the voltage-dividing driving circuit 110 is integrated into the gate driver 100, which is conducive to reducing the volume of the system circuit and reducing the client cost.

[0069] The gate driving circuit 120 includes at least one gate driving module 121; in this embodiment, the gate driving circuit 120 includes a gate driving module 121, such as Figure 1 The gate driving module 121 includes a signal input unit 121a, a high-side driving unit 121b and a low-side driving unit 121c.

[0070] The signal input unit 121a is used to obtain a first intermediate signal according to a received high-side input signal and to obtain a second intermediate signal according to a received low-side input signal; the high-side driving unit 121b is connected to the signal input unit 121a and is used to obtain a floating power supply signal, a floating ground signal and a high-side gate driving signal according to the first intermediate signal; the low-side driving unit 121c is connected to the signal input unit 121a and is used to obtain a low-side gate driving signal according to the second intermediate signal.

[0071] In practical applications, the signal input unit 121a, the high-side driving unit 121b and the low-side driving unit 121c can be implemented using corresponding circuit structures in existing known gate drivers. Of course, other circuit structures that can achieve the above functions can also be used, and this embodiment does not limit this.

[0072] The voltage-dividing sampling unit 111a and the high-side driving unit 121b time-share the floating ground signal port VS, and the voltage-dividing sampling unit 111a samples the back electromotive force signal through the floating ground signal port VS. Specifically, during the load driving process, the high-side driving unit 121b provides a floating ground signal to the subsequent bridge structure through the floating ground signal port VS, so as to control the on and off of the corresponding power tube in the bridge structure, thereby driving the load to operate; and during the load operation process, the voltage-dividing sampling unit 111a samples the back electromotive force signal of the load from the bridge structure through the floating ground signal port VS, so as to feedback control the load.

[0073] It should be noted that Figure 1 The gate driver 100 only shows ports related to the present embodiment, and other irrelevant ports are not shown. However, this does not mean that the gate driver 100 of the present embodiment does not include other ports. In fact, the gate driver 100 of the present embodiment also includes other ports, such as a power port VCC.

[0074] Embodiment 2

[0075] like Figure 3 and Figure 4 As shown, this embodiment provides a gate driver 100 , which is different from the first embodiment in that the number of voltage-dividing driving modules 111 in the voltage-dividing driving circuit 110 and the number of gate driving modules 112 in the gate driving circuit 120 are different.

[0076] In this embodiment, the voltage-dividing driving circuit 110 includes three voltage-dividing driving modules 111, which correspond one-to-one to the U-phase bridge structure, V-phase bridge structure and W-phase bridge structure of the subsequent stage; correspondingly, the gate driving circuit 120 includes three gate driving modules 121, which correspond one-to-one to the U-phase bridge structure, V-phase bridge structure and W-phase bridge structure of the subsequent stage.

[0077] Among them, the three voltage-dividing driving modules 111 implement the same function, except that they process the back electromotive force signals sampled from different bridge structures to output different secondary sampling signals; similarly, the three gate driving modules 121 implement the same function, except that they process different high-side and low-side input signals to output multiple groups of different signals, wherein each group of signals includes a floating power supply signal, a floating ground signal, a high-side gate driving signal and a low-side gate driving signal.

[0078] It should be noted that Figure 3 The gate driver 100 only shows ports related to the present embodiment, and other irrelevant ports are not shown. However, this does not mean that the gate driver 100 of the present embodiment does not include other ports. In fact, the gate driver 100 of the present embodiment also includes other ports, such as a power port VCC.

[0079] Embodiment 3

[0080] like Figure 5 and Figure 6 As shown, this embodiment provides a packaged chip 10 , including a gate driver 100 and a micro-processing unit 200 .

[0081] The gate driver 100 includes a voltage divider drive circuit 110, and further includes a gate drive circuit 120; the voltage divider drive circuit 110 is used to obtain a secondary sampling signal according to the sampled back electromotive force signal, and the gate drive circuit 120 is used to obtain a floating power supply signal, a floating ground signal, a high-side gate drive signal, and a low-side gate drive signal according to a high-side input signal and a low-side input signal. Among them, the gate driver 100 is implemented using the structure of the first embodiment, and the relevant content can be found in the first embodiment, which will not be repeated here.

[0082] The microprocessing unit 200 includes an analog-to-digital converter 210 and further includes a microprocessor 220. The analog-to-digital converter 210 is used to sample the secondary sampling signal to obtain a detection signal, and the microprocessor 220 is used to regulate the high-side input signal and the low-side input signal according to the detection signal.

[0083] In this embodiment, the voltage-dividing driving circuit 110 includes a voltage-dividing driving module 111, and the gate driving circuit 120 includes a gate driving module 121. The voltage-dividing driving module 111 only processes the back electromotive force signal of a bridge structure to obtain a secondary sampling signal, and the gate driving module 121 only processes a group of high-side and low-side input signals to output a group of signals (including a floating power supply signal, a floating ground signal, a high-side gate driving signal, and a low-side gate driving signal); and the microprocessing unit 200 corresponds to the gate driver 100, and the analog-to-digital converter 210 only processes a secondary sampling signal to obtain a detection signal, and the microprocessor 220 can regulate the group of high-side and low-side input signals according to the detection signal. In practical applications, the microprocessor 220 is not limited to regulating the high-side and low-side input signals according to the above-mentioned detection signals, but can also regulate the high-side and low-side input signals in combination with other feedback signals.

[0084] This embodiment combines the gate driver 100 and the microprocessor unit 200 into one chip, thereby reducing the influence of the external circuit on the sampling detection result and improving the sampling detection accuracy. In addition, the combination of the two chips is beneficial to reducing the overall circuit volume and reducing the client cost.

[0085] It should be noted that Figure 5The gate driver 100, the microprocessor unit 200 and the packaged chip 10 only show ports related to the present embodiment, and other irrelevant ports are not shown. However, this does not mean that the above parts do not include other ports. In fact, the above parts also include other ports, such as the power port VCC.

[0086] Embodiment 4

[0087] like Figure 7 and Figure 8 As shown, this embodiment provides a packaged chip 10 , which is different from the third embodiment in that the gate driver 100 and the micro-processing unit 200 are different.

[0088] In this embodiment, the gate driver 100 is implemented by the structure of the second embodiment, the voltage-dividing driving circuit 110 includes three voltage-dividing driving modules 111, and the gate driving circuit 120 includes three gate driving modules 121; the three voltage-dividing driving modules 111 process the back electromotive force signals of different bridge structures to obtain three secondary sampling signals, and the three gate driving modules 121 process the three groups of high-side and low-side input signals to output three groups of signals. The microprocessing unit 200 corresponds to the gate driver 100, the analog-to-digital converter 210 processes the three secondary sampling signals to obtain three detection signals, and the microprocessor 220 regulates the three groups of high-side and low-side input signals according to the three detection signals.

[0089] It should be noted that Figure 7 The gate driver 100, the microprocessor unit 200 and the packaged chip 10 only show ports related to the present embodiment, and other irrelevant ports are not shown. However, this does not mean that the above parts do not include other ports. In fact, the above parts also include other ports, such as the power port VCC.

[0090] Embodiment 5

[0091] like Fig. 9 As shown, this embodiment provides a control system, including a packaged chip 10, a bridge structure 20 and a load 30, and further including a capacitor C and a third resistor R3.

[0092] The packaged chip 10 is implemented using the structure described in Example 3. The relevant content can be found in Example 3 and will not be repeated here. The bridge structure 20 is a half-bridge, which is composed of two power tubes connected in series. The load can be any structure driven by a half-bridge, and this embodiment does not limit this. The capacitor C is connected in series between the floating power signal port VB and the floating ground signal port VS of the packaged chip 10. The third resistor R3 is connected in series between the lower bridge power tube and the reference ground in the bridge structure 20.

[0093] The packaged chip 10 is connected to the load 30 via a bridge structure 20, and the load 30 is driven to operate by controlling the on / off of the power tubes (including the upper bridge power tube and the lower bridge power tube) in the bridge structure 20, and the back electromotive force signal is sampled during the operation of the load 30 to perform feedback control on the load 30.

[0094] Embodiment 6

[0095] like Fig.10 As shown, this embodiment provides a control system, which is different from the fifth embodiment in that the packaged chip 10, the bridge structure 20 and the load 30 are different.

[0096] In this embodiment, the sealed chip 10 is implemented using the structure described in Embodiment 4, wherein the voltage divider drive circuit 110 in the gate driver 100 includes three voltage divider drive modules 111 and the gate drive circuit 120 includes three gate drive modules 121. The relevant contents can be found in Embodiment 4 and will not be repeated here. The number of bridge structures 20 is three, including a U-phase bridge structure 20a, a V-phase bridge structure 20b and a W-phase bridge structure 20c. The load 30 includes a motor, such as a three-phase DC motor.

[0097] In addition, the number of capacitors in the control system is three, among which capacitor C1 is connected in series between the first floating power signal port VB1 and the first floating ground signal port VS1 of the packaged chip 10, capacitor C2 is connected in series between the second floating power signal port VB2 and the second floating ground signal port VS2 of the packaged chip 10, and capacitor C3 is connected in series between the third floating power signal port VB3 and the third floating ground signal port VS3 of the packaged chip 10.

[0098] The three groups of outputs of the packaged chip 10 are respectively connected to the three phases of the motor through three bridge structures. The motor is driven by controlling the on-off of the power tubes (including the upper bridge power tube and the lower bridge power tube) in each bridge structure, and the back electromotive force signal of each phase is sampled during the operation of the motor to perform feedback control on the motor.

[0099] In summary, the utility model provides a gate driver, a sealed chip and a control system, wherein a voltage divider driving circuit is integrated in the gate driver, and a higher back electromotive force signal is sampled through a resistor voltage divider, so that the voltage-divided signal can meet the voltage specification of the ADC in the subsequent MCU, and the driving capability of the voltage-divided signal is improved through a voltage follower formed by an operational amplifier, the charging and discharging speed of the ADC sampling capacitor is accelerated, and the conversion rate of the ADC is improved, so that the full performance can be exerted, fast and accurate back electromotive force detection is achieved, and the stability of load operation is improved; compared with the existing gate driver, the gate driver of the utility model has stronger market competitiveness.

[0100] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed in the present invention shall still be covered by the claims of the present invention.

Claims

1. A gate driver, characterized in that: The gate driver comprises: A voltage-dividing driving circuit, wherein the voltage-dividing driving circuit comprises at least one voltage-dividing driving module, and the voltage-dividing driving module comprises a voltage-dividing sampling unit and an output driving unit; The voltage-dividing sampling unit is used to sample the back electromotive force signal from the subsequent bridge structure to obtain a primary sampling signal; The output driving unit is connected to the output end of the voltage-dividing sampling unit, and is used to increase the driving capability of the primary sampling signal to obtain a secondary sampling signal.

2. The gate driver according to claim 1, characterized in that: The voltage-dividing driving circuit includes three voltage-dividing driving modules, which correspond one-to-one to the U-phase bridge structure, the V-phase bridge structure and the W-phase bridge structure of the subsequent stage.

3. The gate driver according to claim 1, characterized in that: The voltage division sampling unit includes a first resistor and a second resistor, wherein the first end of the first resistor is connected to the back electromotive force signal, the second end of the first resistor is connected to the first end of the second resistor and outputs the primary sampling signal, and the second end of the second resistor is connected to the reference ground.

4. The gate driver according to claim 1, characterized in that: The output driving unit comprises an operational amplifier, a non-inverting input terminal is connected to the primary sampling signal, an inverting input terminal is connected to the output terminal, and the output terminal outputs the secondary sampling signal.

5. The gate driver according to any one of claims 1 to 4, characterized in that: The gate driver further comprises: A gate driving circuit, wherein the gate driving circuit comprises at least one gate driving module, and the gate driving module comprises a signal input unit, a high-side driving unit, and a low-side driving unit; The signal input unit is used to obtain a first intermediate signal according to a received high-side input signal and to obtain a second intermediate signal according to a received low-side input signal; The high-side driving unit is connected to the signal input unit, and is used to obtain a floating power supply signal, a floating ground signal and a high-side gate driving signal according to the first intermediate signal; The low-side driving unit is connected to the signal input unit, and is used to obtain a low-side gate driving signal according to the second intermediate signal; The voltage-dividing sampling unit and the high-side driving unit time-share a floating ground signal port, and the voltage-dividing sampling unit samples the back electromotive force signal through the floating ground signal port.

6. The gate driver according to claim 5, characterized in that: When the voltage-dividing driving circuit includes three voltage-dividing driving modules, the gate driving circuit includes three gate driving modules, which correspond one-to-one to the U-phase bridge structure, the V-phase bridge structure and the W-phase bridge structure of the subsequent stage respectively.

7. A sealed chip, characterized in that: The sealed chip comprises: The gate driver and microprocessor unit according to any one of claims 1 to 6; The gate driver is used to obtain a secondary sampling signal according to the sampled back electromotive force signal; The microprocessing unit comprises an analog-to-digital converter, and the analog-to-digital converter is used to sample the secondary sampling signal to obtain a detection signal.

8. The sealed chip according to claim 7, characterized in that: When the gate driver also includes a gate driving circuit, the gate driver is also used to obtain a floating power supply signal, a floating ground signal, a high-side gate driving signal and a low-side gate driving signal according to the high-side input signal and the low-side input signal. At this time, the microprocessing unit also includes a microprocessor, which is used to obtain the high-side input signal and the low-side input signal according to the detection signal.

9. A control system, characterized in that: The control system comprises: The packaged chip, bridge structure and load as described in claim 8, wherein the packaged chip is connected to the load through the bridge structure, the load is driven to operate by controlling the on-off of the power tube in the bridge structure, and the back electromotive force signal is sampled during the operation of the load to feedback control the load.

10. The control system according to claim 9, characterized in that: In the sealed chip, the voltage divider drive circuit in the gate driver includes three voltage divider drive modules and the gate drive circuit includes three gate drive modules; the bridge structure includes a U-phase bridge structure, a V-phase bridge structure and a W-phase bridge structure; and the load includes a motor.

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