Image sensor based on gain adjustment

Abstract

The utility model provides an image sensor based on gain adjustment. The image sensor comprises a plurality of pixel blocks arranged in an array and a node sharing structure. The pixel block comprises a light sensing unit, an overflow unit and a gain unit, the light sensing unit and the gain unit are coupled to the first floating diffusion node, the overflow unit is coupled to the light sensing unit or the gain unit, and the light sensing unit generates a first charge signal and a second charge signal based on photoelectric conversion and stores the first charge signal; the overflow unit is used for storing the second charge signal, and the gain unit is used for switching different gain modes; the node sharing structure is coupled between the gain units of the at least two pixel blocks and is used for increasing the storage capacity of the first floating diffusion node based on node sharing when the gain units are opened. According to the utility model, the problem that the storage capacity of the image sensor in a low-gain mode cannot be suitable for highlight scene requirements and is gradually increased is solved.

Description

Technical Field

[0001] The utility model relates to the technical field of image sensors, in particular to an image sensor based on gain adjustment. Background Art

[0002] Existing image sensors can achieve a large dynamic range by designing low-gain mode and high-gain mode, but the storage capacity in low-gain mode is fixed and cannot be applied to the situation where the demand for high-light scenes gradually increases, so the fineness of the output image is stretched when the demand for high-light scenes gradually increases. Therefore, how to increase the storage capacity of image sensors in low-gain mode is a technical problem that technicians in this field are eager to solve.

[0003] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the utility model and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology section of the utility model. Utility Model Content

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an image sensor based on gain adjustment, so as to solve the problem that the storage capacity of the existing image sensor in low gain mode cannot meet the gradually increasing demand for high-light scenes.

[0005] To achieve the above-mentioned purpose and other related purposes, the utility model provides an image sensor based on gain adjustment, comprising a plurality of pixel blocks arranged in an array and a node sharing structure;

[0006] The pixel block includes a photosensitive unit, an overflow unit and a gain unit, the photosensitive unit and the gain unit are coupled to a first floating diffusion node, the overflow unit is coupled to the photosensitive unit or the gain unit, the photosensitive unit generates a first charge signal and a second charge signal based on photoelectric conversion and stores the first charge signal, the overflow unit is used to store the second charge signal, and the gain unit is used to switch between different gain modes;

[0007] The node sharing structure is coupled between the gain units of at least two of the pixel blocks, and is used to increase the storage capacity of the first floating diffusion node based on node sharing when the gain unit is turned on.

[0008] Optionally, when the overflow unit is coupled to the photosensitive unit, the overflow unit includes an overflow path and a quantization path, the second charge signal is stored in the overflow unit through the overflow path and transferred to the second floating diffusion node through the quantization path, wherein the first charge signal is transferred to the first floating diffusion node.

[0009] Optionally, when the overflow unit is coupled to the photosensitive unit, the overflow unit includes an overflow path and a quantization path, the second charge signal is stored in the overflow unit through the overflow path and transferred to the first floating diffusion node through the quantization path, wherein the first charge signal is transferred to the first floating diffusion node.

[0010] Optionally, the second charge signal is stored in the overflow unit through the overflow path and transferred to the second floating diffusion node through the quantization path, wherein:

[0011] The first floating diffusion node and the second floating diffusion node belong to the same pixel block, and the pixel block further includes a first reset unit, a second reset unit, a first readout unit, and a second readout unit; the first reset unit is coupled to the first floating diffusion node through the gain unit, and is used to reset the first floating diffusion node and the photosensitive unit; the second reset unit is coupled to the second floating diffusion node, and is used to reset the second floating diffusion node; the first readout unit is coupled to the first floating diffusion node, and is used to at least quantize and read out the first charge signal transferred to the first floating diffusion node; the second readout unit is coupled to the second floating diffusion node, and is used to at least quantize and read out the second charge signal transferred to the second floating diffusion node; the first reset unit and / or the second reset unit are also used to reset the overflow unit;

[0012] Alternatively, the first floating diffusion node and the second floating diffusion node belong to pixel blocks in different rows in the same column, and the pixel block also includes a third reset unit and a third readout unit; the third reset unit is coupled to the corresponding floating diffusion node through the gain unit, and is used to reset the corresponding floating diffusion node, the photosensitive unit and the overflow unit; the third readout unit is coupled to the corresponding floating diffusion node, and is used to at least quantize and read out the corresponding charge signal transferred to the corresponding floating diffusion node.

[0013] Optionally, when the pixel block includes a first readout unit and a second readout unit, the first readout unit and the second readout unit are quantized and read out through different column lines; when the pixel block includes a third readout unit, the third readout units of the pixel blocks in different rows in the same column are quantized and read out through different column lines.

[0014] Optionally, when the first floating diffusion node and the second floating diffusion node belong to pixel blocks in different rows in the same column, the pixel blocks in different rows in the same column include pixel blocks in two adjacent rows in the same column; wherein, among the pixel blocks in two adjacent rows in the same column, the pixel blocks in the upper row always use the floating diffusion nodes corresponding to the pixel blocks in the lower row as their second floating diffusion nodes, or the pixel blocks in the lower row always use the floating diffusion nodes corresponding to the pixel blocks in the upper row as their second floating diffusion nodes; or, the floating diffusion nodes corresponding to the pixel blocks in two rows are each other's second floating diffusion nodes.

[0015] Optionally, the overflow unit includes a first overflow transistor, a first quantization transistor and a first storage device; the control end of the first overflow transistor receives a first overflow control signal, the first end is coupled to the photosensitive unit, and the second end is coupled to the first end of the first storage device; the control end of the first quantization transistor receives a first quantization control signal, the first end is coupled to the second floating diffusion node or is coupled to the second floating diffusion node through the gain unit or is coupled to the first floating diffusion node through the corresponding gain unit, and the second end is coupled to the first end of the first storage device; the second end of the first storage device is coupled to a reference potential; wherein the path where the first overflow transistor is located is the overflow path, and the path where the first quantization transistor is located is the quantization path;

[0016] Alternatively, when the first floating diffusion node and the second floating diffusion node belong to the same pixel block, the overflow unit removes the first quantization transistor, and at this time, the first end of the first storage device is also coupled to the second floating diffusion node.

[0017] Optionally, when the first floating diffusion node and the second floating diffusion node belong to the pixel blocks in different rows in the same column, the overflow unit includes a second overflow transistor, a second quantization transistor and a second storage device; the control end of the second overflow transistor receives a second overflow control signal, the first end is coupled to the photosensitive unit, and the second end is coupled to the first end of the second storage device; the control end of the second quantization transistor receives a second quantization control signal, the first end is coupled to the second floating diffusion node through the node sharing structure and the gain unit corresponding to the second floating diffusion node, and the second end is coupled to the first end of the second storage device; the second end of the second storage device is coupled to a reference potential; wherein, the path where the second overflow transistor is located is the overflow path, and the path where the second quantization transistor is located is the quantization path.

[0018] Optionally, the node sharing structure includes a first connection line coupled between the gain units of at least two of the pixel blocks.

[0019] Optionally, the node sharing structure further includes at least one first switch tube, which is coupled in series to the first connecting line and has a control end thereof receiving a first switch control signal.

[0020] Optionally, when the overflow unit is coupled to the gain unit, the overflow unit includes a common path, the second charge signal is stored in the overflow unit through the common path and transferred to the first floating diffusion node through the common path, wherein the first charge signal is transferred to the first floating diffusion node;

[0021] The pixel block also includes a fourth reset unit and a fourth readout unit; the fourth reset unit is coupled to the first floating diffusion node through the gain unit, and is used to reset the first floating diffusion node, the photosensitive unit and the overflow unit; the fourth readout unit is coupled to the first floating diffusion node, and is used to quantize and read out at least the first charge signal and the second charge signal transferred to the first floating diffusion node.

[0022] Optionally, the overflow unit includes an overflow quantization transistor and a third storage device; the control end of the overflow quantization transistor receives an overflow quantization control signal, the first end is coupled to the high gain quantization node or the low gain quantization node of the gain unit, and the second end is coupled to the first end of the third storage device; the second end of the third storage device is coupled to a reference potential; wherein the path where the overflow quantization transistor is located is the common path;

[0023] When the first end of the overflow quantization transistor is coupled to the high gain quantization node of the gain unit, the node sharing structure includes a second connection line coupled between the gain units of at least two of the pixel blocks; when the first end of the overflow quantization transistor is coupled to the low gain quantization node of the gain unit, the node sharing structure also includes a second switch tube, which is serially coupled to the second connection line, and a control end of which receives a second switch control signal;

[0024] And / or, the fourth readout units of the pixel blocks in different rows in the same column perform quantization readout through different column lines.

[0025] As described above, the gain-adjustable image sensor of the present invention, through the design of pixel blocks and node sharing structures, realizes that when the gain unit is turned on, node sharing is performed through the node sharing structure to increase the storage capacity of the floating diffusion node in the current pixel block, thereby being suitable for situations where the demand for high-light scenes gradually increases. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1Shown is a structural schematic diagram of an image sensor in Embodiment 1 of the present utility model.

[0027] Figure 2 Shown is another structural schematic diagram of the image sensor in the first embodiment of the utility model.

[0028] Figure 3 Shown is another structural schematic diagram of the image sensor in the first embodiment of the utility model.

[0029] Figure 4 Shown is a structural schematic diagram of an image sensor in Embodiment 2 of the present utility model.

[0030] Figure 5 Shown is another structural schematic diagram of the image sensor in the second embodiment of the present utility model.

[0031] Figure 6 Shown is a schematic diagram of the structure of the image sensor in the third embodiment of the present utility model.

[0032] Figure 7 Shown is a schematic diagram of the structure of the image sensor in the fourth embodiment of the present utility model.

[0033] Figure 8 Display as Figure 7 The timing diagram corresponding to the pixel block in the image sensor shown.

[0034] Fig. 9 Shown is a schematic diagram of the structure of the image sensor in the fifth embodiment of the present utility model.

[0035] Fig.10 Display as Fig. 9 A timing diagram corresponding to a pixel block in the image sensor shown.

[0036] Fig.11 Display as Fig. 9 Another timing diagram corresponding to the pixel block in the image sensor shown.

[0037] Component number description

[0038] 100 Image Sensor

[0039] 110 pixel block

[0040] 111 Photosensitive unit

[0041] 112 Overflow Unit

[0042] 113 Gain Unit

[0043] 114a First reset unit

[0044] 114b Second reset unit

[0045] 114c Third reset unit

[0046] 114d Fourth reset unit

[0047] 115a First readout unit

[0048] 115b Second readout unit

[0049] 115c Third readout unit

[0050] 115d Fourth readout unit

[0051] 120 node shared structure

[0052] 121a First connection line

[0053] 121b Second connection line

[0054] 122a The first switch tube

[0055] 122b Second switch tube DETAILED DESCRIPTION

[0056] The following is an explanation of the implementation of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0057] See also Figures 1 to 11 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the utility model in a schematic manner, and the illustrations only show the components related to the utility model rather than the number, shape and size of the components in actual implementation. The form, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.

[0058] Embodiment 1

[0059] like Figure 1 As shown, this embodiment provides an image sensor 100 based on gain adjustment, including a plurality of pixel blocks 110 arranged in an array and a node sharing structure 120 .

[0060] The pixel block 110 includes a photosensitive unit 111, an overflow unit 112 and a gain unit 113, and further includes a first reset unit 114a, a second reset unit 114b, a first readout unit 115a and a second readout unit 115b; wherein the pixel block 110 includes two floating diffusion nodes, namely, a first floating diffusion node FD1 and a second floating diffusion node FD2.

[0061] The photosensitive unit 111 is coupled to the first floating diffusion node FD1 , generates a first charge signal and a second charge signal based on photoelectric conversion, and stores the first charge signal and transfers the first charge signal to the first floating diffusion node FD1 .

[0062] As an example, the photosensitive unit 111 includes at least one photosensitive element PD and at least one transfer transistor M1; the control end of the transfer transistor M1 receives a transmission control signal TX, the first end is coupled to the first floating diffusion node FD1, the second end is coupled to the first end of the photosensitive element PD, and the second end of the photosensitive element PD is coupled to the ground potential or the negative potential.

[0063] The photosensitive element PD includes a photodiode, and the transmission transistor M1 includes an NMOS tube. At this time, the gate of the transmission transistor M1 receives the transmission control signal TX, the drain is connected to the first floating diffusion node FD1, the source is connected to the first end of the photosensitive element PD (such as the N-type ion doping region), and the second end of the photosensitive element PD (such as the P-type ion doping region) is connected to the ground potential or the negative potential. Of course, in other examples, it is also feasible for the photosensitive element PD to include a grating or a photoconductor and the transmission transistor M1 to include a PMOS tube, which has no effect on this embodiment.

[0064] Typically, the photosensitive element PD is designed to correspond one to one with the transfer transistor M1, and the number of the photosensitive element PD and the transfer transistor M1 can be designed according to actual needs. For example, the photosensitive element PD can be one, or a shared structure formed by two, four, eight, etc. This embodiment does not impose any restrictions on this.

[0065] For the photosensitive unit 111, combined with the actual application scenario, the first charge signal refers to the charge signal corresponding to the potential well portion, and the second charge signal refers to the charge signal corresponding to the overflow portion after the charge exceeds the potential well; when the amount of charge sensed by the photosensitive unit 111 does not reach the overflow state, the charge signal converted therefrom only includes the first charge signal, which is stored in the photosensitive element PD. At this time, the second charge signal can be considered to be zero; when the amount of charge sensed by the photosensitive unit 111 reaches the overflow state, the charge signal converted therefrom includes the first charge signal and the second charge signal. The first charge signal is stored in the photosensitive element PD, and the second charge signal overflows the photosensitive element PD and is stored in the overflow unit 112. In some applications, the first charge signal can also be defined as a potential well charge signal, and the second charge signal can be defined as an overflow charge signal.

[0066] The overflow unit 112 is coupled to the photosensitive unit 111 and is used to store the second charge signal. The overflow unit 112 includes an overflow path and a quantization path. The second charge signal is stored in the overflow unit 112 through the overflow path and transferred to the second floating diffusion node FD2 through the quantization path.

[0067] As an example, in one embodiment, the overflow unit 112 includes a first overflow transistor M21, a first quantization transistor M31 and a first storage device C11; the control end of the first overflow transistor M21 receives a first overflow control signal OFG1, the first end is coupled to the photosensitive unit 111, such as, coupled to the first end of the photosensitive element PD, and the second end is coupled to the first end of the first storage device C11; the control end of the first quantization transistor M31 receives a first quantization control signal OF_CTL1, the first end is coupled to the second floating diffusion node FD2, and the second end is coupled to the first end of the first storage device C11; the second end of the first storage device C11 is coupled to a reference potential, such as, coupled to the ground potential; wherein the path where the first overflow transistor M21 is located is an overflow path, and the path where the first quantization transistor M31 is located is a quantization path.

[0068] Among them, the first storage device C11 includes a capacitor device, the first overflow transistor M21 includes an NMOS tube, the first quantization transistor M31 includes an NMOS tube, the gate of the first overflow transistor M21 receives the first overflow control signal OFG1, the drain is connected to one end of the photosensitive element PD, the source is connected to the first end of the first storage device C11, the gate of the first quantization transistor M31 receives the first quantization control signal OF_CTL1, the drain is connected to the second floating diffusion node FD2, and the source is connected to the first end of the first storage device C11; of course, in other examples, it is also feasible that the first overflow transistor M21 includes a PMOS tube and the first quantization transistor M31 includes a PMOS tube, which has no effect on this embodiment.

[0069] In another embodiment, if Figure 2 As shown, the overflow unit 112 can also remove the first quantization transistor M31. At this time, the first end of the first storage device C11 is coupled to the second end of the first overflow transistor M21 and is also coupled to the second floating diffusion node FD2. In this embodiment, the overflow unit 112 includes the first overflow transistor M21 and the first storage device C11. The control end of the first overflow transistor M21 receives the first overflow control signal OFG1, the first end is coupled to the photosensitive unit 111, such as the first end of the photosensitive element PD, the second end is coupled to the first end of the first storage device C11, the first end of the first storage device C11 is coupled to the second floating diffusion node FD2, and the second end is coupled to the reference potential, such as the ground potential; wherein the path where the first overflow transistor M21 is located is the overflow path, and the path where the first end of the first storage device C11 to the second floating diffusion node FD2 is the quantization path.

[0070] As an example, the pixel block 110 also includes a fast reset unit (not shown in the figure), which is coupled to both ends of the first storage device C11 in the overflow unit 112 and is used to reset the overflow unit 112. In an application, the fast reset unit can cooperate with the corresponding reset unit to reset the first storage device C11.

[0071] In one implementation, the fast reset unit may include a fast reset transistor, a control terminal receiving a fast reset control signal, a first terminal coupled to one terminal of the first storage device C11, and a second terminal coupled to the other terminal of the first storage device C11. Optionally, the fast reset transistor includes an NMOS tube, in which case the gate of the fast reset transistor receives the fast reset control signal, the drain is connected to the first terminal of the first storage device C11, and the source is connected to the second terminal of the first storage device C11.

[0072] As an optional solution, the other end of the first storage device C11 is coupled to a variable potential. At this time, the corresponding end of the fast reset transistor is also coupled to the variable potential, and the two can be simultaneously regulated based on the variable potential. In other embodiments, the other end of the first storage device C11 can also be coupled to the ground potential instead of the variable potential. In addition, according to the threshold of the fast reset transistor, the control end of the fast reset transistor can be short-circuited with the end coupled to the variable potential while ensuring the normal switching of the transistor. Among them, the overflow unit 112 can be quickly reset during the global reset of the circuit or the reset reading process of the signal in the first storage device C11, which is beneficial to the resetting of the first storage device C11 and the improvement of the timing control of the device.

[0073] The gain unit 113 is coupled to the first floating diffusion node FD1 for switching between different gain modes, such as switching between a first gain mode and a second gain mode. In one embodiment, the first gain mode includes a low gain (LCG) mode, and the second gain mode includes a high gain (HCG) mode.

[0074] As an example, the gain unit 113 includes a gain transistor M4, a control end receiving a gain control signal DCG, a first end coupled to a first reset unit 114a, and a second end coupled to a first floating diffusion node FD1. If the gain transistor M4 is turned on, the image sensor operates in a first gain mode, and if the gain transistor M4 is turned off, the image sensor operates in a second gain mode. In addition, it should be noted that the gain unit 113 may also have more than two gains, for example, implemented by at least two gain transistors, in which case it can be considered that the gain nodes greater than the minimum gain can all be called high gain nodes, and the gain nodes less than the maximum gain can all be called low gain nodes. For example, in the case of having one gain transistor, and the first gain mode is a low gain (LCG) mode, and the second gain mode is a high gain (HCG) mode, the low gain node corresponds to the drain of the gain transistor, and the high gain corresponds to the source of the gain transistor, that is, the first floating diffusion node FD1.

[0075] The gain transistor M4 includes an NMOS tube, a gate receives a gain control signal DCG, a drain is connected to the first reset unit 114a, and a source is connected to the first floating diffusion node FD1; of course, in other examples, it is also feasible for the gain transistor M4 to include a PMOS tube, which has no effect on this embodiment.

[0076] The first reset unit 114 a is coupled to the first floating diffusion node FD1 through the gain unit 113 , and is used to reset the first floating diffusion node FD1 and the photosensitive unit 111 , and further, is used to reset the overflow unit 112 .

[0077] As an example, the first reset unit 114a includes a first reset transistor M51, a control end receives a first reset control signal RST1, a first end is coupled to a first power supply potential, and a second end is coupled to the gain unit 113, such as, coupled to the drain of the gain transistor M4. The first reset transistor M51 includes an NMOS tube, a gate receives the first reset control signal RST1, a drain is connected to the first power supply potential, and a source is connected to the drain of the gain transistor M4. The first power supply potential is usually the potential of the working voltage and is always a high potential; of course, in other examples, it is also feasible for the first reset transistor M51 to include a PMOS tube, which has no effect on this embodiment.

[0078] The second reset unit 114b is coupled to the second floating diffusion node FD2, and is used to reset the second floating diffusion node FD2, and further, to reset the overflow unit 112. In practical applications, the overflow unit 112 is usually reset using the second reset unit 114b instead of the first reset unit 114a.

[0079] As an example, the second reset unit 114b includes a second reset transistor M52, a control end receiving a second reset control signal RST2, a first end coupled to a second power supply potential, and a second end coupled to a second floating diffusion node FD2. The second reset transistor M52 includes an NMOS tube, a gate receiving the second reset control signal RST2, a drain connected to a second power supply potential, and a source connected to the second floating diffusion node FD2. The second power supply potential is usually the potential of the working voltage and is always a high potential. Of course, in other examples, it is also feasible for the second reset transistor M52 to include a PMOS tube, which has no effect on this embodiment.

[0080] The first readout unit 115 a is coupled to the first floating diffusion node FD1 and is configured to perform quantization readout on at least the first charge signal transferred to the first floating diffusion node FD1 .

[0081] As an example, the first read-out unit 115a includes a first source follower transistor M61 and a first selection transistor M71, the control end of the first source follower transistor M61 is coupled to the first floating diffusion node FD1, the first end is coupled to the third power supply potential, the second end is coupled to the first end of the first selection transistor M71, the control end of the first selection transistor M71 receives the first selection signal SEL1, and the second end is coupled to the first column line BIT1.

[0082] Among them, the first source follower transistor M61 includes an NMOS tube, the first selection transistor M71 includes an NMOS tube, the gate of the first source follower transistor M61 is connected to the first floating diffusion node FD1, the drain is connected to the third power supply potential, the source is connected to the drain of the first selection transistor M71, the gate of the first selection transistor M71 receives the first selection signal SEL1, the source is connected to the first column line BIT1, the third power supply potential is usually the potential of the working voltage, and is always a high potential; of course, in other examples, it is also feasible for the first source follower transistor M61 to include a PMOS tube and the first selection transistor M71 to include a PMOS tube, which has no effect on this embodiment.

[0083] The second readout unit 115 b is coupled to the second floating diffusion node FD2 , and is configured to perform quantized readout on at least the second charge signal transferred to the second floating diffusion node FD2 .

[0084] As an example, the second read-out unit 115b includes a second source follower transistor M62 and a second selection transistor M72, the control end of the second source follower transistor M62 is coupled to the second floating diffusion node FD2, the first end is coupled to the fourth power supply potential, the second end is coupled to the first end of the second selection transistor M72, the control end of the second selection transistor M72 receives the second selection signal SEL2, and the second end is coupled to the second column line BIT2.

[0085] Among them, the second source follower transistor M62 includes an NMOS tube, the second selection transistor M72 includes an NMOS tube, the gate of the second source follower transistor M62 is connected to the second floating diffusion node FD2, the drain is connected to the fourth power supply potential, the source is connected to the drain of the second selection transistor M72, the gate of the second selection transistor M72 receives the second selection signal SEL2, the source is connected to the second column line BIT2, the fourth power supply potential is usually the potential of the working voltage, and is always a high potential; of course, in other examples, it is also feasible for the second source follower transistor M62 to include a PMOS tube and the second selection transistor M72 to include a PMOS tube, which has no effect on this embodiment.

[0086] In the pixel block 110 of the present embodiment, the first readout unit 115a and the second readout unit 115b perform quantization readout through different column lines. For example, the first readout unit 115a performs quantization readout through the first column line BIT1, and the second readout unit 115b performs quantization readout through the second column line BIT2. In this way, simultaneous quantization readout of the first charge signal and the second charge signal can be achieved, thereby improving the quantization readout speed. Of course, it is also feasible for the first readout unit 115a and the second readout unit 115b to perform quantization readout through the same column line.

[0087] The node sharing structure 120 is coupled between the gain units 113 of at least two pixel blocks 110, and is used to increase the storage capacity of the first floating diffusion node FD1 based on node sharing when the gain unit 113 is turned on, so that the first gain mode has a lower conversion gain, so as to be suitable for the situation where the demand for high-light scenes gradually increases. Among them, the node sharing structure 120 can be coupled between any required gain nodes of different gain units 113, and can be coupled between high and low gain nodes according to actual needs. In the embodiment of the utility model, it is preferably coupled between the lowest gain nodes of each gain unit 113 that needs to be coupled.

[0088] In an optional solution, the node sharing structure 120 is coupled between the gain units 113 of the pixel blocks 110 in different rows in the same column; further, the node sharing structure 120 is coupled between the gain units 113 of the pixel blocks 110 in two adjacent rows in the same column. Of course, it can also be coupled between two or more rows as required according to actual needs, for example, it can be coupled between rows corresponding to the same color pixels, so as to prevent the signals of pixels of different colors from affecting each other.

[0089] As an example, the node sharing structure 120 includes a first connecting line 121a, coupled between the gain units 113 of at least two pixel blocks 110, such as, coupled between the first ends of the gain transistors M4 in the corresponding pixel blocks 110; when the gain unit 113 is turned on, the storage capacity of the first floating diffusion node FD1 is increased based on node sharing. At this time, the shared node storage capacity corresponds to at least 2*Cfd1, where Cfd1 is the storage capacity of the first floating diffusion node FD1.

[0090] Further, such as Figure 3 As shown, the node sharing structure 120 also includes at least one first switch tube 122a, which is coupled in series to the first connection line 121a, and its control end receives the first switch control signal SW1; wherein the first switch tube 122a includes an NMOS tube. Of course, it is also feasible for the first switch tube 122a to include a PMOS tube, which has no impact on this embodiment.

[0091] After the node sharing structure 120 of this embodiment is additionally provided with the first switch tube 122 a , if node sharing is desired, in addition to controlling the gain unit 113 to be turned on, the first switch tube 122 a should also be controlled to be turned on.

[0092] Correspondingly, this embodiment also provides a control method for an image sensor, including a quantization stage, and further, a reset stage and an exposure stage; wherein the image sensor is implemented using the circuit structure described above.

[0093] Reset phase:

[0094] The first floating diffusion node FD1, the second floating diffusion node FD2, the photosensitive unit 111 and the overflow unit 112 are reset; further, the first floating diffusion node FD1 and the photosensitive unit 111 are reset by the first reset unit 114a, and the second floating diffusion node FD2 and the overflow unit 112 are reset by the second reset unit 114b.

[0095] For example, Figure 1For example, the first reset transistor M51, the gain transistor M4 and the transfer transistor M1 are controlled to be turned on, and the charge of the first floating diffusion node FD1 and the photosensitive element PD is cleared to achieve signal reset; the second reset transistor M52 and the first quantization transistor M31 are controlled to be turned on, and the charge of the second floating diffusion node FD2 and the first storage device C11 is cleared to achieve signal reset; in this way, the reset operation is completed. After that, the first reset transistor M51, the transfer transistor M1, the second reset transistor M52 and the first quantization transistor M31 are controlled to be turned off.

[0096] Exposure stage:

[0097] The second charge signal is stored in the overflow unit 112 , specifically, the overflow path is opened and the quantization path is closed, and the second charge signal is stored in the overflow unit 112 through the overflow path.

[0098] For example, Figure 1 For example, the first overflow transistor M21 in the overflow unit 112 is controlled to be turned on, and the overflow path is opened, and the second charge signal overflowed from the photosensitive element PD in the photosensitive unit 111 is transferred through the overflow path to the first storage device C11 of the overflow unit 112 for storage. Afterwards, the first overflow transistor M21 is controlled to be turned off.

[0099] When the amount of charge sensed by the photosensitive element PD does not reach the overflow state, the converted charge signal includes only the first charge signal, which is stored on the photosensitive element PD. Although the overflow path is opened at this time, no second charge signal is transferred to the first storage device C11 through the overflow path. It can be considered that the corresponding second charge signal in this process is zero. When the amount of charge sensed by the photosensitive element PD reaches the overflow state, the converted charge signal includes the first charge signal and the second charge signal, wherein the first charge signal is stored on the photosensitive element PD, and the second charge signal is transferred to the first storage device C11 through the overflow path for storage.

[0100] Quantification stage:

[0101] The first charge signal in different gain modes is quantized and read out, and the second charge signal is quantized and read out; wherein, when the gain unit 113 is turned on, the storage capacity of the first floating diffusion node FD1 is increased by node sharing through the node sharing structure 120, and the first floating diffusion node with increased storage capacity is defined as a shared node.

[0102] In one embodiment, the quantization stage includes: performing correlated double sampling on the first charge signal in different gain modes, and performing correlated double sampling on the second charge signal.

[0103] Specifically, it includes: controlling the node sharing structure 120 to be opened, controlling the gain unit 113 to be opened and then closed, so as to quantize and read out the first reset signal in the first gain mode and the second gain mode based on the shared node and the first floating diffusion node FD1 respectively, and controlling the gain unit 113 to be closed and then opened, so as to quantize and read out the first charge signal in the second gain mode and the first gain mode based on the first floating diffusion node FD1 and the shared node respectively; controlling the quantization path in the overflow unit 112 to be closed, so as to quantize and read out the second reset signal based on the second floating diffusion node FD2, and controlling the quantization path to be opened, so as to quantize and read out the second charge signal based on the second floating diffusion node FD2.

[0104] In an optional scheme, the first read-out unit 115a and the second read-out unit 115b are quantized and read out through different column lines. At this time, the second reset signal is quantized and read out simultaneously with the first reset signal in the first gain mode or the second gain mode, and the second charge signal is quantized and read out simultaneously with the first charge signal in the first gain mode or the second gain mode, thereby improving the quantization readout speed.

[0105] It should be noted that when the node sharing structure 120 only includes the first connecting line 121a, there is no need to additionally control the node sharing structure 120 to open, and the node sharing structure 120 is in the open state by default; when the node sharing structure 120 also includes the first switch tube 122a, the node sharing structure 120 is controlled to open by controlling the first switch tube 122a to open.

[0106] by Figure 1 For example, the node sharing structure 120 only includes the first connection line 121a, and the second reset signal is quantized and read out simultaneously with the first reset signal in the first gain mode, and the second charge signal is quantized and read out simultaneously with the first charge signal in the first gain mode;

[0107] Since the gain transistor M4 in the gain unit 113 is turned on and remains turned on during the reset phase, the image sensor operates in the first gain mode; and since the node sharing structure 120 only includes the first connection line 121a, when the gain transistor M4 is turned on, the first floating diffusion nodes FD1 in the two adjacent rows of pixel blocks 110 are coupled together by the first connection line 121a to achieve node sharing;

[0108] Controlling the first selection transistor M71 in the first readout unit 115a and the second selection transistor M72 in the second readout unit 115b to turn on, so as to simultaneously perform quantization reading of the first reset signal and the second reset signal in the first gain mode based on the shared node and the second floating diffusion node FD2 respectively;

[0109] The gain transistor M4 is controlled to be turned off, so that the image sensor switches to the second gain mode, so as to quantize and read out the first reset signal in the second gain mode based on the first floating diffusion node FD1; the transfer transistor M1 in the photosensitive unit 111 is controlled to be turned on and then turned off, so as to transfer the first charge signal stored in the photosensitive element PD to the first floating diffusion node FD1, so as to quantize and read out the first charge signal in the second gain mode based on the first floating diffusion node FD1;

[0110] The gain transistor M4 is controlled to turn on, so that the image sensor switches to the first gain mode again, and the transfer transistor M1 is controlled to turn on and then turn off, so as to transfer the first charge signal stored in the photosensitive element PD to the shared node. At the same time, the first quantization transistor M31 in the overflow unit 112 is controlled to turn on, and the second charge signal stored in the first storage device C11 in the overflow unit 112 is transferred to the second floating diffusion node FD2 through the quantization path, so as to simultaneously perform quantization reading of the first charge signal and the second charge signal in the first gain mode based on the shared node and the second floating diffusion node FD2, respectively.

[0111] In another embodiment, the quantization stage includes: performing correlated double sampling on the first charge signal in different gain modes, and performing non-true correlated double sampling on the second charge signal.

[0112] Specifically, it includes: controlling the node sharing structure 120 to be opened, controlling the gain unit 113 to be opened and then closed, so as to quantize and read out the first reset signal in the first gain mode and the second gain mode based on the shared node and the first floating diffusion node FD1 respectively, and controlling the gain unit 113 to be closed and then opened, so as to quantize and read out the first charge signal in the second gain mode and the first gain mode based on the first floating diffusion node FD1 and the shared node respectively; controlling the quantization path in the overflow unit 112 to be opened, so as to quantize and read out the second charge signal based on the second floating diffusion node FD2, and performing a reset operation on the second floating diffusion node FD2, so as to quantize and read out the second reset signal based on the second floating diffusion node FD2.

[0113] In an optional solution, the first readout unit 115a and the second readout unit 115b perform quantization readout through different column lines. At this time, the second charge signal is quantized and readout simultaneously with the first charge signal in the first gain mode or the second gain mode, thereby improving the quantization readout speed.

[0114] It should be noted that when the node sharing structure 120 only includes the first connecting line 121a, there is no need to additionally control the node sharing structure 120 to open, and the node sharing structure 120 is in the open state by default; when the node sharing structure 120 also includes the first switch tube 122a, the node sharing structure 120 is controlled to open by controlling the first switch tube 122a to open.

[0115] by Figure 1 For example, the node sharing structure 120 only includes the first connection line 121a, and the second charge signal is quantized and read out simultaneously with the first charge signal in the first gain mode;

[0116] Since the gain transistor M4 in the gain unit 113 is turned on and remains turned on during the reset phase, the image sensor operates in the first gain mode; and since the node sharing structure 120 includes the first connection line 121a, when the gain transistor M4 is turned on, the first floating diffusion nodes FD1 in the two adjacent rows of pixel blocks 110 are coupled together by the first connection line 121a to achieve node sharing;

[0117] The first selection transistor M71 in the first readout unit 115a and the second selection transistor M72 in the second readout unit 115b are controlled to be turned on, so as to perform quantization reading of the first reset signal in the first gain mode based on the shared node; the gain transistor M4 is controlled to be turned off, so that the image sensor switches to the second gain mode, so as to perform quantization reading of the first reset signal in the second gain mode based on the first floating diffusion node FD1; the transfer transistor M1 in the photosensitive unit 111 is controlled to be turned on and then turned off, so as to transfer the first charge signal stored in the photosensitive element PD to the first floating diffusion node FD1, so as to perform quantization reading of the first charge signal in the second gain mode based on the first floating diffusion node FD1;

[0118] The gain transistor M4 is controlled to be turned on so that the image sensor switches to the first gain mode again, and the transfer transistor M1 is controlled to be turned on and then turned off to transfer the first charge signal stored in the photosensitive element PD to the shared node. At the same time, the first quantization transistor M31 in the overflow unit 112 is controlled to be turned on, and the second charge signal stored in the first storage device C11 in the overflow unit 112 is transferred to the second floating diffusion node FD2 through the quantization path, so that the first charge signal and the second charge signal in the first gain mode are simultaneously quantized and read out based on the shared node and the second floating diffusion node FD2 respectively; and the second reset transistor M52 in the second reset unit 114b is controlled to be turned on and then turned off to perform a secondary reset operation on the second floating diffusion node FD2, so that the second reset signal is quantized and read out based on the second floating diffusion node FD2.

[0119] Of course, in other implementations, both correlated double sampling and non-true correlated double sampling may be performed on the second charge signal; in this case, usually the second charge signal is first correlated double sampling and then non-true correlated double sampling is performed on the second charge signal.

[0120] In addition, for Figure 2In the image sensor 100 shown, since the overflow unit 112 in the pixel block 110 removes the first quantization transistor M31, the second charge signal overflowed during the exposure phase will not only be stored in the first storage device C11, but also in the second floating diffusion node FD2; in order to ensure signal accuracy, the second charge signal is usually subjected to non-true correlated double sampling, and the related control is the same as above. Of course, if both correlated double sampling and non-true correlated double sampling are required for the second charge signal, the second charge signal is first subjected to non-true correlated double sampling, and then the second charge signal is subjected to correlated double sampling.

[0121] Embodiment 2

[0122] like Figure 4 and Figure 5 As shown, this embodiment provides an image sensor 100 based on gain adjustment, including a plurality of pixel blocks 110 arranged in an array and a node sharing structure 120 .

[0123] The pixel block 110 includes a photosensitive unit 111, an overflow unit 112 and a gain unit 113, and further includes a third reset unit 114c and a third readout unit 115c; wherein the pixel block 110 includes a floating diffusion node, ie, a first floating diffusion node FD1.

[0124] The photosensitive unit 111 and the gain unit 113 are the same as those in the first embodiment, and the overflow unit 112 is the same as one implementation in the first embodiment. The relevant contents can be found in the first embodiment and will not be described again here. It should be noted that the first end of the first quantization transistor M31 in the overflow unit 112 of the present embodiment is no longer directly coupled to the second floating diffusion node FD2, but is coupled to the second floating diffusion node FD2 through the gain unit 113 of the pixel block 110 corresponding to the second floating diffusion node FD2; in addition, the first end of the gain transistor M4 in the gain unit 113 is coupled to the third reset unit 114c instead of the first reset unit 114a.

[0125] In the pixel block 110 of the present embodiment, when the first charge signal and the second charge signal are respectively transferred to the first floating diffusion node FD1 and the second floating diffusion node FD2 for quantization readout, the first floating diffusion node FD1 and the second floating diffusion node FD2 belong to two different pixel blocks 110; in an optional scheme, the first floating diffusion node FD1 and the second floating diffusion node FD2 belong to pixel blocks 110 in different rows in the same column; in an optional scheme, the first floating diffusion node FD1 and the second floating diffusion node FD2 belong to two adjacent rows of pixel blocks 110 in the same column.

[0126] For two adjacent rows of pixel blocks 110 in the same column: In one embodiment, Figure 4As shown, the upper row of pixel blocks 110 always uses the floating diffusion node corresponding to the lower row of pixel blocks 110 as its second floating diffusion node FD2. Of course, in other examples, the lower row of pixel blocks 110 may always use the floating diffusion node corresponding to the upper row of pixel blocks 110 as its second floating diffusion node FD2. In another embodiment, as Figure 5 As shown, the floating diffusion nodes corresponding to the two rows of pixel blocks 110 are each other's second floating diffusion nodes FD2.

[0127] The third reset unit 114 c is coupled to the corresponding floating diffusion node through the gain unit 113 , and is used to reset the corresponding floating diffusion node, the photosensitive unit 111 , and the overflow unit 112 .

[0128] As an example, the third reset unit 114c includes a third reset transistor M53, a control end receiving a third reset control signal RST3, a first end coupled to a fifth power supply potential, and a second end coupled to the gain unit 113, such as, coupled to the drain of the gain transistor M4. The third reset transistor M53 includes an NMOS tube, a gate receiving the third reset control signal RST3, a drain connected to the fifth power supply potential, and a source connected to the drain of the gain transistor M4. The fifth power supply potential is usually the potential of the working voltage and is always a high potential. Of course, in other examples, it is also feasible for the third reset transistor M53 to include a PMOS tube, which has no effect on this embodiment.

[0129] The third readout unit 115 c is coupled to the corresponding floating diffusion node, and is configured to at least perform quantized readout on the corresponding charge signal transferred to the corresponding floating diffusion node.

[0130] As an example, the third read-out unit 115c includes a third source follower transistor M63 and a third selection transistor M73, the control end of the third source follower transistor M63 is coupled to the corresponding floating diffusion node, the first end is coupled to the sixth power supply potential, the second end is coupled to the first end of the third selection transistor M73, the control end of the third selection transistor M73 receives the third selection signal SEL3, and the second end is coupled to the corresponding column line.

[0131] Among them, the third source follower transistor M63 includes an NMOS tube, the third selection transistor M73 includes an NMOS tube, the gate of the third source follower transistor M63 is connected to the corresponding floating diffusion node, the drain is connected to the sixth power supply potential, the source is connected to the drain of the third selection transistor M73, the gate of the third selection transistor M73 receives the third selection signal SEL3, the source is connected to the corresponding column line, the sixth power supply potential is usually the potential of the working voltage, and is always a high potential; of course, in other examples, it is also feasible that the third source follower transistor M63 includes a PMOS tube and the third selection transistor M73 includes a PMOS tube, which has no effect on this embodiment.

[0132] In an optional solution, the third readout units 115c of two adjacent rows of pixel blocks 110 in the same column are quantized and read out through different column lines. In this way, simultaneous quantized readout of the first charge signal and the second charge signal can be achieved, thereby improving the quantized readout speed. Of course, it is also feasible that the third readout units 115c of two adjacent rows of pixel blocks 110 in the same column are quantized and read out through the same column line.

[0133] The node sharing structure 120 is the same as that in the first embodiment, and the relevant contents can be found in the first embodiment, which will not be described again. The figure shows a schematic diagram of the node sharing structure 120 with only the first connecting line 121a.

[0134] Correspondingly, this embodiment also provides a control method for an image sensor, including a quantization stage, and further, a reset stage and an exposure stage; wherein the image sensor is implemented using the circuit structure described above.

[0135] Reset phase:

[0136] The first floating diffusion node FD1, the second floating diffusion node FD2, the photosensitive unit 111 and the overflow unit 112 are reset. Take the case where the first floating diffusion node FD1 and the second floating diffusion node FD2 belong to two adjacent rows of pixel blocks 110 in the same column, and the upper row of pixel blocks 110 in the two adjacent rows of pixel blocks 110 is quantized and read out. At this time, the floating diffusion node corresponding to the lower row of pixel blocks 110 is used as the second floating diffusion node FD2 of the upper row of pixel blocks 110; the first floating diffusion node FD1 and the photosensitive unit 111 are reset by the third reset unit 114c in the upper row of pixel blocks 110, and the second floating diffusion node FD2 and the overflow unit 112 in the upper row of pixel blocks 110 are reset by the third reset unit 114c in the lower row of pixel blocks 110.

[0137] For example, the third reset transistor M53, the gain transistor M4, and the transfer transistor M1 in the previous row of pixel blocks 110 are controlled to be turned on, and the charge of the first floating diffusion node FD1 and the photosensitive element PD is cleared to achieve signal reset; the first quantization transistor M31 in the previous row of pixel blocks 110 is controlled to be turned on, and the third reset transistor M53 and the gain transistor M4 in the next row of pixel blocks 110 are controlled to be turned on, and the charge of the second floating diffusion node FD2 and the first storage device C11 in the previous row of pixel blocks 110 is cleared to achieve signal reset; in this way, the reset operation is completed. Afterwards, the third reset transistor M53, the transfer transistor M1, and the first quantization transistor M31 in the previous row of pixel blocks 110 are controlled to be turned off, and the third reset transistor M53 in the next row of pixel blocks 110 is controlled to be turned off.

[0138] The exposure stage is the same as that in the first embodiment. The relevant contents can be found in the first embodiment and will not be described again here.

[0139] Quantification stage:

[0140] The first charge signal in different gain modes is quantized and read out, and the second charge signal is quantized and read out; wherein, when the gain unit 113 is turned on, the storage capacity of the first floating diffusion node FD1 is increased by node sharing through the node sharing structure 120, and the first floating diffusion node with increased storage capacity is defined as a shared node.

[0141] In one embodiment, the quantization stage includes: performing correlated double sampling on the first charge signal in different gain modes, and performing correlated double sampling on the second charge signal.

[0142] Specifically, it includes: controlling the node sharing structure 120 to be opened, controlling the gain unit 113 to be opened and then closed, so as to quantize and read out the first reset signal in the first gain mode and the second gain mode based on the shared node and the first floating diffusion node FD1 respectively, and controlling the gain unit 113 to be closed and then opened, so as to quantize and read out the first charge signal in the second gain mode and the first gain mode based on the first floating diffusion node FD1 and the shared node respectively; controlling the quantization path in the overflow unit 112 to be closed, so as to quantize and read out the second reset signal based on the second floating diffusion node FD2, and controlling the quantization path to be opened, so as to quantize and read out the second charge signal based on the second floating diffusion node FD2.

[0143] In an optional scheme, the third readout unit 115c of two adjacent rows of pixel blocks 110 in the same column is quantized and read out through different column lines. At this time, the second reset signal is quantized and read out simultaneously with the first reset signal in the second gain mode, and the second charge signal is quantized and read out simultaneously with the first charge signal in the second gain mode, thereby improving the quantization readout speed.

[0144] It should be noted that when the node sharing structure 120 only includes the first connecting line 121a, there is no need to additionally control the node sharing structure 120 to open, and the node sharing structure 120 is in the open state by default; when the node sharing structure 120 also includes the first switch tube 122a, the node sharing structure 120 is controlled to open by controlling the first switch tube 122a to open.

[0145] Take the node sharing structure 120 including only the first connection line 121a as an example; since the gain transistors M4 in the two adjacent rows of pixel blocks 110 are turned on and remain turned on during the reset phase, the image sensor operates in the first gain mode; and since the node sharing structure 120 includes only the first connection line 121a, when the gain transistor M4 is turned on, the floating diffusion nodes in the two adjacent rows of pixel blocks 110 are coupled together by the first connection line 121a to achieve node sharing;

[0146] The third selection transistors M73 in the two adjacent rows of pixel blocks 110 are controlled to be turned on, so as to quantize and read out the first reset signal in the first gain mode based on the shared node; the gain transistors M4 in the two adjacent rows of pixel blocks 110 are controlled to be turned off, so that the image sensor switches to the second gain mode, so as to quantize and read out the first reset signal and the second reset signal in the second gain mode simultaneously based on the first floating diffusion node FD1 and the second floating diffusion node FD2;

[0147] Control the transfer transistor M1 in the previous row of pixel blocks 110 to be turned on and then turned off, and transfer the first charge signal stored in the photosensitive element PD to the first floating diffusion node FD1. At the same time, control the first quantization transistor M31 in the previous row of pixel blocks 110 to be turned on, and control the gain transistor M4 in the next row of pixel blocks 110 to be turned on and then turned off, and transfer the second charge signal stored in the first storage device C11 in the previous row of pixel blocks 110 to the second floating diffusion node FD2 through the quantization path, so as to simultaneously perform quantization reading of the first charge signal and the second charge signal in the second gain mode based on the first floating diffusion node FD1 and the second floating diffusion node FD2 respectively;

[0148] The gain transistors M4 in two adjacent rows of pixel blocks 110 are controlled to open, so that the image sensor switches to the first gain mode again, and the transfer transistors M1 in the previous row of pixel blocks 110 are controlled to open and then close, so as to transfer the first charge signal stored in the photosensitive element PD to the shared node, so as to quantize and read out the first charge signal in the first gain mode based on the shared node.

[0149] In another embodiment, the quantization stage includes: performing correlated double sampling on the first charge signal in different gain modes, and performing non-true correlated double sampling on the second charge signal.

[0150] Specifically, it includes: controlling the node sharing structure 120 to be opened, controlling the gain unit 113 to be opened and then closed, so as to quantize and read out the first reset signal in the first gain mode and the second gain mode based on the shared node and the first floating diffusion node FD1 respectively, and controlling the gain unit 113 to be closed and then opened, so as to quantize and read out the first charge signal in the second gain mode and the first gain mode based on the first floating diffusion node FD1 and the shared node respectively; controlling the quantization path in the overflow unit 112 to be opened, so as to quantize and read out the second charge signal based on the second floating diffusion node FD2, and performing a reset operation on the second floating diffusion node FD2, so as to quantize and read out the second reset signal based on the second floating diffusion node FD2.

[0151] In an optional solution, the third readout units 115c of two adjacent rows of pixel blocks 110 in the same column perform quantization readout through different column lines. At this time, the second charge signal and the first charge signal in the second gain mode are quantized and readout simultaneously, thereby improving the quantization readout speed.

[0152] It should be noted that when the node sharing structure 120 only includes the first connecting line 121a, there is no need to additionally control the node sharing structure 120 to open, and the node sharing structure 120 is in the open state by default; when the node sharing structure 120 also includes the first switch tube 122a, the node sharing structure 120 is controlled to open by controlling the first switch tube 122a to open.

[0153] Take the node sharing structure 120 including only the first connection line 121a as an example; since the gain transistors M4 in the two adjacent rows of pixel blocks 110 are turned on and remain turned on during the reset phase, the image sensor operates in the first gain mode; and since the node sharing structure 120 includes only the first connection line 121a, when the gain transistor M4 is turned on, the floating diffusion nodes in the two adjacent rows of pixel blocks 110 are coupled together by the first connection line 121a to achieve node sharing;

[0154] The third selection transistors M73 in the two adjacent rows of pixel blocks 110 are controlled to be turned on, so as to perform quantization reading of the first reset signal in the first gain mode based on the shared node; and the gain transistors M4 in the two adjacent rows of pixel blocks 110 are controlled to be turned off, so that the image sensor switches to the second gain mode, so as to perform quantization reading of the first reset signal in the second gain mode based on the first floating diffusion node FD1;

[0155] Control the transfer transistor M1 in the previous row of pixel blocks 110 to be turned on and then turned off, and transfer the first charge signal stored in the photosensitive element PD to the first floating diffusion node FD1. At the same time, control the first quantization transistor M31 in the previous row of pixel blocks 110 to be turned on, and control the gain transistor M4 in the next row of pixel blocks 110 to be turned on and then turned off, and transfer the second charge signal stored in the first storage device C11 in the previous row of pixel blocks 110 to the second floating diffusion node FD2 through the quantization path, so as to simultaneously perform quantization reading of the first charge signal and the second charge signal in the second gain mode based on the first floating diffusion node FD1 and the second floating diffusion node FD2 respectively;

[0156] The gain transistors M4 in two adjacent rows of pixel blocks 110 are controlled to open, so that the image sensor switches to the first gain mode again; the transfer transistors M1 in the previous row of pixel blocks 110 are controlled to open and then close, and the first charge signal stored in the photosensitive element PD is transferred to the shared node, so as to quantize and read out the first charge signal in the first gain mode based on the shared node; and the third reset transistor M53 of the third reset unit 114c in the next row of pixel blocks 110 is controlled to open and then close, and a secondary reset operation is performed on the second floating diffusion node FD2, so as to quantize and read out the second reset signal based on the second floating diffusion node FD2.

[0157] Of course, in other implementations, both correlated double sampling and non-true correlated double sampling may be performed on the second charge signal; in this case, usually the second charge signal is first correlated double sampling and then non-true correlated double sampling is performed on the second charge signal.

[0158] Embodiment 3

[0159] like Figure 6 As shown, this embodiment provides an image sensor 100 based on gain adjustment, including a plurality of pixel blocks 110 arranged in an array and a node sharing structure 120 .

[0160] For the pixel block 110, the difference between this embodiment and the second embodiment is that the circuit structure of the overflow unit 112 is different. In this embodiment, the overflow unit 112 includes a second overflow transistor M22, a second quantization transistor M32, and a second storage device C12; the control end of the second overflow transistor M22 receives the second overflow control signal OFG2, the first end is coupled to the photosensitive unit 111, such as the first end of the photosensitive element PD, and the second end is coupled to the first end of the second storage device C12; the control end of the second quantization transistor M32 receives the second quantization control signal OF_CTL2, the first end is coupled to the second floating diffusion node FD2 through the node sharing structure 120 and the gain unit 113 corresponding to the second floating diffusion node FD2, and the second end is coupled to the first end of the second storage device C12; the second end of the second storage device C12 is coupled to the reference potential, such as the ground potential; wherein the path where the second overflow transistor M22 is located is the overflow path, the path where the second quantization transistor M32 is located is the quantization path, and the second charge signal is stored in the overflow unit 112 through the overflow path and transferred to the second floating diffusion node FD2 through the quantization path.

[0161] Among them, the second storage device C12 includes a capacitor device, the second overflow transistor M22 includes an NMOS tube, the second quantization transistor M32 includes an NMOS tube, the gate of the second overflow transistor M22 receives the second overflow control signal OFG2, the drain is connected to one end of the photosensitive element PD, the source is connected to the first end of the second storage device C12, the gate of the second quantization transistor M32 receives the second quantization control signal OF_CTL2, the drain is connected to the second floating diffusion node FD2 through the node sharing structure 120 and the gain unit 113, and the source is connected to the first end of the second storage device C12; of course, in other examples, it is also feasible that the second overflow transistor M22 includes a PMOS tube and the second quantization transistor M32 includes a PMOS tube, which has no effect on this embodiment.

[0162] In other implementations, in the overflow unit 112 of the pixel block 110 of this embodiment, the first end of the second quantization transistor M32 can also be regarded as being coupled to the first floating diffusion node FD1 through the corresponding gain unit 113, and when the second quantization transistor M32 includes an NMOS tube, that is, the drain of the second quantization transistor M32 is connected to the first floating diffusion node FD1 through the gain unit 113. At this time, the path where the second overflow transistor M22 is located is the overflow path, the path where the second quantization transistor M32 is located is the quantization path, and the second charge signal is stored in the overflow unit 112 through the overflow path and transferred to the first floating diffusion node FD1 through the quantization path.

[0163] Regarding the node sharing structure 120 , this embodiment is the same as the second embodiment, and the relevant contents can be found in the first embodiment, which will not be repeated here. The figure shows a schematic diagram of the node sharing structure 120 including the first connecting line 121a and the first switch tube 122a.

[0164] Correspondingly, this embodiment also provides a control method for an image sensor, including a quantization stage, and further, a reset stage and an exposure stage; wherein the image sensor is implemented using the circuit structure described above.

[0165] The reset phase and the exposure phase are the same as those in the second embodiment. The relevant contents can be found in the second embodiment and will not be described again here.

[0166] In the quantization stage, in one implementation, the difference between this embodiment and the second embodiment is that this embodiment performs quantization reading of the second charge signal and the second reset signal based on a new node including the second floating diffusion node FD2, wherein the storage capacity of the new node is the sum of the storage capacity of the second floating diffusion node FD2 itself, the storage capacity of the gain unit 113 itself, and the storage capacity of the node sharing structure 120 itself. In addition, the control of the corresponding transistors in this embodiment and the second embodiment is slightly different, for example, when the second charge signal or the second reset signal is quantized and read out, at least the gain transistor M4 in the pixel block 110 corresponding to the second floating diffusion node FD2 is controlled to be turned on, and when the node sharing structure 120 also includes the first switch tube 122a, the first switch tube 122a is also controlled to be turned on.

[0167] In another embodiment, for the quantization stage, the second charge signal can be stored in the overflow unit 112 through the overflow path and transferred to the first floating diffusion node FD1 through the quantization path. The second charge signal and the second reset signal can be quantized and read out after the first reset signal at different gains and the first charge signal at different gains are quantized and read out. The second charge signal and the second reset signal can be correlated double sampling and / or non-true correlated double sampling (e.g., the quantization path in the overflow unit 112 is controlled to be closed, so as to quantize and read out the second reset signal based on the first floating diffusion node FD1, and the quantization path is controlled to be opened, so as to quantize and read out the second charge signal based on the first floating diffusion node FD1, so as to realize correlated double sampling of the second charge signal; the quantization path in the overflow unit 112 is controlled to be opened, so as to quantize and read out the second charge signal based on the first floating diffusion node FD1, and the first floating diffusion node FD1 is reset, so as to quantize and read out the second reset signal based on the first floating diffusion node FD1, so as to realize non-true correlated double sampling of the second charge signal). In an optional example, after the quantized readout of the first charge signal at the first gain is completed, the quantized readout of the second charge signal is directly performed without performing a reset operation.

[0168] Embodiment 4

[0169] like Figure 7 As shown, this embodiment provides an image sensor 100 based on gain adjustment, including a plurality of pixel blocks 110 arranged in an array and a node sharing structure 120 .

[0170] The pixel block 110 includes a photosensitive unit 111, an overflow unit 112 and a gain unit 113, and further includes a fourth reset unit 114d and a fourth readout unit 115d; wherein the pixel block 110 includes a floating diffusion node, ie, a first floating diffusion node FD1.

[0171] The photosensitive unit 111 and the gain unit 113 are the same as those in the first embodiment, and the relevant descriptions are detailed in the first embodiment, which will not be repeated here. It should be noted that the first end of the gain transistor M4 in the gain unit 113 of this embodiment is coupled to the fourth reset unit 114d instead of the first reset unit 114a.

[0172] The overflow unit 112 is coupled to the gain unit 113, such as coupled to the low gain quantization node of the gain unit 113, for storing the second charge signal; wherein the overflow unit 112 includes a common path, and the second charge signal is stored in the overflow unit 112 through the common path and transferred to the first floating diffusion node FD1 through the common path.

[0173] As an example, the overflow unit 112 includes an overflow quantization transistor M8 and a third storage device C13; the control end of the overflow quantization transistor M8 receives an overflow quantization control signal OF, the first end is coupled to the low gain quantization node of the gain unit 113, such as, coupled to the first end of the gain transistor M4, and the second end is coupled to the first end of the third storage device C13; the second end of the third storage device C13 is coupled to a reference potential, such as, coupled to the ground potential; wherein the path where the overflow quantization transistor M8 is located is a common path.

[0174] Among them, the third storage device C13 includes a capacitor device, the overflow quantization transistor M8 includes an NMOS tube, the gate of the overflow quantization transistor M8 receives the overflow quantization control signal OF, the drain is connected to the drain of the gain transistor M4, and the source is connected to the first end of the third storage device C13; of course, in other examples, it is also feasible that the overflow quantization transistor M8 includes a PMOS tube, which has no effect on this embodiment.

[0175] The fourth reset unit 114 d is coupled to the first floating diffusion node FD1 through the gain unit 113 , and is used to reset the first floating diffusion node FD1 , the photosensitive unit 111 , and the overflow unit 112 .

[0176] As an example, the fourth reset unit 114d includes a fourth reset transistor M54, a control end receiving a fourth reset control signal RST4, a first end coupled to a seventh power supply potential, and a second end coupled to the gain unit 113, such as coupled to the drain of the gain transistor M4. The fourth reset transistor M54 includes an NMOS tube, a gate receiving the fourth reset control signal RST4, a drain connected to the seventh power supply potential, and a source connected to the drain of the gain transistor M4. The seventh power supply potential is usually the potential of the working voltage and is always a high potential. Of course, in other examples, it is also feasible for the fourth reset transistor M54 to include a PMOS tube, which has no effect on this embodiment.

[0177] The fourth readout unit 115d is coupled to the first floating diffusion node FD1, and is used to quantize and read out at least the first charge signal and the second charge signal transferred to the first floating diffusion node FD1; in an optional scheme, the fourth readout units 115d of the pixel blocks 110 in different rows in the same column are quantized and read out through different column lines.

[0178] As an example, the fourth read-out unit 115d includes a fourth source follower transistor M64 and a fourth selection transistor M74, the control end of the fourth source follower transistor M64 is coupled to the first floating diffusion node FD1, the first end is coupled to the eighth power supply potential, the second end is coupled to the first end of the fourth selection transistor M74, the control end of the fourth selection transistor M74 receives the fourth selection signal SEL4, and the second end is coupled to the corresponding column line.

[0179] Among them, the fourth source follower transistor M64 includes an NMOS tube, the fourth selection transistor M74 includes an NMOS tube, the gate of the fourth source follower transistor M64 is connected to the first floating diffusion node FD1, the drain is connected to the eighth power supply potential, the source is connected to the first end of the fourth selection transistor M74, the gate of the fourth selection transistor M74 receives the fourth selection signal SEL4, the source is connected to the corresponding column line, the eighth power supply potential is usually the potential of the working voltage, and is always a high potential; of course, in other examples, it is also feasible that the fourth source follower transistor M64 includes a PMOS tube and the fourth selection transistor M74 includes a PMOS tube, which has no effect on this embodiment.

[0180] The node sharing structure 120 is coupled between the gain units 113 of at least two pixel blocks 110, and is used to increase the storage capacity of the first floating diffusion node FD1 based on node sharing when the gain unit 113 is turned on, so that the first gain mode has a lower conversion gain, thereby being suitable for situations where the demand for high-light scenes gradually increases.

[0181] In an optional solution, the node sharing structure 120 is coupled between the gain units 113 of the pixel blocks 110 in different rows in the same column; further, the node sharing structure 120 is coupled between the gain units 113 of the pixel blocks 110 in two adjacent rows in the same column.

[0182] As an example, the node sharing structure 120 includes a second connection line 121b and a second switch tube 122b, the second connection line 121b is coupled between the gain units 113 of at least two pixel blocks 110, such as, coupled between the first ends of the gain transistors M4 of two adjacent rows of pixel blocks 110 in the same column, the second switch tube 122b is coupled in series to the second connection line 121b, and its control end receives the second switch control signal SW2. Among them, the second switch tube 122b includes an NMOS tube, of course, the second switch tube 122b includes a PMOS tube is also feasible, which has no effect on this embodiment.

[0183] Correspondingly, such as Figure 8 As shown, this embodiment also provides a control method for an image sensor, including a quantization stage, and further, a reset stage and an exposure stage; wherein the image sensor is implemented using the circuit structure as described above.

[0184] Reset phase:

[0185] A reset operation is performed on the first floating diffusion node FD1 , the photosensitive unit 111 , and the overflow unit 112 .

[0186] For example, the fourth reset transistor M54, the gain transistor M4, the transfer transistor M1 and the overflow quantization transistor M8 are controlled to be turned on, and the first floating diffusion node FD1, the photosensitive element PD and the third storage device C13 are charged to zero to achieve signal reset, and the reset operation is completed. After that, the fourth reset transistor M54 and the transfer transistor M1 are controlled to be turned off.

[0187] Exposure stage:

[0188] The second charge signal is stored in the overflow unit 112 , specifically, the common path is opened, and the second charge signal is stored in the overflow unit 112 through the common path.

[0189] For example, since the overflow quantization transistor M8 is turned on during the reset phase and remains turned on, the common path is opened. At this time, the second charge signal overflowing from the photosensitive element PD in the photosensitive unit 111 is transferred through the common path to the third storage device C13 of the overflow unit 112 for storage.

[0190] When the amount of charge sensed by the photosensitive element PD does not reach the overflow state, the converted charge signal includes only the first charge signal, which is stored on the photosensitive element PD. At this time, although the common path is opened, there is no second charge signal transferred to the third storage device C13 through the common path. It can be considered that the corresponding second charge signal in this process is zero. When the amount of charge sensed by the photosensitive element PD reaches the overflow state, the converted charge signal includes the first charge signal and the second charge signal, wherein the first charge signal is stored on the photosensitive element PD, and the second charge signal is transferred to the third storage device C13 through the common path for storage.

[0191] Quantification stage:

[0192] The first charge signal in different gain modes is quantized and read out, and the second charge signal is quantized and read out; wherein, when the gain unit 113 is turned on, the storage capacity of the first floating diffusion node FD1 is increased by node sharing through the node sharing structure 120, and the first floating diffusion node with increased storage capacity is defined as a shared node.

[0193] In one embodiment, the quantization stage includes: first performing non-true correlated double sampling on the second charge signal, and then performing correlated double sampling on the first charge signal in different gain modes to prevent the second charge signal remaining on the first floating diffusion node FD1 from affecting the quantization readout of other signals.

[0194] Specifically, the method includes: controlling the common path and the gain unit 113 in the overflow unit 112 of the readout row to be opened and controlling the node sharing structure 120 to be closed, so as to perform quantized reading of the second charge signal based on the first floating diffusion node FD1, and performing a reset operation on the first floating diffusion node FD1, so as to perform quantized reading of the second reset signal based on the first floating diffusion node FD1;

[0195] The common path in the overflow unit 112 of the control readout line is closed and the node sharing structure 120 is controlled to be opened, the gain unit 113 of the control readout line is turned on and then closed, so as to quantize and read out the first reset signal in the first gain mode and the second gain mode based on the shared node and the first floating diffusion node FD1 respectively, and the gain unit 113 of the control readout line is turned off and then opened, so as to quantize and read out the first charge signal in the second gain mode and the first gain mode based on the first floating diffusion node FD1 and the shared node respectively.

[0196] For example, the node sharing structure 120 is controlled to be closed by controlling the second switch tube 122b to be closed. At the same time, since the gain transistor M4 and the overflow quantization transistor M8 are turned on and remain turned on during the reset phase, the image sensor operates in the first gain mode and the shared path is opened.

[0197] The fourth selection transistor M74 in the fourth readout unit 115d is controlled to be turned on, so as to perform quantization reading of the second charge signal based on the first floating diffusion node FD1; the fourth reset transistor M54 is controlled to be turned on and then turned off, so as to perform a secondary reset operation on the first floating diffusion node FD1, so as to perform quantization reading of the second reset signal based on the first floating diffusion node FD1, and then the overflow quantization transistor M8 is controlled to be turned off;

[0198] The second switch tube 122b is controlled to be turned on and then turned off, so as to quantize and read out the first reset signal in the first gain mode based on the shared node; and the gain transistor M4 is controlled to be turned off, so that the image sensor switches to the second gain mode, so as to quantize and read out the first reset signal in the second gain mode based on the first floating diffusion node FD1;

[0199] The transfer transistor M1 is controlled to be turned on and then turned off to quantize and read out the first charge signal in the second gain mode based on the first floating diffusion node FD1; the gain transistor M4 is controlled to be turned on so that the image sensor switches to the first gain mode again, the transfer transistor M1 is controlled to be turned on and then turned off, and the second switch tube 122b is controlled to be turned on and then turned off to quantize and read out the first charge signal in the first gain mode based on the shared node.

[0200] Embodiment 5

[0201] like Fig. 9As shown, this embodiment provides an image sensor 100 based on gain adjustment, including a plurality of pixel blocks 110 arranged in an array and a node sharing structure 120 .

[0202] With respect to the pixel block 110, the difference between this embodiment and the fourth embodiment is that the overflow unit 112 of this embodiment is coupled to the high gain quantization node of the gain unit 113; specifically: the control end of the overflow quantization transistor M8 receives the overflow quantization control signal OF, the first end is coupled to the high gain quantization node of the gain unit 113, such as, coupled to the second end of the gain transistor M4, the second end is coupled to the first end of the third storage device C13, and the second end of the third storage device C13 is coupled to the reference potential, such as, coupled to the variable potential; wherein the path where the overflow quantization transistor M8 is located is a common path.

[0203] Regarding the node sharing structure 120 , the difference between this embodiment and the fourth embodiment is that the node sharing structure 120 of this embodiment may only include the second connecting line 121 b . Of course, it is also feasible to include the second switch tube 122 b at the same time.

[0204] Correspondingly, such as Fig.10 and Fig.11 As shown, this embodiment also provides a control method for an image sensor, including a quantization stage, and further, a reset stage and an exposure stage; wherein the image sensor is implemented using the circuit structure as described above.

[0205] Reset phase:

[0206] A reset operation is performed on the first floating diffusion node FD1 , the photosensitive unit 111 , and the overflow unit 112 .

[0207] For example, the fourth reset transistor M54, the gain transistor M4, the transfer transistor M1 and the overflow quantization transistor M8 are controlled to be turned on, and the charge of the first floating diffusion node FD1, the photosensitive element PD and the third storage device C13 is cleared to achieve signal reset, and the reset operation is completed. After that, the fourth reset transistor M54, the gain transistor M4 and the transfer transistor M1 are controlled to be turned off.

[0208] Of course, the fourth reset transistor M54 may not be turned off at the end of the reset phase, such as being turned off in the quantization phase. Further, the fourth reset transistor M54 is turned off when the fourth selection transistor M74 in the fourth readout unit 115d is turned on for the first time to avoid crosstalk between other pixel blocks and the corresponding floating diffusion nodes of the current pixel block during the exposure phase.

[0209] Exposure stage:

[0210] The second charge signal is stored in the overflow unit 112 , specifically, the common path is opened, and the second charge signal is stored in the overflow unit 112 through the common path.

[0211] For example, since the overflow quantization transistor M8 is turned on in the reset phase and remains turned on, the common path is opened. At this time, the second charge signal overflowed from the photosensitive element PD in the photosensitive unit 111 is transferred through the common path to the third storage device C13 of the overflow unit 112 for storage. Afterwards, the overflow quantization transistor M8 is controlled to be turned off.

[0212] When the amount of charge sensed by the photosensitive element PD does not reach the overflow state, the converted charge signal includes only the first charge signal, which is stored on the photosensitive element PD. At this time, although the common path is opened, there is no second charge signal transferred to the third storage device C13 through the common path. It can be considered that the corresponding second charge signal in this process is zero. When the amount of charge sensed by the photosensitive element PD reaches the overflow state, the converted charge signal includes the first charge signal and the second charge signal, wherein the first charge signal is stored on the photosensitive element PD, and the second charge signal is transferred to the third storage device C13 through the common path for storage.

[0213] Quantification stage:

[0214] In one embodiment, the quantization stage includes: performing correlated double sampling on the first charge signal in different gain modes, and performing non-true correlated double sampling on the second charge signal.

[0215] Specifically, it includes: controlling the common path of the overflow unit 112 of the readout line to be closed and controlling the node sharing structure 120 to be opened, controlling the gain unit 113 of the readout line to be opened and then closed, so as to respectively perform quantization reading of the first reset signal in the first gain mode and the second gain mode based on the shared node and the first floating diffusion node FD1, and controlling the gain unit 113 of the readout line to be closed and then opened, so as to respectively perform quantization reading of the first charge signal in the second gain mode and the first gain mode based on the first floating diffusion node and the shared node;

[0216] The common path in the overflow unit 112 of the readout row is controlled to be opened and the gain unit 113 is closed to quantize and read out the second charge signal based on the first floating diffusion node FD1, and the first floating diffusion node FD1 is reset to quantize and read out the second reset signal based on the first floating diffusion node FD1.

[0217] It should be noted that when the node sharing structure 120 only includes the second connecting line 121b, there is no need to additionally control the node sharing structure 120 to open, and the node sharing structure 120 is in the open state by default; when the node sharing structure 120 also includes the second switch tube 122b, the node sharing structure 120 is controlled to open by controlling the second switch tube 122b to open.

[0218] Take the node sharing structure 120 including only the second connection line 121b as an example; the gain transistor M4 in the control gain unit 113 is turned on. Since the node sharing structure 120 includes only the second connection line 121b, node sharing is achieved when the gain transistor M4 is turned on, and the image sensor operates in the first gain mode.

[0219] The fourth selection transistor M74 in the fourth readout unit 115d is controlled to be turned on, so as to quantize and read out the first reset signal in the first gain mode based on the shared node; the gain transistor M4 is controlled to be turned off, so that the image sensor is switched to the second gain mode, so as to quantize and read out the first reset signal in the second gain mode based on the first floating diffusion node FD1; the transfer transistor M1 in the photosensitive unit 111 is controlled to be turned on and then turned off, so as to transfer the first charge signal stored in the photosensitive element PD to the first floating diffusion node FD1, so as to quantize and read out the first charge signal in the second gain mode based on the first floating diffusion node FD1; the gain transistor M4 is controlled to be turned on, so as to switch the image sensor to the first gain mode again, and the transfer transistor M1 is controlled to be turned on and then turned off, so as to transfer the first charge signal stored in the photosensitive element PD to the shared node, so as to quantize and read out the first charge signal in the first gain mode based on the shared node;

[0220] The gain transistor M4 is controlled to be closed, and the overflow quantization transistor M8 is controlled to be opened, and the second charge signal stored in the third storage device C13 in the overflow unit 112 is transferred to the first floating diffusion node FD1 through a common path, so as to perform quantization reading of the second charge signal based on the first floating diffusion node FD1; and the fourth reset transistor M54 in the fourth reset unit 114d is controlled to be opened and then closed, and the gain transistor M4 is controlled to be opened and then closed, so as to perform a secondary reset operation on the first floating diffusion node FD1, so as to perform quantization reading of the second reset signal based on the first floating diffusion node FD1.

[0221] In another embodiment, the quantization stage includes: performing correlated double sampling on the first charge signal in different gain modes, and performing correlated double sampling on the second charge signal.

[0222] Specifically, it includes: controlling the common path of the overflow unit 112 of the readout line to be closed and controlling the node sharing structure 120 to be opened, controlling the gain unit 113 of the readout line to be opened and then closed, so as to respectively perform quantization reading of the first reset signal in the first gain mode and the second gain mode based on the shared node and the first floating diffusion node FD1, and controlling the gain unit 113 of the readout line to be closed and then opened, so as to respectively perform quantization reading of the first charge signal in the second gain mode and the first gain mode based on the first floating diffusion node and the shared node;

[0223] The gain unit 113 is controlled to be closed so as to perform quantized reading of the second reset signal based on the first floating diffusion node FD1, and then the common path in the overflow unit 112 of the readout row is controlled to be opened and then closed, and the second charge signal is transferred to the first floating diffusion node FD1 through the common path so as to perform quantized reading of the second charge signal based on the first floating diffusion node FD1.

[0224] It should be noted that when the node sharing structure 120 only includes the second connecting line 121b, there is no need to additionally control the node sharing structure 120 to open, and the node sharing structure 120 is in the open state by default; when the node sharing structure 120 also includes the second switch tube 122b, the node sharing structure 120 is controlled to open by controlling the second switch tube 122b to open.

[0225] Take the node sharing structure 120 including only the second connection line 121b as an example; the gain transistor M4 in the control gain unit 113 is turned on. Since the node sharing structure 120 includes only the second connection line 121b, node sharing is achieved when the gain transistor M4 is turned on, and the image sensor operates in the first gain mode.

[0226] The fourth selection transistor M74 in the fourth readout unit 115d is controlled to be turned on, so as to quantize and read out the first reset signal in the first gain mode based on the shared node; the gain transistor M4 is controlled to be turned off, so that the image sensor is switched to the second gain mode, so as to quantize and read out the first reset signal in the second gain mode based on the first floating diffusion node FD1; the transfer transistor M1 in the photosensitive unit 111 is controlled to be turned on and then turned off, so as to transfer the first charge signal stored in the photosensitive element PD to the first floating diffusion node FD1, so as to quantize and read out the first charge signal in the second gain mode based on the first floating diffusion node FD1; the gain transistor M4 is controlled to be turned on, so as to switch the image sensor to the first gain mode again, and the transfer transistor M1 is controlled to be turned on and then turned off, so as to transfer the first charge signal stored in the photosensitive element PD to the shared node, so as to quantize and read out the first charge signal in the first gain mode based on the shared node;

[0227] The fourth reset transistor M54 is controlled to be turned on and then turned off, and then the gain transistor M4 is controlled to be turned off, and a secondary reset operation is performed on the first floating diffusion node FD1, so as to quantize and read out the second reset signal based on the first floating diffusion node FD1; the overflow quantization transistor M8 is controlled to be turned on, and the second charge signal stored in the third storage device C13 in the overflow unit 112 is transferred to the first floating diffusion node FD1 through a common path, so as to quantize and read out the second charge signal based on the first floating diffusion node FD1. Of course, in other embodiments, both correlated double sampling and non-true correlated double sampling can be performed on the second charge signal; in this case, the second charge signal is usually first correlated double sampling, and then non-true correlated double sampling is performed on the second charge signal.

[0228] In summary, the present invention is a gain-adjustable image sensor, which realizes that when the gain unit is turned on, the node sharing structure is used to increase the storage capacity of the floating diffusion node in the current pixel block through node sharing, thereby being suitable for the situation where the demand for high-light scenes is gradually increasing. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0229] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed in the present invention shall still be covered by the claims of the present invention.

Claims

1. An image sensor based on gain adjustment, characterized in that: It includes a plurality of pixel blocks and a node sharing structure arranged in an array; The pixel block includes a photosensitive unit, an overflow unit and a gain unit, the photosensitive unit and the gain unit are coupled to a first floating diffusion node, the overflow unit is coupled to the photosensitive unit or the gain unit, the photosensitive unit generates a first charge signal and a second charge signal based on photoelectric conversion and stores the first charge signal, the overflow unit is used to store the second charge signal, and the gain unit is used to switch between different gain modes; The node sharing structure is coupled between the gain units of at least two of the pixel blocks, and is used to increase the storage capacity of the first floating diffusion node based on node sharing when the gain unit is turned on.

2. The image sensor based on gain adjustment according to claim 1, characterized in that: When the overflow unit is coupled to the photosensitive unit, the overflow unit includes an overflow path and a quantization path, the second charge signal is stored in the overflow unit through the overflow path and transferred to the second floating diffusion node or the first floating diffusion node through the quantization path, wherein the first charge signal is transferred to the first floating diffusion node.

3. The image sensor based on gain adjustment according to claim 2, characterized in that: The second charge signal is stored in the overflow unit through the overflow path and transferred to the second floating diffusion node through the quantization path, wherein: The first floating diffusion node and the second floating diffusion node belong to the same pixel block, and the pixel block further includes a first reset unit, a second reset unit, a first readout unit, and a second readout unit; the first reset unit is coupled to the first floating diffusion node through the gain unit, and is used to reset the first floating diffusion node and the photosensitive unit; the second reset unit is coupled to the second floating diffusion node, and is used to reset the second floating diffusion node; the first readout unit is coupled to the first floating diffusion node, and is used to at least quantize and read out the first charge signal transferred to the first floating diffusion node; the second readout unit is coupled to the second floating diffusion node, and is used to at least quantize and read out the second charge signal transferred to the second floating diffusion node; the first reset unit and / or the second reset unit are also used to reset the overflow unit; Alternatively, the first floating diffusion node and the second floating diffusion node belong to pixel blocks in different rows in the same column, and the pixel block also includes a third reset unit and a third readout unit; the third reset unit is coupled to the corresponding floating diffusion node through the gain unit, and is used to reset the corresponding floating diffusion node, the photosensitive unit and the overflow unit; the third readout unit is coupled to the corresponding floating diffusion node, and is used to at least quantize and read out the corresponding charge signal transferred to the corresponding floating diffusion node.

4. The image sensor based on gain adjustment according to claim 3, characterized in that: When the pixel block includes a first readout unit and a second readout unit, the first readout unit and the second readout unit are quantized and read out through different column lines; when the pixel block includes a third readout unit, the third readout units of the pixel blocks in different rows in the same column are quantized and read out through different column lines.

5. The image sensor based on gain adjustment according to claim 3, characterized in that: When the first floating diffusion node and the second floating diffusion node belong to pixel blocks in different rows in the same column, the pixel blocks in different rows in the same column include pixel blocks in two adjacent rows in the same column; wherein, among the pixel blocks in two adjacent rows in the same column, the pixel blocks in the upper row always use the floating diffusion nodes corresponding to the pixel blocks in the lower row as their second floating diffusion nodes, or the pixel blocks in the lower row always use the floating diffusion nodes corresponding to the pixel blocks in the upper row as their second floating diffusion nodes, or, the floating diffusion nodes corresponding to the pixel blocks in two rows are each other's second floating diffusion nodes.

6. The image sensor based on gain adjustment according to any one of claims 2 to 5, characterized in that: The overflow unit includes a first overflow transistor, a first quantization transistor and a first storage device; the control end of the first overflow transistor receives a first overflow control signal, the first end is coupled to the photosensitive unit, and the second end is coupled to the first end of the first storage device; the control end of the first quantization transistor receives a first quantization control signal, the first end is coupled to the second floating diffusion node or is coupled to the second floating diffusion node through the gain unit or is coupled to the first floating diffusion node through the corresponding gain unit, and the second end is coupled to the first end of the first storage device; the second end of the first storage device is coupled to a reference potential; wherein the path where the first overflow transistor is located is the overflow path, and the path where the first quantization transistor is located is the quantization path; Alternatively, when the first floating diffusion node and the second floating diffusion node belong to the same pixel block, the overflow unit removes the first quantization transistor, and at this time, the first end of the first storage device is also coupled to the second floating diffusion node.

7. The image sensor based on gain adjustment according to claim 3, characterized in that: When the first floating diffusion node and the second floating diffusion node belong to the pixel blocks in different rows in the same column, the overflow unit includes a second overflow transistor, a second quantization transistor and a second storage device; the control end of the second overflow transistor receives a second overflow control signal, the first end is coupled to the photosensitive unit, and the second end is coupled to the first end of the second storage device; the control end of the second quantization transistor receives a second quantization control signal, the first end is coupled to the second floating diffusion node through the node sharing structure and the gain unit corresponding to the second floating diffusion node, and the second end is coupled to the first end of the second storage device; the second end of the second storage device is coupled to a reference potential; wherein, the path where the second overflow transistor is located is the overflow path, and the path where the second quantization transistor is located is the quantization path.

8. The image sensor based on gain adjustment according to claim 1, characterized in that: The node sharing structure includes a first connection line coupled between the gain units of at least two of the pixel blocks.

9. The image sensor based on gain adjustment according to claim 8, characterized in that: The node sharing structure further includes at least one first switch tube, which is serially coupled to the first connection line and has a control end receiving a first switch control signal.

10. The image sensor based on gain adjustment according to claim 1, characterized in that: When the overflow unit is coupled to the gain unit, the overflow unit includes a common path, the second charge signal is stored in the overflow unit through the common path and transferred to the first floating diffusion node through the common path, wherein the first charge signal is transferred to the first floating diffusion node; The pixel block also includes a fourth reset unit and a fourth readout unit; the fourth reset unit is coupled to the first floating diffusion node through the gain unit, and is used to reset the first floating diffusion node, the photosensitive unit and the overflow unit; the fourth readout unit is coupled to the first floating diffusion node, and is used to quantize and read out at least the first charge signal and the second charge signal transferred to the first floating diffusion node.

11. The image sensor based on gain adjustment according to claim 10, characterized in that: The overflow unit comprises an overflow quantization transistor and a third storage device; the control end of the overflow quantization transistor receives an overflow quantization control signal, the first end is coupled to the high gain quantization node or the low gain quantization node of the gain unit, and the second end is coupled to the first end of the third storage device; The second terminal of the third storage device is coupled to a reference potential; wherein the path where the overflow quantization transistor is located is the common path; When the first end of the overflow quantization transistor is coupled to the high gain quantization node of the gain unit, the node sharing structure includes a second connection line coupled between the gain units of at least two of the pixel blocks; when the first end of the overflow quantization transistor is coupled to the low gain quantization node of the gain unit, the node sharing structure also includes a second switch tube, which is serially coupled to the second connection line, and a control end of which receives a second switch control signal; And / or, the fourth readout units of the pixel blocks in different rows in the same column perform quantization readout through different column lines.

Images