Practical training device and system for deducing attributes of logic gate
By designing the training device of input control module, logic circuit module and measurement module, using multiple logic relationship coverage, the problems of singleness and complexity of traditional logic gate circuit training benches are solved, and the coverage of multiple logic circuit situations is achieved, improving the improvement of the coverage of various logic circuit situations. The maintenance personnel's testing proficiency and logic circuit failure abilities are provided.
Patent Information
- Application Number
- CN202420949556.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-30
- Publication Date
- 2024-12-20
- Estimated Expiration
- 2034-04-30
AI Technical Summary
Traditional logic gate circuit training benches are single and can only be set up with simple and fixed circuits, and cannot effectively train maintenance personnel of complex industrial products. They are not able to cultivate proficiency in different logic circuits, and are time-consuming and labor-consuming. The use of different benches is There are differences in methods, which affects the teaching effect.
Design a training device including an input control module, a logic circuit module and a measurement module. It covers multiple logic relationships, controls the input signals using several switches, combines the output signals of the logic gate, and judges the internal circuit of the logic circuit through the measurement module. Determine the properties of logic gates and realize the coverage of multiple logic circuit situations without disassembling circuit components or setting up multiple sets of pedestals.
Without disassembling line components or setting up multiple sets of trenches, the coverage of multiple logic circuit situations can be achieved, and the maintenance personnel can be improved in testing the principle of logic gates, and provide better services for logic circuit failure. Training efficiency and accuracy.
Smart Images
Figure CN222213556U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of digital electronic technology, in particular to a training device and system for inferring logic gate properties. Background Art
[0002] The traditional logic gate circuit identification, measurement and troubleshooting training bench has a single circuit and can only set up a few simple fixed situations through mechanical means.
[0003] At present, the circuit principles of industrial products are becoming increasingly complex. For example, the logic between different components of complex industrial products such as aircraft are different. In order to train the proficiency of maintenance personnel for various industrial products, it is necessary to make multiple sets of test benches for different logic circuit training cases. This method is not only time-consuming and labor-intensive, but the usage methods of different test benches may vary, which is not conducive to teaching. Utility Model Content
[0004] The technical problem to be solved by the present invention is to provide a practical training device for inferring the properties of logic gates. By covering multiple logical relationships, a variety of logic circuit situations can be realized without disassembling circuit components or setting up multiple sets of test stands, so as to cultivate maintenance personnel's proficiency in testing logic gate principles and provide better services for troubleshooting logic circuits.
[0005] To solve the above technical problems, an embodiment of the present utility model provides a training device for inferring logic gate properties, which is characterized by comprising an input control module, a logic circuit module and a measurement module;
[0006] The input control module includes a plurality of input ports and a plurality of switches, and the signals of the plurality of input ports are controlled by the plurality of switches to be input into the logic circuit module;
[0007] The logic circuit module includes several logic gates and output ports. It receives the signal of the input port and obtains the signal of the output port through the combination of several logic gates. The measurement module measures the on-off of the internal circuit of the logic circuit module to determine the properties of several logic gates.
[0008] As an improvement of the above solution, the input control module includes input ports Vi1 to Vi12 and switches K1 to K12;
[0009] Specifically, the first terminal input port Vi1 of switch K1, the first terminal input port Vi2 of switch K2, the first terminal input port Vi3 of switch K3, the first terminal input port Vi4 of switch K4, the first terminal input port Vi5 of switch K5, the first terminal input port Vi6 of switch K6, the first terminal input port Vi7 of switch K7, the first terminal input port Vi8 of switch K8, the first terminal input port Vi9 of switch K9, the first terminal input port Vi10 of switch K10, the first terminal input port Vi11 of switch K11, and the first terminal input port Vi12 of switch K12.
[0010] As an improvement of the above solution, the logic circuit module includes logic gates U1 to U11 and an output port Vo;
[0011] Specifically, the first input terminal and the second input terminal of the logic gate U1 are connected to the second terminal of the switch K1 and the second terminal of the switch K2, respectively, and the output terminal is connected to the first input terminal of the logic gate U7; the first input terminal and the second input terminal of the logic gate U2 are connected to the second terminal of the switch K3 and the second terminal of the switch K4, respectively, and the output terminal is connected to the second input terminal of the logic gate U7 and the first input terminal of the logic gate U8; the first input terminal and the second input terminal of the logic gate U3 are connected to the second terminal of the switch K5 and the second terminal of the switch K6, respectively, and the output terminal is connected to the second input terminal of the logic gate U8; the first input terminal and the second input terminal of the logic gate U10 are connected to the output terminal of the logic gate U7 and the output terminal of the logic gate U8, respectively; the first input terminal and the second input terminal of the logic gate U4 are connected to the output terminal of the logic gate U7 and the output terminal of the logic gate U8; The first input terminal and the second input terminal are connected to the second terminal of switch K7 and the second terminal of switch K8 respectively; the first input terminal and the second input terminal of logic gate U5 are connected to the second terminal of switch K9 and the second terminal of switch K10 respectively; the first input terminal and the second input terminal of logic gate U6 are connected to the second terminal of switch K11 and the second terminal of switch K12 respectively; the first input terminal, the second input terminal and the third input terminal of logic gate U9 are connected to the output terminal of logic gate U4, the output terminal of logic gate U5 and the output terminal of logic gate U6 respectively; the first input terminal and the second input terminal of logic gate U11 are connected to the output terminal of logic gate U9 and the output terminal of logic gate U10 respectively; and the output terminal of logic gate U11 is connected to output port Vo.
[0012] As an improvement of the above solution, the device further includes a measurement module, and the measurement module includes measurement points X1 to X23;
[0013] Specifically, measurement point X1 is set at the first input terminal of logic gate U1; measurement point X2 is set at the second input terminal of logic gate U1; measurement point X3 is set at the first input terminal of logic gate U2; measurement point X4 is set at the second input terminal of logic gate U2; measurement point X5 is set at the first input terminal of logic gate U3; measurement point X6 is set at the second input terminal of logic gate U3; measurement point X7 is set at the first input terminal of logic gate U4; measurement point X8 is set at the second input terminal of logic gate U4; measurement point X9 is set at the first input terminal of logic gate U5; measurement point X10 is set at the second input terminal of logic gate U5; measurement point X11 is set at the first input terminal of logic gate U6; measurement point X20 is set at the second input terminal of logic gate U5; measurement point X21 is set at the first input terminal of logic gate U6; measurement point X22 is set at the second input terminal of logic gate U6; measurement point X23 is set at the first input terminal of logic gate U6; measurement point X24 is set at the second input terminal of logic gate U6; measurement point X25 is set at the first input terminal of logic gate U6; measurement point X26 is set at the second input terminal of logic gate U6; measurement point X27 is set at the first input terminal of logic gate U4; measurement point X28 is set at the second input terminal of logic gate U4; measurement point X29 is set at the first input terminal of logic gate U5; measurement point X29 is set at the first input terminal of logic gate U5; measurement point X21 is set at the second input terminal of logic gate U6; measurement point X21 is set at the first input terminal of logic gate U6; measurement point X21 is set at the first input terminal of logic gate U6; measurement point X21 is set at the second input terminal of logic gate U6; measurement point X22 is set at the first input terminal of logic gate U6; measurement point X23 is set at the second input terminal of logic gate U6 Point X12 is set at the second input end of logic gate U6; measurement point X13 is set at the output end of logic gate U1; measurement point X14 is set at the output end of logic gate U2; measurement point X15 is set at the output end of logic gate U3; measurement point X16 is set at the output end of logic gate U4; measurement point X17 is set at the output end of logic gate U5; measurement point X18 is set at the output end of logic gate U6; measurement point X19 is set at the output end of logic gate U7; measurement point X20 is set at the output end of logic gate U8; measurement point X21 is set at the output end of logic gate U9; measurement point X22 is set at the output end of logic gate U10; measurement point X23 is set at the output end of logic gate U11.
[0014] As an improvement of the above solution, the logic gate is any one of an AND gate, a NOT gate, an OR gate, a NAND gate, a NOR gate, and an XOR gate.
[0015] The embodiment of the present utility model further provides a training system for inferring logic gate properties, comprising any of the training devices for inferring logic gate properties as described above, and further comprising: a main control device and a logic gate setting device;
[0016] The main control device, the logic gate setting device and the training device for inferring the properties of the logic gate are connected in sequence;
[0017] The main control device provides the logic gate setting device with information of a plurality of logic gates; and the logic gate setting device specifically sets a plurality of logic gates for the logic circuit module according to the information of the plurality of logic gates.
[0018] The beneficial effects of the present utility model are specifically as follows:
[0019] The present invention provides a training device and system for inferring the properties of logic gates. An input control module controls the input port's signal input to a logic circuit module through a plurality of switches. The logic circuit module receives the input port's signal and obtains the output port's signal through a combination of a plurality of logic gates. The measurement module measures the on / off state of the internal circuit of the logic circuit module and judges the properties of a plurality of logic gates. Without disassembling circuit components or setting up multiple sets of test benches, a variety of logic circuit situations can be covered, thereby cultivating maintenance personnel's proficiency in logic gate testing and providing better service for troubleshooting logic circuits. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 This is a schematic diagram of the module structure of a training device for inferring logic gate properties provided by an embodiment of the present utility model;
[0021] Figure 2 This is a circuit structure diagram of a training device for inferring logic gate properties provided by an embodiment of the present invention;
[0022] Figure 3 This is a schematic diagram of the configuration of a logic circuit module provided by an embodiment of the present utility model;
[0023] Figure 4 1 is a schematic diagram of the device structure of a training system for inferring logic gate properties provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0024] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.
[0025] See Figure 1 ,This embodiment provides a training device for inferring logic gate properties, ,characterized in that it includes an input control module, a logic circuit module, and a measurement module;
[0026] The input control module includes a plurality of input ports and a plurality of switches, and the signals of the plurality of input ports are controlled by the plurality of switches to be input into the logic circuit module;
[0027] The logic circuit module includes several logic gates and output ports. It receives the signal of the input port and obtains the signal of the output port through the combination of several logic gates. The measurement module measures the on-off of the internal circuit of the logic circuit module to determine the properties of several logic gates.
[0028] In this solution, the input control module controls the input port signal, while the logic circuit module combines multiple logic gates to achieve multi-logic coverage and output port signals. Trainees can determine the properties of multiple logic gates by measuring the continuity of the logic circuit module's internal circuits. This allows for coverage of various circuit scenarios without disassembling circuit components or setting up multiple test benches, thereby cultivating maintenance personnel's proficiency in logic gate testing and providing improved troubleshooting services for logic circuits.
[0029] See Figure 2 , Figure 2 This is a schematic diagram of the circuit structure of a training device for inferring logic gate properties, provided by one embodiment of the present invention. The training device provided by this utility model can generate a variety of logic circuit scenarios, each of which has corresponding circuit configurations in many electronic products. Using this training device, trainees can master various logic circuit scenarios and more accurately determine logic gate properties, thereby improving the efficiency and accuracy of actual maintenance processes.
[0030] Preferably, the input control module includes input ports Vi1 to Vi12 and switches K1 to K12;
[0031] Specifically, the first terminal input port Vi1 of switch K1, the first terminal input port Vi2 of switch K2, the first terminal input port Vi3 of switch K3, the first terminal input port Vi4 of switch K4, the first terminal input port Vi5 of switch K5, the first terminal input port Vi6 of switch K6, the first terminal input port Vi7 of switch K7, the first terminal input port Vi8 of switch K8, the first terminal input port Vi9 of switch K9, the first terminal input port Vi10 of switch K10, the first terminal input port Vi11 of switch K11, and the first terminal input port Vi12 of switch K12.
[0032] Furthermore, as a preferred embodiment, the logic circuit module includes logic gates U1 to U11 and an output port Vo;
[0033] Specifically, the first input terminal and the second input terminal of the logic gate U1 are connected to the second terminal of the switch K1 and the second terminal of the switch K2, respectively, and the output terminal is connected to the first input terminal of the logic gate U7; the first input terminal and the second input terminal of the logic gate U2 are connected to the second terminal of the switch K3 and the second terminal of the switch K4, respectively, and the output terminal is connected to the second input terminal of the logic gate U7 and the first input terminal of the logic gate U8; the first input terminal and the second input terminal of the logic gate U3 are connected to the second terminal of the switch K5 and the second terminal of the switch K6, respectively, and the output terminal is connected to the second input terminal of the logic gate U8; the first input terminal and the second input terminal of the logic gate U10 are connected to the output terminal of the logic gate U7 and the output terminal of the logic gate U8, respectively; the first input terminal and the second input terminal of the logic gate U4 are connected to the output terminal of the logic gate U7 and the output terminal of the logic gate U8; The first input terminal and the second input terminal are connected to the second terminal of switch K7 and the second terminal of switch K8 respectively; the first input terminal and the second input terminal of logic gate U5 are connected to the second terminal of switch K9 and the second terminal of switch K10 respectively; the first input terminal and the second input terminal of logic gate U6 are connected to the second terminal of switch K11 and the second terminal of switch K12 respectively; the first input terminal, the second input terminal and the third input terminal of logic gate U9 are connected to the output terminal of logic gate U4, the output terminal of logic gate U5 and the output terminal of logic gate U6 respectively; the first input terminal and the second input terminal of logic gate U11 are connected to the output terminal of logic gate U9 and the output terminal of logic gate U10 respectively; and the output terminal of logic gate U11 is connected to output port Vo.
[0034] Preferably, the logic gate is any one of an AND gate, a NOT gate, an OR gate, a NAND gate, a NOR gate, and an XOR gate.
[0035] For example, see Figure 3 Logic gates U1, U3, and U10 are NOR gates; logic gates U2 and U8 are OR gates; logic gates U4, U6, and U7 are NAND gates; logic gates U5 and U11 are XOR gates; and logic gate U9 is an XNOR gate. By configuring specific logic gates, multiple logic coverage of the circuit can be achieved.
[0036] Preferably, the measurement module includes measurement points X1 to X23;
[0037] Specifically, measurement point X1 is set at the first input terminal of logic gate U1; measurement point X2 is set at the second input terminal of logic gate U1; measurement point X3 is set at the first input terminal of logic gate U2; measurement point X4 is set at the second input terminal of logic gate U2; measurement point X5 is set at the first input terminal of logic gate U3; measurement point X6 is set at the second input terminal of logic gate U3; measurement point X7 is set at the first input terminal of logic gate U4; measurement point X8 is set at the second input terminal of logic gate U4; measurement point X9 is set at the first input terminal of logic gate U5; measurement point X10 is set at the second input terminal of logic gate U5; measurement point X11 is set at the first input terminal of logic gate U6; measurement point X20 is set at the second input terminal of logic gate U5; measurement point X21 is set at the first input terminal of logic gate U6; measurement point X22 is set at the second input terminal of logic gate U6; measurement point X23 is set at the first input terminal of logic gate U6; measurement point X24 is set at the second input terminal of logic gate U6; measurement point X25 is set at the first input terminal of logic gate U6; measurement point X26 is set at the second input terminal of logic gate U6; measurement point X27 is set at the first input terminal of logic gate U4; measurement point X28 is set at the second input terminal of logic gate U4; measurement point X29 is set at the first input terminal of logic gate U5; measurement point X29 is set at the first input terminal of logic gate U5; measurement point X21 is set at the second input terminal of logic gate U6; measurement point X21 is set at the first input terminal of logic gate U6; measurement point X21 is set at the first input terminal of logic gate U6; measurement point X21 is set at the second input terminal of logic gate U6; measurement point X22 is set at the first input terminal of logic gate U6; measurement point X23 is set at the second input terminal of logic gate U6 Point X12 is set at the second input end of logic gate U6; measurement point X13 is set at the output end of logic gate U1; measurement point X14 is set at the output end of logic gate U2; measurement point X15 is set at the output end of logic gate U3; measurement point X16 is set at the output end of logic gate U4; measurement point X17 is set at the output end of logic gate U5; measurement point X18 is set at the output end of logic gate U6; measurement point X19 is set at the output end of logic gate U7; measurement point X20 is set at the output end of logic gate U8; measurement point X21 is set at the output end of logic gate U9; measurement point X22 is set at the output end of logic gate U10; measurement point X23 is set at the output end of logic gate U11.
[0038] In the above scheme, the measurement points are set at the input and output ends of several logic gates. The trainees can use several switches to control the input of the logic circuit module, and determine the logic gate placed at the corresponding position by detecting the input and output signals of each logic gate. They can also determine the logic gate placed at the corresponding position by detecting the input and output signals of the combination of multiple logic gates. During training, the trainees can determine the logic gate placed at each logic gate position by detecting and analyzing the circuit of the logic gate circuit training device provided by the embodiment of the utility model, which can cultivate the maintenance personnel's understanding of the logic gate principle and exercise their proficiency in line maintenance.
[0039] See Figure 4 ,This embodiment also provides a training system for inferring logic gate properties, including the training device for inferring logic gate properties as described above, and further including: a main control device and a logic gate setting device;
[0040] The main control device, the logic gate setting device and the training device for inferring the properties of the logic gate are connected in sequence;
[0041] The main control device provides the logic gate setting device with information of a plurality of logic gates; and the logic gate setting device specifically sets a plurality of logic gates for the logic circuit module according to the information of the plurality of logic gates.
[0042] In the above scheme, the user of the training system for inferring logic gate properties can set the information of several logic gates in the main control device. The main control device provides the information of the several logic gates to the logic gate setting device, and the logic gate setting device sets specific logic gates in the training device for inferring logic gate properties. The main control device can set multiple sets of logic gate information and ultimately set different logic gates on the training device for inferring logic gate properties. For the trainers, the logic gates placed at various positions in the training device for inferring logic gate properties are unknown and need to be analyzed through circuit measurement. Using the training system for inferring logic gate properties provided by this embodiment can cultivate maintenance personnel's proficiency in logic gate testing and provide better services for troubleshooting logic circuits.
[0043] As an example, a main control device of a training system for inferring logic gate properties provided by an embodiment of the present invention includes information on each logic gate and information on multiple sets of logic gates. When trainees use the system, the main control device can randomly select one set of information from the multiple sets of logic gates and provide it to the logic gate setting device, or randomly select a corresponding number of logic gates based on the information of each logic gate and provide them to the logic gate setting device; the logic gate setting device places corresponding logic gates at corresponding positions of the training device for inferring logic gate properties based on the information of the logic gates, and the trainees judge the properties of the logic gates placed at each position by detecting the measurement points.
[0044] In an embodiment of the present invention, a master control device, a logic gate setting device, and a training device for inferring logic gate properties are sequentially connected. This provides the training device with information about several logic gates and sets corresponding logic gates at corresponding locations, achieving multi-logic coverage. Signals are then output through output ports. This covers a wide range of circuit scenarios without requiring disassembly of circuit components or the installation of multiple test benches, thereby cultivating maintenance personnel's proficiency in logic gate testing and providing improved troubleshooting services for logic circuits.
[0045] The above description is only a preferred embodiment of the present invention. The present invention is not limited to the above embodiment. During the implementation process, there may be changes in the circuit model, drive signal and related parameters. If the changes or deformations of the present invention do not depart from the spirit and scope of the present invention and fall within the scope of the claims and equivalent technologies of the present invention, the present invention is also intended to include these changes and deformations.
[0046] In the description of this specification, the reference terms "one embodiment," "some embodiments," "example," "specific example," or "some examples" mean that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. Moreover, the specific features, structures, materials, or characteristics described may be combined in any appropriate manner in any one or more embodiments or examples. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification, as well as features of different embodiments or examples, unless they are mutually inconsistent.
[0047] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.
Claims
1. A training device for inferring the properties of logic gates, characterized in that: It includes an input control module, a logic circuit module and a measurement module; The input control module includes a plurality of input ports and a plurality of switches, and the signals of the plurality of input ports are controlled by the plurality of switches to be input into the logic circuit module; The logic circuit module includes several logic gates and output ports, which receives the signal of the input port, obtains the signal of the output port through the combination of several logic gates, and measures the on-off of the internal circuit of the logic circuit module through the measurement module to judge the properties of several logic gates.
2. A training device for inferring logic gate properties as claimed in claim 1, characterized in that: The input control module includes input ports Vi1-Vi12 and switches K1-K12; Specifically, the first terminal input port Vi1 of switch K1, the first terminal input port Vi2 of switch K2, the first terminal input port Vi3 of switch K3, the first terminal input port Vi4 of switch K4, the first terminal input port Vi5 of switch K5, the first terminal input port Vi6 of switch K6, the first terminal input port Vi7 of switch K7, the first terminal input port Vi8 of switch K8, the first terminal input port Vi9 of switch K9, the first terminal input port Vi10 of switch K10, the first terminal input port Vi11 of switch K11, and the first terminal input port Vi12 of switch K12.
3. A training device for inferring logic gate properties as claimed in claim 2, characterized in that: The logic circuit module includes logic gates U1 to U11 and an output port Vo; Specifically, the first input terminal and the second input terminal of the logic gate U1 are respectively connected to the second terminal of the switch K1 and the second terminal of the switch K2, and the output terminal is connected to the first input terminal of the logic gate U7; the first input terminal and the second input terminal of the logic gate U2 are respectively connected to the second terminal of the switch K3 and the second terminal of the switch K4, and the output terminal is connected to the second input terminal of the logic gate U7 and the first input terminal of the logic gate U8; the first input terminal and the second input terminal of the logic gate U3 are respectively connected to the second terminal of the switch K5 and the second terminal of the switch K6, and the output terminal is connected to the second input terminal of the logic gate U8; the first input terminal and the second input terminal of the logic gate U10 are respectively connected to the output terminal of the logic gate U7 and the output terminal of the logic gate U8; The first input terminal and the second input terminal are connected to the second terminal of the switch K7 and the second terminal of the switch K8 respectively; the first input terminal and the second input terminal of the logic gate U5 are connected to the second terminal of the switch K9 and the second terminal of the switch K10 respectively; the first input terminal and the second input terminal of the logic gate U6 are connected to the second terminal of the switch K11 and the second terminal of the switch K12 respectively; the first input terminal, the second input terminal and the third input terminal of the logic gate U9 are connected to the output terminal of the logic gate U4, the output terminal of the logic gate U5 and the output terminal of the logic gate U6 respectively; the first input terminal and the second input terminal of the logic gate U11 are connected to the output terminal of the logic gate U9 and the output terminal of the logic gate U10 respectively; the output terminal of the logic gate U11 is connected to the output port Vo.
4. A training device for inferring logic gate properties as claimed in claim 3, characterized in that: The measurement module includes measurement points X1 to X23; Specifically, the measuring point X1 is set at the first input terminal of the logic gate U1; the measuring point X2 is set at the second input terminal of the logic gate U1; the measuring point X3 is set at the first input terminal of the logic gate U2; the measuring point X4 is set at the second input terminal of the logic gate U2; the measuring point X5 is set at the first input terminal of the logic gate U3; the measuring point X6 is set at the second input terminal of the logic gate U3; the measuring point X7 is set at the first input terminal of the logic gate U4; the measuring point X8 is set at the second input terminal of the logic gate U4; the measuring point X9 is set at the first input terminal of the logic gate U5; the measuring point X10 is set at the second input terminal of the logic gate U5; the measuring point X11 is set at the first input terminal of the logic gate U6; the measuring point X12 is set at the second input terminal of the logic gate U6; the measuring point X13 is set at the first input terminal of the logic gate U6; the measuring point X14 is set at the second input terminal of the logic gate U6; the measuring point X15 is set at the first input terminal of the logic gate U6; the measuring point X16 is set at the second input terminal of the logic gate U6; the measuring point X17 is set at the first input terminal of the logic gate U6; the measuring point X18 is set at the second input terminal of the logic gate U6; the measuring point X19 is set at the first input terminal of the logic gate U6; the measuring point X20 is set at the second input terminal of the logic gate U6; the measuring point X21 is set at the first input terminal of the logic gate U6; the measuring point X22 is set at the second input terminal of the logic gate U6; the measuring point X23 is set at the first input terminal of the logic gate U6; the measuring point X24 is set at the second input terminal of the logic gate U6; the measuring point X25 is set at the first input terminal of the logic gate U6; the measuring point X26 is set at the second input terminal of the logic gate U Point X12 is set at the second input terminal of logic gate U6; measurement point X13 is set at the output terminal of logic gate U1; measurement point X14 is set at the output terminal of logic gate U2; measurement point X15 is set at the output terminal of logic gate U3; measurement point X16 is set at the output terminal of logic gate U4; measurement point X17 is set at the output terminal of logic gate U5; measurement point X18 is set at the output terminal of logic gate U6; measurement point X19 is set at the output terminal of logic gate U7; measurement point X20 is set at the output terminal of logic gate U8; measurement point X21 is set at the output terminal of logic gate U9; measurement point X22 is set at the output terminal of logic gate U10; measurement point X23 is set at the output terminal of logic gate U11.
5. A training device for inferring logic gate properties as claimed in claim 1, characterized in that: The logic gate is any one of an AND gate, a NOT gate, an OR gate, a NAND gate, a NOR gate, and an XOR gate.
6. A training system for inferring the properties of logic gates, characterized in that: The training system for inferring logic gate properties comprises the training device for inferring logic gate properties according to any one of claims 1 to 5, and further comprises: a main control device and a logic gate setting device; The main control device, the logic gate setting device and the training device for inferring the properties of the logic gate are connected in sequence; The main control device provides the logic gate setting device with information of a plurality of logic gates; and the logic gate setting device specifically sets a plurality of logic gates for the logic circuit module according to the information of the plurality of logic gates.