Transistor, display circuit, and electronic device

Abstract

The utility model discloses a transistor, a display circuit and electronic equipment. The transistor comprises an active layer, a first electrode and a second electrode; the first electrode is arranged on the active layer; the second electrode comprises a first sub-electrode and a second sub-electrode which are arranged on the same layer, and the first sub-electrode and the second sub-electrode are located on the two sides of the first electrode in the thickness direction respectively; the orthographic projection of the first sub-electrode and / or the second sub-electrode in the thickness direction is not overlapped with the orthographic projection of the active layer in the thickness direction.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a transistor, a display circuit, and an electronic device. Background Art

[0002] As electronic devices are increasingly pursuing thinner and lighter devices, the size of the driver IC in OLED displays is reduced to achieve the effect of making the overall device thinner and lighter and reducing costs. For example, the connection pins of the driver IC are compressed through time-sharing multiplexing of multiple switching transistors, thereby reducing the size of the driver IC and design costs.

[0003] However, the structure of the multi-way switch transistor has a large amount of parasitic capacitance, which affects the flow rate of current in the transistor. Utility Model Content

[0004] The first aspect of the present application provides a transistor comprising

[0005] active layer;

[0006] a first electrode, disposed on the active layer;

[0007] a second electrode, the second electrode including a first sub-electrode and a second sub-electrode provided in the same layer, the first sub-electrode and the second sub-electrode being respectively located on both sides of the first electrode in a thickness direction;

[0008] An orthographic projection of the first sub-electrode and / or the second sub-electrode along the thickness direction does not overlap with an orthographic projection of the active layer along the thickness direction.

[0009] In some modified implementations of the first aspect of the present application, in the aforementioned transistor, the side of the first sub-electrode and / or the second sub-electrode facing away from the active layer is a flat surface.

[0010] In some modified implementations of the first aspect of the present application, the aforementioned transistor further includes a conductive layer, and two ends of the conductive layer are respectively connected to the second electrode and the active layer.

[0011] In some modified embodiments of the first aspect of the present application, in the aforementioned transistor, the first sub-electrode and / or the second sub-electrode are in a plane parallel to the active layer, and the orthographic projection of one end of the first electrode along the thickness direction is adjacent to the edge of the orthographic projection of the active layer along the thickness direction.

[0012] In some modified embodiments of the first aspect of the present application, the aforementioned transistor, wherein the first sub-electrode and / or the second sub-electrode are arranged with an orthographic projection of one end of the first electrode along the thickness direction in a plane parallel to the active layer and spaced apart from the edge of the orthographic projection of the active layer along the thickness direction.

[0013] In some modified implementations of the first aspect of the present application, the aforementioned transistor further includes a first insulating layer and / or a second insulating layer;

[0014] The first insulating layer is provided on a side of the second electrode facing the active layer;

[0015] The second insulating layer is disposed between the first electrode and the active layer.

[0016] In some modified embodiments of the first aspect of the present application, the aforementioned transistor further includes a glass substrate;

[0017] The glass substrate is disposed on a side of the active layer away from the first electrode.

[0018] A second aspect of the present application provides a display circuit comprising a first column of pixel units, a second column of pixel units, and at least one multi-way switch group;

[0019] The multi-way switch group includes a first multi-way switch and a second multi-way switch connected in parallel with each other, the first multi-way switch is used to connect the first column of pixel units in series, and the second multi-way switch is used to connect the second column of pixel units in series;

[0020] The first multi-way switch and / or the second multi-way switch includes a transistor, wherein the transistor includes an active layer, a first electrode, and a second electrode, wherein the second electrode includes a first sub-electrode and a second sub-electrode provided in the same layer, and the first sub-electrode and the second sub-electrode are respectively located on both sides of the first electrode in a thickness direction;

[0021] An orthographic projection of the first sub-electrode and / or the second sub-electrode along the thickness direction does not overlap with an orthographic projection of the active layer along the thickness direction.

[0022] In some modified implementations of the second aspect of the present application, in the aforementioned display circuit, the first column of pixel units includes red pixel units and blue pixel units that are alternately arranged;

[0023] The second pixel unit includes a plurality of green pixel units.

[0024] The third aspect of the present application provides an electronic device, which includes

[0025] A display panel, wherein a display circuit is provided in the display panel;

[0026] The display circuit includes a first column of pixel units, a second column of pixel units and at least one multi-way switch group;

[0027] The multi-way switch group includes a first multi-way switch and a second multi-way switch connected in parallel with each other, the first multi-way switch is used to connect the first column of pixel units in series, and the second multi-way switch is used to connect the second column of pixel units in series;

[0028] The first multi-way switch and / or the second multi-way switch includes a transistor, wherein the transistor includes an active layer, a first electrode, and a second electrode, wherein the second electrode includes a first sub-electrode and a second sub-electrode provided in the same layer, and the first sub-electrode and the second sub-electrode are respectively located on both sides of the first electrode in a thickness direction;

[0029] An orthographic projection of the first sub-electrode and / or the second sub-electrode along the thickness direction does not overlap with an orthographic projection of the active layer along the thickness direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other objects, features and advantages of the exemplary embodiments of the present application will become readily understood by reading the detailed description below with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present application are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0031] Figure 1 Schematically shows a first structural diagram of a transistor provided in an embodiment of the present application;

[0032] Figure 2 Schematically shows a second structural diagram of a transistor provided in an embodiment of the present application;

[0033] Figure 3 Schematically shows a third structural diagram of a transistor provided in an embodiment of the present application;

[0034] Figure 4 The structure diagram of the display circuit provided in the embodiment of the present application is schematically shown;

[0035] Figure 5 The following schematically shows a working signal diagram of a display circuit according to an embodiment of the present application;

[0036] Explanation of the accompanying drawings: active layer 1, first electrode 2, second electrode 3, first sub-electrode 31, second sub-electrode 32, conductive layer 4, first insulating layer 5, second insulating layer 6, third insulating layer 7, glass substrate 8, first column of pixel units 9, red pixel units 91, blue pixel units 92, second column of pixel units 10, green pixel units 101, first multiplexer 11, second multiplexer 12. DETAILED DESCRIPTION

[0037] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0038] It should be noted that, unless otherwise specified, the technical or scientific terms used in this application should have the common meanings understood by those skilled in the art to which this application belongs.

[0039] As electronic devices are increasingly pursuing thinner and lighter devices, the size of the driver IC in OLED displays is reduced to achieve the effect of making the overall device thinner and lighter and reducing costs. For example, the connection pins of the driver IC are compressed through time-sharing multiplexing of multiple switching transistors, thereby reducing the size of the driver IC and design costs.

[0040] However, the inventors of this application discovered that in terms of the traditional structure of the transistor, the source and drain are located above the gate and are connected to the active layer through vias, and thus there is a first parasitic capacitance in the stacking relationship between the gate and the active layer, a second parasitic capacitance in the stacking relationship between the active layer and the source and drain, and a third parasitic capacitance in the adjacent relationship between the gate and the source and drain. All three parasitic capacitances will affect the flow rate of current in the transistor.

[0041] The technical solution of the embodiment of the present application is to solve the above technical problems, and the overall idea is as follows:

[0042] In some embodiments, refer to the attached Figure 2 and attached Figure 1 The transistor provided in an embodiment of the present application includes an active layer 1, a first electrode 2 and a second electrode 3; the first electrode 2 is arranged on the active layer 1; the second electrode 3 includes a first sub-electrode 31 and a second sub-electrode 32 arranged in the same layer, and the first sub-electrode 31 and the second sub-electrode 32 are respectively located on both sides of the first electrode 2 in the thickness direction; the orthographic projection of the first sub-electrode 31 and / or the second sub-electrode 32 along the thickness direction does not overlap with the orthographic projection of the active layer 1 along the thickness direction.

[0043] In the transistor provided in this embodiment, the second electrode 3 is configured to include a first sub-electrode 31 and a second sub-electrode 32, and the first sub-electrode 31 and / or the second sub-electrode 32 are configured so that the positive projection in the thickness direction of the first electrode 2 does not overlap with the positive projection of the active layer 1 in the same direction, thereby reducing the distance between the first sub-electrode 31 and the active layer 1, and / or between the second sub-electrode 32 and the active layer 1, and then reducing the parasitic capacitance between the first sub-electrode 31 and the active layer 1, and / or between the second sub-electrode 32 and the active layer 1, thereby reducing the influence of the parasitic capacitance on the current flow rate, so that the current flow rate that can pass through the transistor can be effectively increased.

[0044] Among them, a transistor is a solid semiconductor device that can have multiple functions such as detection, rectification, amplification, switching, voltage stabilization, and signal modulation. The transistor can be used as a variable current switch to control the output current based on the input voltage and is often used in display circuits. Its structure and working principle can be easily understood by those skilled in the art and will not be elaborated on here.

[0045] In this embodiment, the active layer 1 can be made of, but is not limited to, polysilicon (Poly-Si) material.

[0046] The first electrode 2 can be provided on the active layer 1 as a gate structure of the transistor, and the first electrode 2 can be any conductive metal; it can be understood that the thickness direction of the first electrode 2 is Figure 1 Middle up and down direction a.

[0047] Among them, the second electrode 3 including the first sub-electrode 31 and the second sub-electrode 32 serves as the source and drain of the transistor. One of the first sub-electrode 31 and the second sub-electrode 32 is the source and the other is the drain. The specific corresponding relationship can be designed and adjusted according to actual needs. In this embodiment, the second electrode 3 can be arranged in the same layer as the first electrode 2. In this embodiment, the first sub-electrode 31 and the second sub-electrode 32 can be respectively arranged on both sides of the straight line in the thickness direction of the first electrode 2. Figure 1 The left and right sides b in the diagram can also be the two sides of the inclined direction with a certain angle to the left and right directions, as long as the on-off requirements of the transistor are guaranteed. As for the transistor, there is a first parasitic capacitance in the stacking relationship between the active layer 1 and the first electrode 2, a second parasitic capacitance in the stacking relationship between the active layer 1 and the second electrode 3, and a third parasitic capacitance in the adjacent relationship between the first electrode 2 and the second electrode 3. The three parasitic capacitances will affect the flow rate of the current in the transistor. In this embodiment, at least one of the first sub-electrode 31 and the second sub-electrode 32 is set to have no projection overlap with the active layer 1 in the thickness direction of the first electrode 2, that is, no stacking correspondence, that is, it can be Figure 2The first sub-electrode 31 shown has no overlapping relationship with the active layer 1, and can be Figure 2 Similarly, the second sub-electrode 32 has no overlapping relationship with the active layer 1, or it can be Figure 1 The first sub-electrode 31 and the second sub-electrode 32 shown have no projection overlap with the active layer 1 , which can effectively reduce the second parasitic capacitance and thus increase the flow rate of current in the transistor.

[0048] The orthographic projection is a projection generated when the parallel projection line is perpendicular to the projection plane. The orthographic projection in this embodiment may be a projection generated when the parallel projection line is perpendicular to the active layer or the second electrode.

[0049] According to the above, the transistor provided in the first aspect of the present application sets at least one of the first sub-electrode 31 and the second sub-electrode 32 in a form in which the orthographic projection along the thickness direction of the first electrode 2 has no overlap with the active layer 1 in the same direction, thereby effectively reducing the parasitic capacitance between the second electrode 3 and the active layer 1, thereby effectively increasing the flow rate of current in the transistor.

[0050] The term "and / or" in this article is merely a description of the association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B is specifically understood as: A and B may be included at the same time, A may exist alone, or B may exist alone, and any of the above three situations may exist.

[0051] In some embodiments, refer to the attached Figure 2 In the transistor provided in this embodiment, in a specific implementation, the side of the first sub-electrode 31 and / or the second sub-electrode 32 facing away from the active layer 1 can be a flat surface.

[0052] Specifically, in order to achieve a form in which at least one of the first sub-electrode 31 and the second sub-electrode 32 is configured such that the orthographic projection along the thickness direction of the first electrode 2 does not overlap with the active layer 1 in the same direction, in this embodiment, at least one of the first sub-electrode 31 and the second sub-electrode 32 can be configured so that the side away from the active layer 1 is a flat surface, that is, a whole block or whole surface electrode film layer structure design without notches or vias; it can be understood that when one of the first sub-electrode 31 and the second sub-electrode 32 is a whole block or whole surface electrode film layer structure, the other can have the following configuration:

[0053] In one possible case, Figure 2The setting shown is a setting form with a via in the middle. Under this setting, the via can be used to set the conductive layer 4 to achieve the connection between the conductive layer 4 and the active layer 1, thereby ensuring the conduction of the entire transistor. Under this setting, the conductive layer 4 needs to be connected to the active layer 1 using a via, and then at least the part of the sub-electrode along the thickness direction of the first electrode 2 that is located on one side of the via has an overlapping positive projection in the thickness direction of the first electrode 2 and an positive projection of the active layer 1 in the same direction, and then it is necessary to rely on another sub-electrode without a via design to reduce the second parasitic capacitance.

[0054] In one possible case, the other sub-electrode is also configured as a whole or a solid electrode film layer structure. Under this configuration, both sub-electrodes can reduce the second parasitic electrode.

[0055] Further, refer to the attached Figure 2 and attached Figure 1 In a specific implementation of the transistor provided in this embodiment, the conductive layer 4 has two ends connected to the second electrode 3 and the active layer 1 respectively.

[0056] Specifically, in order to achieve conduction of the transistor, a conductive layer 4 is provided in this embodiment. The conductive layer 4 has conductivity and can be, but is not limited to, indium tin oxide (ITO). Its two ends are respectively connected to the second electrode 3 and the active layer 1. Corresponding to the configuration of the aforementioned second electrode 3, the conductive layer 4 can have the following configurations:

[0057] In one possible case, when the first sub-electrode 31 is set to a whole block or whole surface electrode film structure, and the second sub-electrode 32 is set to have a via hole, the conductive layer 4 is set to a relatively flat whole block or whole surface film structure corresponding to the first sub-electrode 31, and the left and right ends are respectively connected to the first sub-electrode 31 and the active layer 1, specifically covering the side surface of the overlapping sub-electrode facing away from the active layer 1 and the side surface of the active layer 1 facing the sub-electrode; the conductive layer 4 is set to pass through the via hole corresponding to the second sub-electrode 32, and the upper and lower ends of the conductive layer 4 are respectively connected to the second sub-electrode 32 and the active layer 1, specifically covering the side surface of the overlapping sub-electrode facing away from the active layer 1 and the side surface of the active layer 1 facing the sub-electrode;

[0058] In another possible scenario, when the second sub-electrode 32 is configured as a monolithic or full-surface electrode film structure and the first sub-electrode 31 is configured with a via, the configuration of the conductive layer 4 is interchangeably adjusted with reference to the first scenario. In a third scenario, when both the first sub-electrode 31 and the second sub-electrode 32 are configured as monolithic or full-surface electrode film structures, the conductive layer 4 is configured as a relatively flat monolithic or full-surface ground structure.

[0059] It should be noted that this application does not specifically limit the types of the first sub-electrode 31 and / or the second sub-electrode 32. Those skilled in the art may adjust their types based on actual circumstances. The above examples are merely illustrative of the possible types of the first sub-electrode 31 and / or the second sub-electrode 32 in this application, and are not limited to those described in the above embodiments.

[0060] Furthermore, in the transistor provided in this embodiment, in a specific implementation, the first sub-electrode 31 and / or the second sub-electrode 32 is adjacent to the edge of the orthographic projection of the active layer 1 along the thickness direction toward one end of the first electrode 2 in a plane parallel to the active layer 1.

[0061] Specifically, in order to achieve non-overlapping relationship between the projection of at least one of the first sub-electrode 31 and the second sub-electrode 32 and the active layer 1, in this embodiment, when setting the first sub-electrode 31 and the second sub-electrode 32, the projection edge of at least one of them can be adjacent to the projection edge of the active layer 1, that is, just connected but without overlapping. Of course, the projection of the other sub-electrode can be set at intervals with the projection of the active layer 1, can be set adjacent to it, or can be set overlappingly. When set at intervals, the third parasitic capacitance between the first electrode 2 and the second electrode 3 can be reduced.

[0062] Further, refer to the attached Figure 1 In the transistor provided in this embodiment, in a specific implementation, the first sub-electrode 31 and / or the second sub-electrode 32 are arranged in a plane parallel to the active layer 1, with the orthographic projection of one end of the first electrode 2 along the thickness direction being spaced apart from the edge of the orthographic projection of the active layer 1 along the thickness direction.

[0063] Specifically, to further reduce the parasitic capacitance within the transistor, in this embodiment, at least one of the first sub-electrode 31 and the second sub-electrode 32 is set so that the projected edge is spaced apart from the projected edge of the active layer 1. That is, it can be understood that at least one of the first sub-electrode 31 and the second sub-electrode 32 is translated toward the outer edge of the active layer 1 in a plane parallel to the active layer 1, and thus the distance between at least one sub-electrode and the first electrode 2 in a plane parallel to the active layer 1 is increased, thereby reducing the third parasitic capacitance between the first electrode 2 and the second electrode 3. Combined with the reduction of the second parasitic capacitance, the flow rate of the current in the transistor is greatly improved.

[0064] Further, refer to the attached Figure 3 In a specific implementation, the transistor provided in this embodiment further includes a first insulating layer 5 and / or a second insulating layer 6; the first insulating layer 5 is arranged on the side of the second electrode 3 facing the active layer 1; the second insulating layer 6 is arranged between the first electrode 2 and the active layer 1.

[0065] Specifically, in order to complete the transistor structure and ensure normal conduction between the gate and the source and drain, a first insulating layer 5 and a second insulating layer 6 are provided in this embodiment. The materials of the first insulating layer 5 and the second insulating layer 6 can be the same or different, for example, they can be a mixture of silicon nitride and silicon oxide. The first insulating layer 5 serves as an isolation layer between the second electrode 3 and the active layer 1, and the second insulating layer 6 serves as an isolation layer between the first electrode 2 and the active layer 1; of course, it can be understood that a third insulating layer 7 is also provided between the conductive layer 4 and the first electrode 2, and the material of the third insulating layer 7 can be the same or different from that of the first two insulating layers, for example, it can be a mixture of silicon nitride and silicon oxide; the third insulating layer 7 can isolate the conductive layer 4 from the first electrode 2 or isolate the second electrode 3 from the first electrode 2, paving the way for other wiring layers above; the above settings can be easily understood by those skilled in the art and will not be elaborated on here.

[0066] Further, refer to the attached Figure 3 In a specific implementation, the transistor provided in this embodiment further includes a glass substrate 8 ; the glass substrate 8 is arranged on a side of the active layer 1 away from the first electrode 2 .

[0067] Specifically, in order to complete the overall structure of the transistor, a glass substrate 8 is provided in this embodiment. The glass substrate 8 is a rigid structure and can be transparent or not according to actual needs. The glass substrate serves as a film-forming carrier for the active layer 1, the first electrode 2, the second electrode 3, the conductive layer 4, the first insulating layer 5, the second insulating layer 6 and the third insulating layer 7.

[0068] Reference Attachment Figure 4 and attached Figure 5 This embodiment provides a display circuit, which includes a first column of pixel units 9, a second column of pixel units 10 and at least one multiplexer switch group; the multiplexer switch group includes a first multiplexer (MUX1) 11 and a second multiplexer (MUX2) 12 connected in parallel, the first multiplexer 11 is used to connect the first column of pixel units 9 in series, and the second multiplexer 12 is used to connect the second column of pixel units 10 in series; the first multiplexer 11 and / or the second multiplexer 12 include transistors, and the transistors include an active layer 1, a first electrode 2 and a second electrode 3, the second electrode 3 includes a first sub-electrode 31 and a second sub-electrode 32 arranged in the same layer, the first sub-electrode 31 and the second sub-electrode 32 are respectively located on both sides of the first electrode 2 in the thickness direction; the orthographic projection of the first sub-electrode 31 and / or the second sub-electrode 32 along the thickness direction does not overlap with the orthographic projection of the active layer 1 along the thickness direction.

[0069] Specifically, as electronic devices are increasingly pursuing the trend of becoming thinner and lighter, the connection pins of the driver IC are compressed by time-sharing multiplexing of the multiplexer, thereby effectively reducing the size and design cost of the driver IC. However, the time-sharing multiplexing of the multiplexer will limit the refresh rate of the display; and thus, in the display circuit provided by this embodiment, at least one of the first multiplexer 11 and the second multiplexer 12 is set to include the form of the transistor described in the embodiment, and the first sub-electrode 31 and the second sub-electrode 32 in the transistor are set to a form in which the orthographic projection along the thickness direction of the first electrode 2 does not overlap with the active layer 1, thereby effectively reducing the parasitic capacitance between the second electrode 3 and the active layer 1, effectively increasing the flow rate of the current in the transistor, and thus effectively reducing the time interval when switching between transistors. Figure 5 By reducing t2 in the display, the time of one row scanning cycle (1H), that is, the sum of the time from t1 to t5, can be shortened, and the refresh rate of the display circuit can be improved.

[0070] in, Figure 4 As shown, the number of the first column of pixel units 9 and the second column of pixel units 10 and the number of sub-pixels contained therein can be designed and adjusted according to actual needs. The first column of pixel units 9 includes red pixel units 91 and blue pixel units 92 arranged alternately; the second pixel unit 10 includes a plurality of green pixel units 101, thereby forming a display circuit with three primary colors. This setting is easily understood by those skilled in the art and will not be described in detail here. The first multiplexer 11 and the second multiplexer 12 can share the same PIN pin connected to the driver IC (not shown in the figure). When the first multiplexer 11 is turned on, it can charge the first column of pixel units 9. When the second multiplexer 12 is turned on, it can charge the second column of pixel units 10. The two multiplexers are turned off to start row scanning to complete the display. Of course, it is understandable that the number of multiplexer groups can be adapted to the number of pixel units.

[0071] in, Figure 5 As shown, t1 is the time when the first multiplexer 11 is turned on, t2 is the interval time between the first multiplexer 11 and the second multiplexer 12 being switched on, t3 is the time interval between the second multiplexer 12 and the row scan being switched on, t4 is the time when the row scan is turned on, and t5 is the time interval between the row scan and the first multiplexer 11 being switched on. The sum of the time from t1 to t5 is the entire scanning cycle.

[0072] This embodiment provides an electronic device, which includes a display panel (not shown in the figure), in which a display circuit is provided; the display circuit includes a first column of pixel units 9, a second column of pixel units 10 and at least one multi-way switch group; the multi-way switch group includes a first multi-way switch 11 and a second multi-way switch 12 connected in parallel to each other, the first multi-way switch 11 is used to connect the first column of pixel units 9 in series, and the second multi-way switch 12 is used to connect the second column of pixel units 10 in series; the first multi-way switch 11 and / or the second multi-way switch 12 include a transistor, and the transistor includes an active layer 1, a first electrode 2 and a second electrode 3, the second electrode 3 includes a first sub-electrode 31 and a second sub-electrode 32 arranged in the same layer, the first sub-electrode 31 and the second sub-electrode 32 are respectively located on both sides of the first electrode 2 in the thickness direction; the orthographic projection of the first sub-electrode 31 and / or the second sub-electrode 32 along the thickness direction does not overlap with the orthographic projection of the active layer 1 along the thickness direction.

[0073] Specifically, as electronic devices are increasingly pursuing the trend of becoming thinner and lighter, the connection pins of the driver IC are compressed by time-sharing multiplexing of the multiplexer, thereby effectively reducing the size and design cost of the driver IC. However, the time-sharing multiplexing of the multiplexer will limit the refresh rate of the display; and further, in the electronic device provided in this embodiment, at least one of the first multiplexer 11 and the second multiplexer 12 is set to include the form of the transistor described in the embodiment, and the first sub-electrode 31 and the second sub-electrode 32 in the transistor are set to a form in which the orthographic projection along the thickness direction of the first electrode 2 does not overlap with the active layer 1, thereby effectively reducing the parasitic capacitance between the second electrode 3 and the active layer 1, effectively increasing the flow rate of the current in the transistor, and thus effectively reducing the time interval when switching between transistors. Figure 5 By reducing t2 in the image, the time of one row scanning cycle, i.e. the sum of the time from t1 to t5, can be shortened, and the refresh rate of the display panel can be improved.

[0074] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A transistor, It is characterized in that include: Active layer; A first electrode is disposed on the active layer; a second electrode, the second electrode comprising a first sub-electrode and a second sub-electrode arranged in the same layer, the first sub-electrode and the second sub-electrode being respectively located at two sides of the first electrode in a thickness direction; An orthographic projection of the first sub-electrode and / or the second sub-electrode along the thickness direction does not overlap with an orthographic projection of the active layer along the thickness direction.

2. The transistor according to claim 1, It is characterized in that A side of the first sub-electrode and / or the second sub-electrode facing away from the active layer is a flat surface.

3. The transistor according to claim 2, It is characterized in that The transistor includes a conductive layer, and two ends of the conductive layer are respectively connected to the second electrode and the active layer.

4. The transistor according to claim 1, Features: An orthographic projection of one end of the first sub-electrode and / or the second sub-electrode facing the first electrode in a plane parallel to the active layer along the thickness direction borders an edge of an orthographic projection of the active layer along the thickness direction.

5. The transistor according to claim 1, Features: The first sub-electrode and / or the second sub-electrode are arranged in a plane parallel to the active layer, with the orthographic projection of one end of the first electrode along the thickness direction being spaced apart from the edge of the orthographic projection of the active layer along the thickness direction.

6. The transistor according to claim 1, Features: Also includes a first insulating layer and / or a second insulating layer; The first insulating layer is disposed on a side of the second electrode facing the active layer; The second insulating layer is disposed between the first electrode and the active layer.

7. The transistor according to claim 1, Features: Also included is a glass substrate; The glass substrate is disposed on a side of the active layer away from the first electrode.

8. A display circuit, It is characterized in that It includes: A first column of pixel units, a second column of pixel units, and at least one multi-way switch group; The multi-way switch group includes a first multi-way switch and a second multi-way switch connected in parallel with each other, the first multi-way switch is used to connect the first column of pixel units in series, and the second multi-way switch is used to connect the second column of pixel units in series; The first multi-way switch and / or the second multi-way switch comprises a transistor, wherein the transistor comprises an active layer, a first electrode and a second electrode, wherein the second electrode comprises a first sub-electrode and a second sub-electrode arranged in the same layer, and the first sub-electrode and the second sub-electrode are respectively located on two sides of the first electrode in a thickness direction; An orthographic projection of the first sub-electrode and / or the second sub-electrode along the thickness direction does not overlap with an orthographic projection of the active layer along the thickness direction.

9. The display circuit according to claim 8, Features: The first column of pixel units includes red pixel units and blue pixel units that are alternately arranged; The second column of pixel units includes a plurality of green pixel units.

10. An electronic device, It is characterized in that It includes: A display panel, wherein a display circuit is provided in the display panel; The display circuit includes a first column of pixel units, a second column of pixel units and at least one multi-way switch group; The multi-way switch group includes a first multi-way switch and a second multi-way switch connected in parallel with each other, the first multi-way switch is used to connect the first column of pixel units in series, and the second multi-way switch is used to connect the second column of pixel units in series; The first multi-way switch and / or the second multi-way switch comprises a transistor, wherein the transistor comprises an active layer, a first electrode and a second electrode, wherein the second electrode comprises a first sub-electrode and a second sub-electrode arranged in the same layer, and the first sub-electrode and the second sub-electrode are respectively located on two sides of the first electrode in a thickness direction; An orthographic projection of the first sub-electrode and / or the second sub-electrode along the thickness direction does not overlap with an orthographic projection of the active layer along the thickness direction.

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