Starting control circuit of receiving card
By designing a start control circuit and delay circuit in the receiving card, the stability of the FPGA chip in the power-on timing is ensured, and the problem of insufficient release of energy storage components when the receiving card is connected to the power supply is solved, and the normal start of the FPGA chip is achieved and normal use of the receiving card.
Patent Information
- Application Number
- CN202421110291.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-21
- Publication Date
- 2024-12-24
- Estimated Expiration
- 2034-05-21
AI Technical Summary
The existing receiving card has several brief power-up and down power when connected to the power supply, resulting in the energy storage element not being able to fully release energy, resulting in the failure of the delay circuit, and the normal start of the FPGA chip cannot be guaranteed, which in turn causes the receiving card to be unusable.
A startup control circuit for receiving a card is designed, and the delay start of the second voltage and the third voltage circuit is controlled by outputting a high-level reset signal through the start control circuit, and the first delay circuit and the second delay circuit are used to control the second delay circuit respectively. The delay start of the second voltage and third voltage circuits ensures the stable timing of the FPGA chip during power-on.
The normal start-up of the FPGA chip is achieved, the generation of pulse current is avoided, the normal use of the receiving card is ensured, and fewer components are used in a compact layout.
Smart Images
Figure CN222232897U_ABST
Abstract
Description
Technical Field
[0001] The embodiment of the utility model relates to the technical field of integrated circuits, and in particular to a start-up control circuit of a receiving card. Background Art
[0002] FPGA chip is a semi-customized, programmable logic chip. Its internal structure integrates programmable input / output units (I / O), programmable logic blocks (LC), complete clock management (CMT), embedded block RAM (BRAM), wiring resources, embedded low-level functional units and dedicated hardware modules. Such a high-performance, highly integrated chip has high requirements in use, especially in the startup phase of the chip. As a product that will be powered on and off at a high frequency during installation and use, the FPGA chip used in the receiving card must also adapt to this feature. It is particularly important to ensure that the voltage required by the FPGA chip is started in the specified order. It was found during use that when the external power supply is connected, a certain degree of poor contact will cause the FPGA chip to have a disordered power-on sequence, which will cause the FPGA chip to have a large pulse current, thereby causing the power IC chip and the FPGA chip to enter an abnormal state.
[0003] The receiving card usually uses FPGA chip as the main control, and the required power-on sequence is the first voltage, the second voltage, and the third voltage. Due to its lower required voltage, the existing technology prefers to use DCDC chips to obtain the corresponding voltage. How to deal with the startup time of the power IC chip is the key to ensuring the power-on sequence. Because the first voltage and the second voltage are lower, the voltage generated by the upper path is difficult to be directly used as the startup voltage of the lower path. The three voltages are more likely to use the input 5V power supply to reduce the voltage at the same time, and use the delay circuit for power-on delay. If it is used simply in this way, when the power is connected, multiple short power on and off will cause the energy storage elements in the receiving card and the power supply to not be able to release energy completely and effectively. When the power is turned on next time, the delay circuit will fail to delay, and the power-on sequence cannot be guaranteed, causing the FPGA chip to fail to start normally, and then the receiving card cannot be used. Utility Model Content
[0004] The utility model provides a start-up control circuit of a receiving card, which ensures that the timing of an FPGA chip is stable during the power-on process, so that the FPGA chip starts normally and the normal use of the receiving card is ensured.
[0005] According to one aspect of the utility model, a start-up control circuit of a receiving card is provided, and the start-up control circuit of the receiving card includes: a start-up control circuit, a first delay circuit, a second delay circuit, an FPGA chip, a first voltage circuit, a second voltage circuit, and a third voltage circuit;
[0006] The power supply is connected to the startup control circuit and the first voltage circuit, the startup control circuit and the first voltage circuit are started simultaneously, the startup control circuit is connected to the second voltage circuit and the third voltage circuit, and the first voltage circuit is started before the second voltage circuit and the third voltage circuit;
[0007] The first delay circuit is connected between the start control circuit and the second voltage circuit, and the first delay circuit and the start control circuit are used to control the delayed start of the second voltage circuit;
[0008] The second delay circuit is connected between the start control circuit and the third voltage circuit, and the second delay circuit and the start control circuit are used to control the delayed start of the third voltage circuit;
[0009] The FPGA chip is connected to the first voltage circuit, the second voltage circuit and the third voltage circuit.
[0010] Optionally, the startup control circuit includes: a fourth resistor, a reset chip and a fifth resistor;
[0011] The first end of the fourth resistor is connected to the first power supply end, the second end of the fourth resistor is connected to the third end of the reset chip, the fifth resistor is connected between the second end and the first end of the reset chip, and the second end of the reset chip is connected to the first delay circuit and the second delay circuit.
[0012] Optionally, the first delay circuit includes: a sixth resistor and an eighth capacitor;
[0013] The first end of the sixth resistor is connected to the second end of the reset chip, the second end of the sixth resistor is connected to the first end of the eighth capacitor and the second voltage circuit, and the second end of the eighth capacitor is grounded.
[0014] Optionally, the second delay circuit includes: a ninth resistor and a fourteenth capacitor;
[0015] The first end of the ninth resistor is connected to the second end of the reset chip, the second end of the ninth resistor is connected to the first end of the fourteenth capacitor and the third voltage circuit, and the second end of the fourteenth capacitor is grounded.
[0016] Optionally, the first voltage circuit includes: a first capacitor, a second capacitor, a first power IC chip, a first inductor, a second resistor, a third resistor, a third capacitor and a fourth capacitor;
[0017] The first end of the first capacitor is connected to the first end of the second capacitor, the first power supply end and the fourth end of the first power IC chip, the second end of the first capacitor is connected to the second end of the second capacitor and then grounded, the second end of the first power IC chip is grounded, the fifth end of the first power IC chip is connected to the first end of the second resistor and the first end of the third resistor, the second end of the third resistor is grounded, the second end of the second resistor is connected to the first end of the first inductor, the first end of the third capacitor, the first end of the fourth capacitor and the second power supply end, the second end of the first inductor is connected to the third end of the first power IC chip, and the second end of the third capacitor is connected to the second end of the fourth capacitor and then grounded.
[0018] Optionally, the first voltage circuit further includes a current limiting resistor, and the current limiting resistor is connected between the fourth terminal and the first terminal of the first power IC chip.
[0019] Optionally, the second voltage circuit includes: a second power IC chip, a second inductor, a seventh resistor, an eighth resistor, a seventh capacitor and a ninth capacitor;
[0020] The first end of the second power supply IC chip is connected to the first delay circuit, the second end of the second power supply IC chip is grounded, the third end of the second power supply IC chip is connected to the first end of the second inductor, the second end of the second inductor is connected to the first end of the seventh resistor, the first end of the seventh capacitor, the first end of the ninth capacitor and the third power supply end, the second end of the seventh capacitor is grounded, the second end of the ninth capacitor is grounded, the second end of the seventh resistor is connected to the first end of the eighth resistor and the fifth end of the second power supply IC chip, and the second end of the eighth resistor is grounded.
[0021] Optionally, the second voltage circuit also includes a fifth capacitor and a sixth capacitor, the first end of the fifth capacitor is connected to the first end of the sixth capacitor, the fourth end of the second power IC chip and the first power supply end, the second end of the fifth capacitor is grounded, and the second end of the sixth capacitor is grounded.
[0022] Optionally, the third voltage circuit includes: a third power IC chip, a third inductor, a tenth resistor, an eleventh resistor, a twelfth capacitor and a thirteenth capacitor;
[0023] The first end of the third power supply IC chip is connected to the second delay circuit, the second end of the third power supply IC chip is grounded, the third end of the third power supply IC chip is connected to the first end of the third inductor, the second end of the third inductor is connected to the first end of the tenth resistor, the first end of the twelfth capacitor, the first end of the thirteenth capacitor and the fourth power supply end, the second end of the twelfth capacitor is grounded, the second end of the thirteenth capacitor is grounded, the second end of the tenth resistor is connected to the first end of the eleventh resistor and the fifth end of the third power supply IC chip, and the second end of the eleventh resistor is grounded.
[0024] Optionally, the third voltage circuit also includes a tenth capacitor and an eleventh capacitor, the first end of the tenth capacitor is connected to the first end of the eleventh capacitor, the fourth end of the third power supply IC chip and the first power supply end, the second end of the tenth capacitor is grounded, and the second end of the eleventh capacitor is grounded.
[0025] The technical solution of the embodiment of the utility model controls the startup of the subsequent second voltage circuit and the third voltage circuit by outputting a high-level reset signal through the startup control circuit, ensures the priority startup of the first voltage circuit 50, uses the first delay circuit and the startup control circuit to control the delayed startup of the second voltage circuit, and uses the second delay circuit and the startup control circuit to control the delayed startup of the third voltage circuit, thereby ensuring that the timing of the FPGA chip is stable during the power-on process, so that the FPGA chip starts normally, and the energy storage elements in the receiving card and the power supply can fully and effectively release energy, ensuring the normal use of the receiving card. The startup control circuit structure in the utility model is simple, strictly guarantees the power-on timing of the FPGA chip, avoids the FPGA chip from generating pulse current under abnormal conditions, and at the same time, in a relatively compact receiving card layout, uses fewer components to achieve the required requirements. In summary, the utility model solves the problem that when the existing receiving card is connected to the power supply, multiple short power-ups and downs will cause the energy storage elements in the receiving card and the power supply to not fully and effectively release energy; when the power is turned on next time, the delay circuit will fail to delay, and the power-on timing cannot be guaranteed, causing the FPGA chip to fail to start normally, and then causing the receiving card to be unusable.
[0026] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present utility model, nor are they intended to limit the scope of the present utility model. Other features of the present utility model will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0028] Figure 1 It is a structural schematic diagram of a start-up control circuit of a receiving card provided according to an embodiment of the utility model;
[0029] Figure 2 It is a circuit principle diagram of a startup control circuit provided according to an embodiment of the utility model;
[0030] Figure 3 This is a schematic diagram of the internal structure of an SGM809B reset chip provided according to an embodiment of the utility model;
[0031] Figure 4 It is a circuit schematic diagram of a first delay circuit and a second voltage circuit provided according to an embodiment of the utility model;
[0032] Figure 5 It is a circuit principle diagram of a second delay circuit and a third voltage circuit provided according to an embodiment of the utility model;
[0033] Figure 6 is a circuit schematic diagram of a first voltage circuit provided according to an embodiment of the utility model;
[0034] Figure 7 It is a schematic diagram of a pulse current with improved timing according to an embodiment of the utility model;
[0035] Figure 8 It is a schematic diagram of another pulse current with improved timing provided according to an embodiment of the utility model;
[0036] Fig. 9 It is a schematic diagram of a pulse current when a timing error is provided according to an embodiment of the utility model. DETAILED DESCRIPTION
[0037] In order to enable those skilled in the art to better understand the solution of the utility model, the technical solution in the embodiment of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiment of the utility model. Obviously, the described embodiment is only a part of the embodiment of the utility model, not all of the embodiments. Based on the embodiment of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the utility model.
[0038] It should be noted that the terms "first", "second", etc. in the specification and claims of the utility model and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the utility model described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0039] Figure 1 is a schematic diagram of a start-up control circuit of a receiving card provided according to an embodiment of the utility model, with reference to Figure 1 The embodiment of the utility model provides a start-up control circuit of a receiving card, and the start-up control circuit of the receiving card includes: a start-up control circuit 10, a first delay circuit 20, a second delay circuit 30, an FPGA chip 40, a first voltage circuit 50, a second voltage circuit 60 and a third voltage circuit 70; the power supply is connected to the start-up control circuit 10 and the first voltage circuit 50, the start-up control circuit 10 and the first voltage circuit 50 are started at the same time, the start-up control circuit 10 is connected to the second voltage circuit 60 and the third voltage circuit 70, and the first voltage circuit 50 takes precedence over The second voltage circuit 60 and the third voltage circuit 70 are started; the first delay circuit 20 is connected between the start control circuit 10 and the second voltage circuit 60, and the first delay circuit 20 and the start control circuit 10 are used to control the delayed start of the second voltage circuit 60; the second delay circuit 30 is connected between the start control circuit 10 and the third voltage circuit 70, and the second delay circuit 30 and the start control circuit 10 are used to control the delayed start of the third voltage circuit 70; the FPGA chip 40 is connected to the first voltage circuit 50, the second voltage circuit 60 and the third voltage circuit 70.
[0040] Specifically, the power-on timing of the first voltage circuit 50, the second voltage circuit 60, and the third voltage circuit 70 may be 1.8V, 0.95V, and 3.3V, respectively. The startup control circuit 10 does not control the 1.8V voltage of the first voltage circuit 50, but monitors the input 5V voltage, and the output reset signal is connected to the EN pin of the power IC of the second voltage circuit 60 and the EN pin of the power IC of the third voltage circuit 70, respectively. For example, the delay between 1.8V and 0.95V may be 267ms, and the delay between 0.95V and 3.3V may be 920us.
[0041] The startup control circuit 10 monitors the input 5V power supply, and when conditions are met, outputs a high-level reset signal to control the delayed startup of the subsequent second voltage circuit 60 and the third voltage circuit 70, thereby ensuring the priority startup of the first voltage circuit 50. The first delay circuit 20 is used for delay between the startup control circuit 10 and the second voltage circuit 60, and the second delay circuit 30 is used for delay between the startup control circuit 10 and the third voltage circuit 70, so that a power-on timing sequence that strictly meets the requirements can be guaranteed.
[0042] The technical solution of the embodiment of the utility model controls the startup of the subsequent second voltage circuit and the third voltage circuit by outputting a high-level reset signal through the startup control circuit, ensures the priority startup of the first voltage circuit 50, uses the first delay circuit and the startup control circuit to control the delayed startup of the second voltage circuit, and uses the second delay circuit and the startup control circuit to control the delayed startup of the third voltage circuit, thereby ensuring that the timing of the FPGA chip is stable during the power-on process, so that the FPGA chip starts normally, and the energy storage elements in the receiving card and the power supply can fully and effectively release energy, ensuring the normal use of the receiving card. The startup control circuit structure in the utility model is simple, strictly guarantees the power-on timing of the FPGA chip, avoids the FPGA chip from generating pulse current under abnormal conditions, and at the same time, in a relatively compact receiving card layout, uses fewer components to achieve the required requirements. In summary, the utility model solves the problem that when the existing receiving card is connected to the power supply, multiple short power-ups and downs will cause the energy storage elements in the receiving card and the power supply to not fully and effectively release energy; when the power is turned on next time, the delay circuit will fail to delay, and the power-on timing cannot be guaranteed, causing the FPGA chip to fail to start normally, and then causing the receiving card to be unusable.
[0043] Figure 2 is a circuit diagram of a startup control circuit provided according to an embodiment of the utility model, referring to Figure 2 Optionally, the startup control circuit 10 includes: a fourth resistor R4, a reset chip U2 and a fifth resistor R5; the first end of the fourth resistor R4 is connected to the first power supply end 5V, the second end of the fourth resistor R4 is connected to the third end 3 of the reset chip U2, the fifth resistor R5 is connected between the second end 2 and the first end 1 of the reset chip U2, and the second end of the reset chip U2 is connected to the first delay circuit and the second delay circuit.
[0044] Specifically, the reset chip U2 can be an SGM809B reset chip. The first pin of the reset chip U2 is grounded, the second pin of the reset chip U2 outputs a high-level reset signal, and the third pin of the reset chip U2 is connected to the monitored input voltage. The fourth resistor R4 is a current-limiting resistor used to protect the reset chip U2 from damage caused by high-voltage pulses, and its value can be added with 0 - 1K according to actual use. The function of the fifth resistor R5 is to ensure that the logic point of the internal CMOS of the reset chip U2 is 0V and release the energy that the chip cannot absorb when the voltage is below 1V.
[0045] Figure 3 It is a schematic diagram of the internal structure of an SGM809B reset chip provided according to an embodiment of the present invention. Refer to Figure 3 , the working principle of the SGM809B reset chip is specifically as follows: The midpoint voltage of the resistor voltage division network is denoted as V1. When the VCC to be monitored drops or is turned off, V1 < Vref, and the comparator at the rear will output a low level. After passing through a NAND gate, a high level is output. The high level drives a push-pull output structure, and the lower NMOS is turned on to pull down the output, thereby outputting a low-level reset signal to the rear. When the power supply is reconnected, at this time, V1 > Vref, the comparator outputs a high level, and two high levels pass through a NAND gate to generate a low level. The low level drives the push-pull output, and the upper PMOS is turned on to pull the output to VCC, that is, a high level is output. After this process, the first voltage will start 140ms - 300ms later, and then the next voltage will start, which ensures the timing to a certain extent. By using the internal comparator, it can avoid abnormalities caused by voltage drops in case of poor contact. Among them, the value of Vref can be determined by chip selection. The RC delays of the second voltage circuit and the third voltage circuit can be calculated according to the formula to obtain the specific delay time.
[0046] Figure 4 It is a circuit schematic diagram of a first delay circuit and a second voltage circuit provided according to an embodiment of the present invention. Refer to Figure 4 and Figure 2 , optionally, the first delay circuit 20 includes: a sixth resistor R6 and an eighth capacitor C8; the first end of the sixth resistor R6 is connected to the second end 2 of the reset chip U2, the second end of the sixth resistor R6 is connected to the first end of the eighth capacitor C8 and the second voltage circuit 60, and the second end of the eighth capacitor C8 is grounded to GND.
[0047] Specifically, the sixth resistor R6 and the eighth capacitor C8 form an RC circuit for delaying.
[0048] Continue to refer to Figure 4Optionally, the second voltage circuit 60 includes: a second power supply IC chip U3, a second inductor L2, a seventh resistor R7, an eighth resistor R8, a seventh capacitor C7 and a ninth capacitor C9; the first end 1 of the second power supply IC chip U3 is connected to the first delay circuit 20, the second end 2 of the second power supply IC chip U3 is grounded GND, the third end 3 of the second power supply IC chip U3 is connected to the first end of the second inductor L2, the second end of the second inductor L2 is connected to the first end of the seventh resistor R7, the first end of the seventh capacitor C7, the first end of the ninth capacitor C9 and the third power supply end 0P9V5, the second end of the seventh capacitor C7 is grounded GND, the second end of the ninth capacitor C9 is grounded GND, the second end of the seventh resistor R7 is connected to the first end of the eighth resistor R8 and the fifth end 5 of the second power supply IC chip U3, and the second end of the eighth resistor R8 is grounded GND.
[0049] Specifically, the second inductor L2 is a power inductor for storing energy and rectifying. The seventh resistor R7 and the eighth resistor R8 are voltage divider resistors for increasing the reference voltage of the FB pin of the second power IC chip U3 to the output voltage. The seventh capacitor C7 and the ninth capacitor C9 are output capacitors for reducing the ripple voltage of the output power supply.
[0050] Continue to refer Figure 4 Optionally, the second voltage circuit 60 also includes a fifth capacitor C5 and a sixth capacitor C6, the first end of the fifth capacitor C5 is connected to the first end of the sixth capacitor C6, the fourth end 4 of the second power IC chip U3 and the first power supply end 5V, the second end of the fifth capacitor C5 is grounded GND, and the second end of the sixth capacitor C6 is grounded GND.
[0051] Specifically, the fifth capacitor C5 and the sixth capacitor C6 are input capacitors, which are used to reduce surge current from the input end and switching noise from the device.
[0052] Figure 5 is a circuit schematic diagram of a second delay circuit and a third voltage circuit provided according to an embodiment of the utility model, with reference to Figure 5 and Figure 2 Optionally, the second delay circuit 30 includes: a ninth resistor R9 and a fourteenth capacitor C14; the first end of the ninth resistor R9 is connected to the second end 2 of the reset chip U2, the second end of the ninth resistor R9 is connected to the first end of the fourteenth capacitor C14 and the third voltage circuit 70, and the second end of the fourteenth capacitor C14 is grounded GND.
[0053] Specifically, the ninth resistor R9 and the fourteenth capacitor C14 form an RC circuit for delay.
[0054] Continue to refer Figure 5Optionally, the third voltage circuit 70 includes: a third power IC chip U4, a third inductor L3, a tenth resistor R10, an eleventh resistor R11, a twelfth capacitor C12 and a thirteenth capacitor C13; the first end of the third power IC chip U4 is connected to the second delay circuit 30, the second end 2 of the third power IC chip U4 is grounded GND, the third end 3 of the third power IC chip U4 is connected to the first end of the third inductor L3, the second end of the third inductor L3 is connected to the first end of the tenth resistor R10, the first end of the twelfth capacitor C12, the first end of the thirteenth capacitor C13 and the fourth power supply end D3V3, the second end of the twelfth capacitor C12 is grounded GND, the second end of the thirteenth capacitor C13 is grounded GND, the second end of the tenth resistor R10 is connected to the first end of the eleventh resistor R11 and the fifth end 5 of the third power IC chip U4, and the second end of the eleventh resistor R11 is grounded GND.
[0055] Specifically, the third inductor L3 is a power inductor, which is used for storing energy and rectifying. The tenth resistor R10 and the eleventh resistor R11 are voltage divider resistors, which are used to increase the reference voltage of the FB pin of the third power IC chip U4 to the output voltage. The twelfth capacitor C12 and the thirteenth capacitor C13 are output capacitors, which are used to reduce the ripple voltage of the output power supply.
[0056] Continue to refer Figure 5 Optionally, the third voltage circuit 70 also includes a tenth capacitor C10 and an eleventh capacitor C11, the first end of the tenth capacitor C10 is connected to the first end of the eleventh capacitor C11, the fourth end 4 of the third power IC chip U4 and the first power supply end 5V, the second end of the tenth capacitor C10 is grounded GND, and the second end of the eleventh capacitor C11 is grounded GND.
[0057] Specifically, the tenth capacitor C10 and the eleventh capacitor C11 are input capacitors, which are used to reduce surge current from the input end and switching noise from the device.
[0058] Figure 6 is a circuit schematic diagram of a first voltage circuit provided according to an embodiment of the utility model, referring to Figure 6Optionally, the first voltage circuit 50 includes: a first capacitor C1, a second capacitor C2, a first power IC chip U1, a first inductor L1, a second resistor R2, a third resistor R3, a third capacitor C3 and a fourth capacitor C4; the first end of the first capacitor C1 is connected to the first end of the second capacitor C2, the first power supply end 5V and the fourth end 4 of the first power IC chip U1, the second end of the first capacitor C1 is connected to the second end of the second capacitor C2 and then grounded GND, the second end 2 of the first power IC chip U1 is grounded GND, the fifth end 5 of the first power IC chip U1 is connected to the first end of the second resistor R2 and the first end of the third resistor R3, the second end of the third resistor R3 is grounded GND, the second end of the second resistor R2 is connected to the first end of the first inductor L1, the first end of the third capacitor C3, the first end of the fourth capacitor C4 and the second power supply end D1V8, the second end of the first inductor L1 is connected to the third end 3 of the first power IC chip U1, and the second end of the third capacitor C3 is connected to the second end of the fourth capacitor C4 and then grounded GND.
[0059] Specifically, the first capacitor C1 and the second capacitor C2 are input capacitors, which are used to reduce the surge current from the input end and the switching noise from the device. The first inductor L1 is a power inductor, which is used to store energy and rectify. The second resistor R2 and the third resistor R3 are voltage divider resistors, which are used to increase the reference voltage of the FB pin of the first power IC chip U1 to the output voltage. The third capacitor C3 and the fourth capacitor C4 are output capacitors, which are used to reduce the ripple voltage of the output power supply.
[0060] Continue to refer Figure 6 Optionally, the first voltage circuit 50 further includes a current limiting resistor R1, and the current limiting resistor R1 is connected between the fourth terminal 4 and the first terminal 1 of the first power IC chip U1.
[0061] Specifically, the current limiting resistor R1 is used to reduce the current input to the EN pin of the first power IC chip U1 to prevent damage to the first power IC chip U1.
[0062] It should be noted that Figure 2 , Figure 4 , Figure 5 , Figure 6 The electrical nodes with the same label are electrically connected, such as 5V, Reset, GND, etc. The electrical nodes with the same text characters in the figure are electrically connected to each other, which is done to make the figure clear.
[0063] Figure 7 is a schematic diagram of a pulse current with improved timing according to an embodiment of the utility model, Figure 8 is a schematic diagram of another pulse current with improved timing according to an embodiment of the utility model, Fig. 9is a schematic diagram of a pulse current when a timing error is provided according to an embodiment of the utility model, with reference to Figure 7 , Figure 8 , Fig. 9 , Figure 7 The measured delay between 1.8V and 0.95V is 267ms. Figure 8 The measured delay between 0.95V and 3.3V is 920us. Fig. 9 It is a pulse current when the timing is wrong. The startup control circuit structure of the receiving card in the utility model is simple, strictly guarantees the power-on timing of the FPGA chip, avoids the FPGA chip from generating pulse current under abnormal conditions, and at the same time uses fewer components to achieve the required requirements in a relatively compact receiving card layout.
[0064] The above specific implementations do not constitute a limitation on the protection scope of the present utility model. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present utility model shall be included in the protection scope of the present utility model.
Claims
1. A start-up control circuit for a receiving card, characterized in that: include: A start-up control circuit, a first delay circuit, a second delay circuit, an FPGA chip, a first voltage circuit, a second voltage circuit, and a third voltage circuit; The power supply is connected to the startup control circuit and the first voltage circuit, the startup control circuit and the first voltage circuit are started simultaneously, the startup control circuit is connected to the second voltage circuit and the third voltage circuit, and the first voltage circuit is started before the second voltage circuit and the third voltage circuit; The first delay circuit is connected between the start control circuit and the second voltage circuit, and the first delay circuit and the start control circuit are used to control the delayed start of the second voltage circuit; The second delay circuit is connected between the start control circuit and the third voltage circuit, and the second delay circuit and the start control circuit are used to control the delayed start of the third voltage circuit; The FPGA chip is connected to the first voltage circuit, the second voltage circuit and the third voltage circuit.
2. The circuit according to claim 1, characterized in that The startup control circuit includes: a fourth resistor, a reset chip and a fifth resistor; The first end of the fourth resistor is connected to the first power supply end, the second end of the fourth resistor is connected to the third end of the reset chip, the fifth resistor is connected between the second end and the first end of the reset chip, and the second end of the reset chip is connected to the first delay circuit and the second delay circuit.
3. The circuit according to claim 2, characterized in that The first delay circuit comprises: a sixth resistor and an eighth capacitor; The first end of the sixth resistor is connected to the second end of the reset chip, the second end of the sixth resistor is connected to the first end of the eighth capacitor and the second voltage circuit, and the second end of the eighth capacitor is grounded.
4. The circuit according to claim 2, characterized in that The second delay circuit comprises: a ninth resistor and a fourteenth capacitor; The first end of the ninth resistor is connected to the second end of the reset chip, the second end of the ninth resistor is connected to the first end of the fourteenth capacitor and the third voltage circuit, and the second end of the fourteenth capacitor is grounded.
5. The circuit according to claim 1, characterized in that The first voltage circuit includes: a first capacitor, a second capacitor, a first power IC chip, a first inductor, a second resistor, a third resistor, a third capacitor and a fourth capacitor; The first end of the first capacitor is connected to the first end of the second capacitor, the first power supply end and the fourth end of the first power IC chip, the second end of the first capacitor is connected to the second end of the second capacitor and then grounded, the second end of the first power IC chip is grounded, the fifth end of the first power IC chip is connected to the first end of the second resistor and the first end of the third resistor, the second end of the third resistor is grounded, the second end of the second resistor is connected to the first end of the first inductor, the first end of the third capacitor, the first end of the fourth capacitor and the second power supply end, the second end of the first inductor is connected to the third end of the first power IC chip, and the second end of the third capacitor is connected to the second end of the fourth capacitor and then grounded.
6. The circuit according to claim 5, characterized in that The first voltage circuit further includes a current limiting resistor connected between the fourth terminal and the first terminal of the first power IC chip.
7. The circuit according to claim 1, characterized in that The second voltage circuit includes: a second power IC chip, a second inductor, a seventh resistor, an eighth resistor, a seventh capacitor and a ninth capacitor; The first end of the second power supply IC chip is connected to the first delay circuit, the second end of the second power supply IC chip is grounded, the third end of the second power supply IC chip is connected to the first end of the second inductor, the second end of the second inductor is connected to the first end of the seventh resistor, the first end of the seventh capacitor, the first end of the ninth capacitor and the third power supply end, the second end of the seventh capacitor is grounded, the second end of the ninth capacitor is grounded, the second end of the seventh resistor is connected to the first end of the eighth resistor and the fifth end of the second power supply IC chip, and the second end of the eighth resistor is grounded.
8. The circuit according to claim 7, characterized in that The second voltage circuit also includes a fifth capacitor and a sixth capacitor, the first end of the fifth capacitor is connected to the first end of the sixth capacitor, the fourth end of the second power IC chip and the first power supply end, the second end of the fifth capacitor is grounded, and the second end of the sixth capacitor is grounded.
9. The circuit according to claim 1, characterized in that The third voltage circuit includes: a third power IC chip, a third inductor, a tenth resistor, an eleventh resistor, a twelfth capacitor and a thirteenth capacitor; The first end of the third power supply IC chip is connected to the second delay circuit, the second end of the third power supply IC chip is grounded, the third end of the third power supply IC chip is connected to the first end of the third inductor, the second end of the third inductor is connected to the first end of the tenth resistor, the first end of the twelfth capacitor, the first end of the thirteenth capacitor and the fourth power supply end, the second end of the twelfth capacitor is grounded, the second end of the thirteenth capacitor is grounded, the second end of the tenth resistor is connected to the first end of the eleventh resistor and the fifth end of the third power supply IC chip, and the second end of the eleventh resistor is grounded.
10. The circuit according to claim 9, characterized in that The third voltage circuit also includes a tenth capacitor and an eleventh capacitor, the first end of the tenth capacitor is connected to the first end of the eleventh capacitor, the fourth end of the third power IC chip and the first power supply end, the second end of the tenth capacitor is grounded, and the second end of the eleventh capacitor is grounded.