Half-duplex serial port communication circuit for single-line and double-line conversion
By designing a half-duplex serial communication circuit for single- and double-wire conversion in the chip communication circuit, single-wire communication is achieved using field effect transistors and resistors, the dual-wire routing problem caused by chip upgrade is solved, and communication stability and signal lines are improved. Utilization.
Patent Information
- Application Number
- CN202420487495.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-13
- Publication Date
- 2024-12-24
- Estimated Expiration
- 2034-03-13
AI Technical Summary
With the upgrade of the chip, some nodes cannot meet the dual-wire routing, which has a great impact on the communication between the two chips.
Design a half-duplex serial communication circuit for single- and double-wire conversion. By using field effect transistors and resistors with different resistance values in the first and second communication modules, single-wire communication between chips is realized, making full use of equipment space and improving The utilization rate of signal lines.
In the case of chip upgrade, stable communication between the two chips is achieved, the utilization rate of signal lines is improved, and communication interference is avoided.
Smart Images
Figure CN222232993U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of communication circuits, in particular to a half-duplex serial communication circuit for single-wire and double-wire conversion. Background Art
[0002] Serial communication is a communication method that transmits data through a serial interface. Serial communication is usually used to transmit data between computers and external devices, such as printers, sensors, modules, etc. Serial communication can be divided into two types: synchronous serial communication and asynchronous serial communication.
[0003] In serial communication, data is transmitted in bit order, with a start bit, one or more data bits, and one or more stop bits between each data bit. Serial communication has the following characteristics: Easy to use: Serial communication only requires a small number of pins and simple circuits to achieve data transmission. Stable and reliable: Serial communication is not affected by interference, and data transmission is stable and reliable. Cross-platform: Serial communication can perform data transmission between different platforms, such as communication between PC and embedded devices.
[0004] Under normal circumstances, serial communication requires the use of two data lines to meet the needs of one send and one receive. Figure 1 As shown, the TXD pin of chip A is connected to the RXD pin of chip B, so that the serial port data from chip A to chip B is sent; the TXD pin of chip B is connected to the RXD pin of chip A, so that the serial port data from chip B to chip A is sent.
[0005] However, with the influence of various factors such as chip upgrades, double-wire routing cannot be achieved at some nodes, which has a great impact on the communication between the two chips. Utility Model Content
[0006] The utility model aims to provide a half-duplex serial communication circuit for single-to-double-wire conversion, aiming to improve the problem that as the chip is upgraded, some nodes cannot meet the double-wire routing requirements, which affects the communication between the two chips.
[0007] In order to achieve the above purpose, the utility model adopts the following technical solutions:
[0008] A half-duplex serial communication circuit for single-to-double-wire conversion includes a first communication module and a second communication module.
[0009] The first communication module includes a field effect transistor Q1, a field effect transistor Q2, a pull-up resistor R1 and a pull-down resistor R4; the second communication module includes a field effect transistor Q3, a field effect transistor Q4, a pull-up resistor R5 and a pull-down resistor R8;
[0010] One end of the pull-up resistor R1 and the source of the field effect transistor Q2 are both electrically connected to an external power supply, the other end of the pull-up resistor R1 is electrically connected to the drain of the field effect transistor Q1, and is electrically connected to the signal receiving end of the external first chip as a first receiving port, the gate of the field effect transistor Q1 is electrically connected to one end of the pull-down resistor R4 and the drain of the field effect transistor Q2, and is electrically connected to the second communication module as a first connection port, the gate of the field effect transistor Q2 is a first sending port, and is electrically connected to the signal sending end of the external first chip, and the other end of the pull-down resistor R4 and the source of the field effect transistor Q1 are grounded;
[0011] One end of the pull-up resistor R5 and the source of the field effect transistor Q4 are both electrically connected to an external power supply, the other end of the pull-up resistor R5 is electrically connected to the drain of the field effect transistor Q3, and is electrically connected to the signal receiving end of the external second chip as a second receiving port, the gate of the field effect transistor Q3 is electrically connected to one end of the pull-down resistor R8 and the drain of the field effect transistor Q4, and is electrically connected to the first communication module as a second connection port, the gate of the field effect transistor Q4 is a second sending port, and is electrically connected to the signal sending end of the external second chip, and the other end of the pull-down resistor R8 and the source of the field effect transistor Q3 are grounded.
[0012] Furthermore, the field effect transistor Q1 and the field effect transistor Q3 are both N-channel field effect transistors; and the field effect transistor Q2 and the field effect transistor Q4 are both P-channel field effect transistors.
[0013] Furthermore, the input capacitance values of the field effect transistor Q1, the field effect transistor Q2, the field effect transistor Q3 and the field effect transistor Q4 are less than or equal to 100PF.
[0014] Further, the first communication module further includes a resistor R2 and a resistor R3, the gate of the field effect transistor Q1 is electrically connected to one end of the resistor R2, the other end of the resistor R2 is electrically connected to the drain of the field effect transistor Q2, and is electrically connected to the second communication module as a first connection port,
[0015] The gate of the field effect transistor Q2 is electrically connected to one end of the resistor R3, and the other end of the resistor R3 is electrically connected to the signal sending end of the external first chip.
[0016] Further, the second communication module further includes a resistor R6 and a resistor R7, the gate of the field effect transistor Q3 is electrically connected to one end of the resistor R6, the other end of the resistor R6 is electrically connected to the drain of the field effect transistor Q4, and is electrically connected to the other end of the resistor R2 as a first connection port,
[0017] The gate of the field effect transistor Q4 is electrically connected to one end of the resistor R7, and the other end of the resistor R7 is electrically connected to the signal sending end of the external second chip.
[0018] Furthermore, the first communication module also includes a field effect transistor Q5, the source of the field effect transistor Q1 and the other end of the pull-down electron R4 are electrically connected to the drain of the field effect transistor Q5, the gate of the field effect transistor Q5 is electrically connected to the gate of the field effect transistor Q2, and the source of the field effect transistor Q5 is grounded.
[0019] Furthermore, the second communication module also includes a field effect transistor Q6, the source of the field effect transistor Q3 and the other end of the pull-down electron R8 are electrically connected to the drain of the field effect transistor Q6, the gate of the field effect transistor Q6 is electrically connected to the gate of the field effect transistor Q4, and the source of the field effect transistor Q6 is grounded.
[0020] Furthermore, the first connection port and the second connection port are electrically connected via a wire or a contact.
[0021] After adopting the above technical solution, the utility model has the following advantages compared with the background technology:
[0022] In this solution, the first chip and the second chip are arranged on two different structures, and the first communication module and the second communication module are respectively arranged at the front end of the first chip and the second chip, and resistors, N-channel field effect transistors and P-channel field effect transistors with different resistance values are used to realize single-line communication between the first chip and the second chip within a distance, so that the equipment space is fully utilized to meet the communication between the first chip and the second chip, without affecting the signal, thereby improving the utilization rate of the signal line. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 It is a schematic diagram of the existing serial communication connection circuit diagram;
[0024] Figure 2 The first circuit diagram of the half-duplex serial communication circuit for single-to-double-wire conversion of the utility model;
[0025] Figure 3 This is the second circuit diagram of the half-duplex serial communication circuit for single-to-double-wire conversion described in the utility model. DETAILED DESCRIPTION
[0026] In order to make the purpose, technical solution and advantages of the utility model more clear, the utility model is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the utility model and are not used to limit the utility model.
[0027] In addition, it should be noted that the terms "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc. are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element of the present invention must have a specific orientation, and therefore cannot be understood as a limitation on the present invention.
[0028] When an element is referred to as being “fixed to” or “disposed on” or “provided on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.
[0029] Unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the utility model can be understood according to specific circumstances.
[0030] Example
[0031] Please refer to Figure 1-3 As shown, this embodiment provides a half-duplex serial communication circuit for single-to-dual line conversion, including a first communication module and a second communication module. Figure 2 The first communication module includes a field effect transistor Q1, a field effect transistor Q2, a pull-up resistor R1 and a pull-down resistor R4; the second communication module includes a field effect transistor Q3, a field effect transistor Q4, a pull-up resistor R5 and a pull-down resistor R8.
[0032] One end of the pull-up resistor R1 and the source of the field effect transistor Q2 are both electrically connected to an external power supply. The other end of the pull-up resistor R1 is electrically connected to the drain of the field effect transistor Q1, and is electrically connected to the signal receiving end of the external first chip as a first receiving port (B_RX). The gate of the field effect transistor Q1 is electrically connected to one end of the pull-down resistor R4 and the drain of the field effect transistor Q2, and is electrically connected to the second communication module as a first connection port. The gate of the field effect transistor Q2 is a first sending port (B_TX), which is electrically connected to the signal sending end of the external first chip. The other end of the pull-down resistor R4 and the source of the field effect transistor Q1 are grounded.
[0033] One end of the pull-up resistor R5 and the source of the field effect tube Q4 are both electrically connected to the external power supply. The other end of the pull-up resistor R5 is electrically connected to the drain of the field effect tube Q3, and is electrically connected to the signal receiving end of the external second chip as the second receiving port (A_RX). The gate of the field effect tube Q3 is electrically connected to one end of the pull-down resistor R8 and the drain of the field effect tube Q4, and is electrically connected to the first communication module as the second connection port. The gate of the field effect tube Q4 is the second sending port (A_TX), which is electrically connected to the signal sending end of the external second chip. The other end of the pull-down resistor R8 and the source of the field effect tube Q3 are grounded. In the present embodiment, the external power supply provides a 3.0VA voltage.
[0034] Specifically, the first communication module further includes a resistor R2 and a resistor R3, the gate of the field effect transistor Q1 is electrically connected to one end of the resistor R2, the other end of the resistor R2 is electrically connected to the drain of the field effect transistor Q2, and is electrically connected to the second communication module as a first connection port. The gate of the field effect transistor Q2 is electrically connected to one end of the resistor R3, and the other end of the resistor R3 is electrically connected to the signal sending end of the external first chip.
[0035] The second communication module also includes a resistor R6 and a resistor R7. The gate of the field effect transistor Q3 is electrically connected to one end of the resistor R6. The other end of the resistor R6 is electrically connected to the drain of the field effect transistor Q4 and is electrically connected to the other end of the resistor R2 as a first connection port. The gate of the field effect transistor Q4 is electrically connected to one end of the resistor R7. The other end of the resistor R7 is electrically connected to the signal sending end of the external second chip.
[0036] In this embodiment, the first connection port and the second connection port are electrically connected through a wire, that is, the other end of the resistor R6 is electrically connected to the other end of the resistor R2 through a wire. Similarly, the resistor R6 and the resistor R2 can be electrically connected through a contact. In this embodiment, the resistance values of the resistors R2, R3, R6, and R7 are greater than or equal to 0 ohms.
[0037] Specifically, the field effect transistor Q1 and the field effect transistor Q3 are both N-channel field effect transistors; the field effect transistor Q2 and the field effect transistor Q4 are both P-channel field effect transistors. The input capacitance values of the field effect transistors Q1, Q2, Q3 and Q4 are less than or equal to 100PF. In this embodiment, the input capacitance values of the field effect transistors Q1, Q2, Q3 and Q4 are equal to 100PF, and the input capacitance values of the field effect transistors Q1, Q2, Q3 and Q4 can also be equal to 90PF, 80PF, 70PF, 60PF or 50PF. The input capacitance values of the field effect transistors Q1, Q2, Q3 and Q4 are controlled to be less than or equal to 100PF, and the resistance values of the pull-down resistors R4 and R8 are within the range of 510Ω-2KΩ, which can effectively increase the switching rate and avoid waveform distortion. In this embodiment, the resistance of the pull-down resistor R4 and the pull-down resistor R8 is 1KΩ. Similarly, the resistance of the pull-down resistor R4 and the pull-down resistor R8 can also be 2KΩ or 510Ω.
[0038] Table 1: Figure 2 Truth table for circuit node levels
[0039] The voltage sent by the A_TX pin The voltage sent by the B_TX pin A_RX pin receives voltage B_RX pin receives voltage 1 1 1 1 0 1 0 0 1 0 0 0
[0040] Please refer to Table 1. Table 1 is Figure 2 Truth table of circuit node levels. A_TX level is high (sending data 1), MOSFET Q4's DS pin is turned off, MOSFET Q1 is pulled down by pull-down resistor R4 and turned off, MOSFET Q1's DS pin is not conducting, and B_RX pin is pulled up by pull-up resistor R1 (receiving data 1).
[0041] For example, the A_TX level is low (sending data 0), the DS pin of the field effect transistor Q4 is turned on, the DS pin of the field effect transistor Q1 is turned on, and the B_RX pin is pulled low (receiving data 0).
[0042] Conversely, sending from B_TX has the same effect.
[0043] Please refer to the attached Figure 3 The first communication module also includes a field effect transistor Q5, the source of the field effect transistor Q1 and the other end of the pull-down electron R4 are electrically connected to the drain of the field effect transistor Q5, the gate of the field effect transistor Q5 is electrically connected to the gate of the field effect transistor Q2, and the source of the field effect transistor Q5 is grounded.
[0044] The second communication module also includes a field effect transistor Q6, the source of the field effect transistor Q3 and the other end of the pull-down electron R8 are electrically connected to the drain of the field effect transistor Q6, the gate of the field effect transistor Q6 is electrically connected to the gate of the field effect transistor Q4, and the source of the field effect transistor Q6 is grounded.
[0045] In this embodiment, both the field effect transistor Q5 and the field effect transistor Q6 are N-channel field effect transistors.
[0046] Table 2: Figure 3 Truth table for circuit node levels
[0047] The voltage sent by the A_TX pin The voltage sent by the B_TX pin A_RX pin receives voltage B_RX pin receives voltage 1 1 1 1 0 1 1 0 1 0 0 1
[0048] Please refer to Table 2. Table 2 is Figure 3 Truth table of circuit node levels. A_TX level is high (sending data 1), DS pin of FET Q4 is turned off, DS pin of FET Q6 is turned on, FET Q3 is pulled down and turned off by pull-down resistor R8, A_RX pin is pulled up by pull-up resistor R5 (data 1 received), B_TX is not sending data level is high (sending data 1), DS pin of FET Q6 is turned on, DS pin of FET Q1 is turned off, B_RX pin is pulled up by pull-up resistor R1 (data 1 received);
[0049] The A_TX level is low (data 0 is sent), the DS of the field effect transistor Q6 is turned off, and the A_RX pin is pulled high by the pull-up resistor R5 (data 1 is received). The B_TX unsent data level is high (data 1 is sent), the DS of the field effect transistor Q6 is turned on, the DS of the field effect transistor Q1 is turned on, and the B_RX pin is pulled low (data 0 is received).
[0050] The effect is the same in reverse.
[0051] A set of N-channel field effect transistors is added to the receiving side of the first communication module and the second communication module, and is controlled by the transmitting end of the same party. This effectively avoids the error situation that the data sent by the first chip to the second chip is also received by the first chip, and improves the accuracy of data transmission and reception.
[0052] The above is only a preferred specific implementation of the utility model, but the protection scope of the utility model is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the utility model should be included in the protection scope of the utility model. Therefore, the protection scope of the utility model should be based on the protection scope of the claims.
Claims
1. A half-duplex serial communication circuit for single-to-double-wire conversion, characterized in that: comprising a first communication module and a second communication module, The first communication module includes a field effect transistor Q1, a field effect transistor Q2, a pull-up resistor R1 and a pull-down resistor R4; the second communication module includes a field effect transistor Q3, a field effect transistor Q4, a pull-up resistor R5 and a pull-down resistor R8; One end of the pull-up resistor R1 and the source of the field effect transistor Q2 are both electrically connected to an external power supply, the other end of the pull-up resistor R1 is electrically connected to the drain of the field effect transistor Q1, and is electrically connected to the signal receiving end of the external first chip as a first receiving port, the gate of the field effect transistor Q1 is electrically connected to one end of the pull-down resistor R4 and the drain of the field effect transistor Q2, and is electrically connected to the second communication module as a first connection port, the gate of the field effect transistor Q2 is a first sending port, and is electrically connected to the signal sending end of the external first chip, and the other end of the pull-down resistor R4 and the source of the field effect transistor Q1 are grounded; One end of the pull-up resistor R5 and the source of the field effect transistor Q4 are both electrically connected to an external power supply, the other end of the pull-up resistor R5 is electrically connected to the drain of the field effect transistor Q3, and is electrically connected to the signal receiving end of the external second chip as a second receiving port, the gate of the field effect transistor Q3 is electrically connected to one end of the pull-down resistor R8 and the drain of the field effect transistor Q4, and is electrically connected to the first communication module as a second connection port, the gate of the field effect transistor Q4 is a second sending port, and is electrically connected to the signal sending end of the external second chip, and the other end of the pull-down resistor R8 and the source of the field effect transistor Q3 are grounded.
2. The half-duplex serial communication circuit for single-to-double-wire conversion according to claim 1 is characterized in that: The field effect transistor Q1 and the field effect transistor Q3 are both N-channel field effect transistors; the field effect transistor Q2 and the field effect transistor Q4 are both P-channel field effect transistors.
3. The half-duplex serial communication circuit for single-to-double-wire conversion according to claim 1, characterized in that: The input capacitance values of the field effect transistors Q1, Q2, Q3 and Q4 are less than or equal to 100PF.
4. The half-duplex serial communication circuit for single-to-double-wire conversion according to claim 1, characterized in that: The first communication module further includes a resistor R2 and a resistor R3. The gate of the field effect transistor Q1 is electrically connected to one end of the resistor R2. The other end of the resistor R2 is electrically connected to the drain of the field effect transistor Q2 and is electrically connected to the second communication module as a first connection port. The gate of the field effect transistor Q2 is electrically connected to one end of the resistor R3, and the other end of the resistor R3 is electrically connected to the signal sending end of the external first chip.
5. The half-duplex serial communication circuit for single-to-double-wire conversion according to claim 4 is characterized in that: The second communication module further includes a resistor R6 and a resistor R7. The gate of the field effect transistor Q3 is electrically connected to one end of the resistor R6. The other end of the resistor R6 is electrically connected to the drain of the field effect transistor Q4 and is electrically connected to the other end of the resistor R2 as a first connection port. The gate of the field effect transistor Q4 is electrically connected to one end of the resistor R7, and the other end of the resistor R7 is electrically connected to the signal sending end of the external second chip.
6. The half-duplex serial communication circuit for single-to-double-wire conversion according to claim 4, characterized in that: The first communication module also includes a field effect transistor Q5, the source of the field effect transistor Q1 and the other end of the pull-down electron R4 are electrically connected to the drain of the field effect transistor Q5, the gate of the field effect transistor Q5 is electrically connected to the gate of the field effect transistor Q2, and the source of the field effect transistor Q5 is grounded.
7. The half-duplex serial communication circuit for single-to-double-wire conversion according to claim 5, characterized in that: The second communication module also includes a field effect transistor Q6, the source of the field effect transistor Q3 and the other end of the pull-down electron R8 are electrically connected to the drain of the field effect transistor Q6, the gate of the field effect transistor Q6 is electrically connected to the gate of the field effect transistor Q4, and the source of the field effect transistor Q6 is grounded.
8. The half-duplex serial communication circuit for single-to-double-wire conversion according to claim 1, characterized in that: The first connection port and the second connection port are electrically connected via a wire or a contact.