Direct current commutation controller

Abstract

The utility model relates to the technical field of motors, particularly provides a direct current commutation controller, and aims to solve the problem of how to effectively avoid the risk of simultaneous conduction of NMOS (N-channel Metal Oxide Semiconductor) and PMOS (P-channel Metal Oxide Semiconductor) tubes of the direct current commutation controller. In order to achieve the purpose, the direct-current reversing controller comprises two driving circuits of the same structure, and each driving circuit comprises a first control module, a second control module, a driving PMOS tube, a driving NMOS tube and a logic interlocking module. The logic interlocking module can realize that after one of the driving PMOS tube and the driving NMOS tube in the same driving circuit is switched off, the other one is switched on; the driving PMOS tube and the driving NMOS tube can be effectively prevented from being conducted at the same time, the circuit short-circuit damage risk caused by the fact that the driving PMOS tube and the driving NMOS tube are conducted at the same time can be prevented, and the circuit is simple, reliable and low in cost.

Description

Technical Field

[0001] The present application relates to the field of motor technology, and specifically provides a direct current commutation controller. Background Art

[0002] The DC power commutation controller is a device used to control the direction of rotation of electric push rod motors, DC motors and other rotating equipment. The control signal from the PLC (Programmable Logic Controller) / DCS (Distributed Control System) and other systems can be converted into the corresponding power output voltage after passing through the DC power commutation controller, and then used to control the rotation direction of the motor.

[0003] In traditional industrial control, electromagnetic relays are generally used for DC motor commutation control. However, electromagnetic relays have defects such as slow response time, short life span, and large switching losses. Therefore, more and more industrial occasions have begun to use DC power commutation controllers composed of MOS tubes (Metal-Oxide-Semiconductor Field-Effect Transistor) to replace traditional electromagnetic relays.

[0004] The DC power commutation controller currently on the market, which is composed of MOS tubes, may be turned on at the same time due to the existence of Miller capacitance and dead zone of the MOS tube when the input changes rapidly, thus causing circuit short circuit damage, which brings major hidden dangers to industrial control.

[0005] At the same time, the DC power commutation controller composed of MOS tubes on the market cannot effectively filter out millisecond-level interference on the input side. If a filter capacitor is added between the gate and source of the MOS tube, the risk of NMOS and PMOS being turned on at the same time will be further increased.

[0006] Accordingly, the art needs a new DC commutation controller solution to solve the above problems. Utility Model Content

[0007] In order to overcome the above-mentioned defects, the present application is proposed to provide a solution or at least partially solve the problem of how to effectively avoid the risk of the NMOS and PMOS tubes of the DC commutation controller being turned on at the same time.

[0008] In a first aspect, the present application provides a DC commutation controller, the DC commutation controller comprising two drive circuits with the same structure;

[0009] The driving circuit includes a first control module, a second control module, a driving PMOS tube, a driving NMOS tube and a logic interlocking module;

[0010] The logic interlock module is used to realize that after one of the driving PMOS tube and the driving NMOS tube in the same driving circuit is turned off, the other is turned on again;

[0011] The first end of the first control module is connected to a forward control signal, and the first end of the second control module is connected to a reverse control signal;

[0012] The second end of the first control module is connected to the gate of the driving PMOS tube, and the third end of the first control module is connected to the logic interlock module;

[0013] The second end of the second control module is connected to the driving voltage, and the third end of the second control module is connected to the gate of the driving NMOS tube; the source of the driving PMOS tube is connected to the driving voltage, and the source of the driving NMOS tube is grounded;

[0014] The drain of the driving PMOS tube is connected to the drain of the driving NMOS tube to form an output control terminal of the driving circuit.

[0015] In a technical solution of the above-mentioned DC commutation controller, the logic interlock module includes a first small signal NMOS tube and a second small signal NMOS tube, the drain of the first small signal NMOS tube is connected to the third end of the first control module, the gate of the first small signal NMOS tube is connected to the drain of the second small signal NMOS tube, the sources of the first small signal NMOS tube and the second small signal NMOS tube are grounded, and the gate of the second small signal NMOS tube is connected to the gate of the driving NMOS tube.

[0016] In a technical solution of the above-mentioned DC commutation controller, the logic interlock module also includes a third resistor and a fourth resistor, the first ends of the third resistor and the fourth resistor are both connected to the gate of the first small signal NMOS tube, the second end of the third resistor is connected to the driving voltage; the second end of the fourth resistor is grounded.

[0017] In one technical solution of the above DC commutation controller, the DC commutation controller further includes a first filter capacitor and a second filter capacitor;

[0018] The first filter capacitor is arranged between the gate and the source of the driving PMOS tube;

[0019] The second filter capacitor is arranged between the gate and the source of the driving NMOS tube.

[0020] In a technical solution of the above DC commutation controller, the DC commutation controller further includes a first voltage regulator diode and a second voltage regulator diode;

[0021] The anode of the first voltage stabilizing diode is connected to the gate of the driving PMOS tube, and the cathode of the first voltage stabilizing diode is connected to the source of the driving PMOS tube;

[0022] The anode of the second voltage stabilizing diode is connected to the source of the driving NMOS tube, and the cathode of the second voltage stabilizing diode is connected to the gate of the driving NMOS tube.

[0023] In a technical solution of the above-mentioned DC commutation controller, the DC commutation controller also includes a first voltage-dividing resistor and a sixth voltage-dividing resistor; the first voltage-dividing resistor is arranged between the gate and the source of the driving PMOS tube; the sixth voltage-dividing resistor is arranged between the gate and the source of the driving NMOS tube.

[0024] In a technical solution of the above-mentioned DC commutation controller, the DC commutation controller also includes a first voltage-dividing resistor and a fifth voltage-dividing resistor, the first voltage-dividing resistor is arranged between the first end of the first control module and the gate of the driving PMOS tube, and the fifth voltage-dividing resistor is arranged between the second end of the second control module and the driving voltage.

[0025] In a technical solution of the above DC commutation controller, the first control module and the second control module are both photoelectric couplers; and the fourth ends of the first control module and the second control module are both connected to a common control signal.

[0026] In a technical solution of the above DC commutation controller, the first control module is an NMOS tube, the second control module is an optocoupler; the fourth end of the second control module is connected to the common control signal

[0027] In a technical solution of the above DC commutation controller, the source of the driving PMOS tube is connected to the driving voltage, and the source of the driving NMOS tube is grounded.

[0028] The above one or more technical solutions of this application have at least one or more of the following

[0029] Beneficial effects:

[0030] In the technical solution for implementing the present application, the DC commutation controller of the present application includes two drive circuits with the same structure, each of which includes a first control module, a second control module, a driving PMOS tube, a driving NMOS tube and a logic interlocking module. The logic interlocking module can realize that after one of the driving PMOS tube and the driving NMOS tube is turned off in the same drive circuit, the other is turned on again; the first end of the first control module is connected to the forward control signal, and the first end of the second control module is connected to the reverse control signal; the second end of the first control module is connected to the gate of the driving PMOS tube, and the third end of the first control module is connected to the logic interlocking module; the second end of the second control module is connected to the driving voltage, and the third end of the second control module is connected to the gate of the driving NMOS tube; the source of the driving PMOS tube is connected to the driving voltage, and the source of the driving NMOS tube is grounded; the drain of the driving PMOS tube is connected to the drain of the driving NMOS tube to form an output control terminal. Through the above-mentioned setting method, the present application can effectively avoid driving the PMOS tube and the NMOS tube to be turned on at the same time, and can prevent the risk of circuit short circuit damage caused by driving the PMOS tube and the NMOS tube to be turned on at the same time. The circuit is simple, reliable and low-cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The disclosure of the present application will become more easily understood with reference to the accompanying drawings. It is easy for those skilled in the art to understand that these drawings are only for illustrative purposes and are not intended to limit the scope of protection of the present application. In addition, similar numbers in the drawings are used to represent similar components, among which:

[0032] Figure 1 is a schematic diagram of a main structural block diagram of a DC commutation controller according to an embodiment of the present application;

[0033] Figure 2 It is a schematic diagram of the main structure block diagram of a DC commutation controller according to an implementation method of an embodiment of the present application;

[0034] Figure 3 It is a schematic diagram of the connection relationship between a DC commutation controller and a control side and an electric push rod side according to an implementation of an embodiment of the present application.

[0035] Reference numerals list :

[0036] 1: driving circuit; 11: first control module; 12: second control module; 13: driving PMOS tube; 14: driving NMOS tube; 15: logic interlocking module. DETAILED DESCRIPTION

[0037] Some embodiments of the present application are described below with reference to the accompanying drawings. Those skilled in the art should understand that these embodiments are only used to explain the technical principles of the present application and are not intended to limit the protection scope of the present application.

[0038] In the description of the present application, "module" and "processor" may include hardware, software or a combination of the two. A module may include hardware circuits, various suitable sensors, communication ports, memory, and may also include software parts, such as program code, or a combination of software and hardware. The processor may be a central processing unit, a microprocessor, an image processor, a digital signal processor or any other suitable processor. The processor has data and / or signal processing functions. The processor may be implemented in software, hardware or a combination of the two. Non-temporary computer-readable storage media include any suitable medium that can store program code, such as a disk, a hard disk, an optical disk, a flash memory, a read-only memory, a random access memory, etc. The term "A and / or B" means all possible combinations of A and B, such as only A, only B or A and B. The term "at least one A or B" or "at least one of A and B" has a similar meaning to "A and / or B" and may include only A, only B or A and B. The singular terms "one" and "the" may also include plural forms.

[0039] Terminology explanation:

[0040] NMOS (N-Metal-Oxide-Semiconductor), N-channel metal oxide semiconductor.

[0041] PMOS (P-Metal-Oxide-Semiconductor), P-channel metal oxide semiconductor.

[0042] See attached Figure 1 , Figure 1 FIG. 1 is a schematic diagram of the main structure block diagram of a DC commutation controller according to an embodiment of the present application. Figure 1As shown, the DC commutation controller in the embodiment of the present application may include two drive circuits 1 with the same structure; the drive circuit 1 includes a first control module 11, a second control module 12, a drive PMOS tube 13 (Q1), a drive NMOS tube 14 (Q2) and a logic interlock module 15; the logic interlock module 15 is used to realize that after one of the drive PMOS tube 13 and the drive NMOS tube 14 in the same drive circuit 1 is turned off, the other is turned on again; the first end of the first control module 11 is connected to the positive control signal (I+), and the first end of the second control module 12 is connected to the reverse control signal (I-) connection; the second end of the first control module 11 is connected to the gate of the driving PMOS tube 13, and the third end of the first control module 11 is connected to the logic interlock module 15; the second end of the second control module 12 is connected to the driving voltage (VDD), and the third end of the second control module 12 is connected to the gate of the driving NMOS tube 14; the source of the driving PMOS tube 13 is connected to the driving voltage (VDD), and the source of the driving NMOS tube 14 is grounded; the drain of the driving PMOS tube 13 is connected to the drain of the driving NMOS tube 14 to form the output control end (A, B) of the driving circuit 1.

[0043] In one implementation of the present application, Figure 1 As shown, the logic interlock module 15 may include a first small signal NMOS tube (Q3) and a second small signal NMOS tube (Q4), the drain of the first small signal NMOS tube is connected to the third end of the first control module 11, the gate of the first small signal NMOS tube is connected to the drain of the second small signal NMOS tube, the sources of the first small signal NMOS tube and the second small signal NMOS tube are grounded, and the gate of the second small signal NMOS tube is connected to the gate of the driving NMOS tube 14. The first small signal NMOS tube and the second small signal NMOS tube constitute the logic interlock module 15, which can ensure that after one of the driving PMOS tube 13 and the driving NMOS tube 14 in the same driving circuit 1 is turned off, the other is turned on again.

[0044] In one embodiment, if Figure 1 As shown, the logic interlock module 15 also includes a third resistor (R3) and a fourth resistor (R4), the first ends of the third resistor and the fourth resistor are both connected to the gate of the first small signal NMOS tube, the second end of the third resistor is connected to the driving voltage; the second end of the fourth resistor is grounded.

[0045] In one embodiment, if Figure 1 As shown, the DC commutation controller may further include a first filter capacitor (C1) and a second filter capacitor (C2); the first filter capacitor is arranged between the gate and source of the driving PMOS tube 13; the second filter capacitor is arranged between the gate and source of the driving NMOS tube 14. The arrangement of the first filter capacitor and the second filter capacitor can filter out millisecond-level pulse interference on the input side.

[0046] In one embodiment, if Figure 1 As shown, the DC commutation controller may further include a first zener diode (Z1) and a second zener diode (Z2); the anode of the first zener diode is connected to the gate of the driving PMOS tube 13, and the cathode of the first zener diode is connected to the source of the driving PMOS tube 13; the anode of the second zener diode is connected to the source of the driving NMOS tube 14, and the cathode of the second zener diode is connected to the gate of the driving NMOS tube 14. The arrangement of the first zener diode can ensure that the voltage between the gate and the source of the driving PMOS tube 13 does not exceed the maximum withstand voltage of the driving PMOS tube 13. The arrangement of the second zener diode can ensure that the voltage between the gate and the source of the driving NMOS tube 14 does not exceed the maximum withstand voltage of the driving NMOS tube 14.

[0047] In one embodiment, if Figure 1 As shown, the DC commutation controller may further include a first voltage-dividing resistor (R1) and a sixth voltage-dividing resistor (R6); the first voltage-dividing resistor is arranged between the gate and the source of the driving PMOS tube 13; the sixth voltage-dividing resistor is arranged between the gate and the source of the driving NMOS tube 14.

[0048] In one embodiment, if Figure 1 As shown, the DC commutation controller may further include a first voltage-dividing resistor (R1) and a fifth voltage-dividing resistor (R5), wherein the first voltage-dividing resistor is arranged between the first end of the first control module 11 and the gate of the driving PMOS tube 13, and the fifth voltage-dividing resistor is arranged between the second end of the second control module 12 and the driving voltage.

[0049] In one embodiment, if Figure 1 As shown, the first control module 11 and the second control module 12 are both photoelectric couplers (E1, E2); the fourth ends of the first control module 11 and the second control module 12 are both connected to a common control signal (COM).

[0050] In one embodiment, if Figure 1 As shown, the source of the driving PMOS tube 13 is connected to the driving voltage, and the source of the driving NMOS tube 14 is grounded.

[0051] See attached Figure 3 , Figure 3 Schematic diagram of the connection relationship between the DC commutation controller, the control side and the electric push rod side according to an implementation of the embodiment of the present application. Figure 3 As shown, the control side provides control signals (I+, I-) for the switching power supply 1; the DC commutation controller is provided with driving voltages (VCC, GND) by the switching power supply 2; and the output control terminals (A, B) of the DC commutation controller are connected to the electric push rod motor. Figure 3,by Figure 1 Taking the DC commutation controller as an example, the working process of the DC commutation controller is explained.

[0052] 1. When I+=VDD and I- is in high-impedance state, I+ forms a loop with the common control signal COM terminal through the primary side of the photocoupler E1, the output transistor side of the photocoupler E1 is turned on, the driving PMOS tube 13 corresponding to the output control terminal A is turned on, and the driving NMOS tube 14 corresponding to the output control terminal B is turned on, and the VDD voltage is output through the output control terminal A, and then finally flows back to the ground from the output control terminal B after passing through the load, thereby realizing the positive control of the electric push rod.

[0053] 2. When I-=VDD and I+ is in high-impedance state, I- forms a loop with the common control signal COM terminal through the primary side of the photocoupler E2, and the output transistor side of the photocoupler E2 is turned on; the driving NMOS tube 14 corresponding to the output control terminal A is turned on, and the driving PMOS tube 13 corresponding to the output control terminal B is turned on, and the VDD voltage is output through the output control terminal B, and then finally flows back to the ground from the output control terminal A after passing through the load, thereby realizing reverse control of the electric push rod.

[0054] 3. When I+ and I- are both VDD or high-impedance at the same time, due to the existence of logic interlock, the first control module 11, and the second control module 12, the optocouplers E1 and E2 cannot form a loop and are both not conducting. The corresponding output-side driving PMOS tube 13 and driving NMOS tube 14 are both turned off, and the electric push rod does not move.

[0055] Next, combine Figure 1 The working process of the logic interlock module 15 when the input control signal changes rapidly is described.

[0056] When I+=VDD and I- is in a high-impedance state, the driving PMOS tube 13 corresponding to the output control terminal A and the driving NMOS tube 14 corresponding to the output control terminal B are turned on; at this time, if the input is switched to I-=VDD and I+ is in a high-impedance state, the driving NMOS tube 14 corresponding to the output control terminal A and the driving PMOS tube 13 corresponding to the output control terminal B will switch from the off state to the on state, and the driving PMOS tube 13 corresponding to the output control terminal A and the driving NMOS tube 14 corresponding to the output control terminal B will switch from the on state to the off state. Taking the output control terminal A as an example, due to the switching dead zone of the MOS tube, and the introduction of the external filter capacitor further increases the overlapping interval of the dead zone, when the input changes rapidly, when the driving PMOS tube 13 corresponding to the output control terminal A has not been completely turned off, turning on the driving NMOS tube 14 of the output control terminal A will cause the risk of both tubes being turned on at the same time and short-circuiting; similarly, when the input switches from I-=VDD, I+ is a high-impedance state to I+=VDD, I- is a high-impedance state, the driving PMOS tube 13 corresponding to the output control terminal A and the driving NMOS tube 14 corresponding to the output control terminal B will switch from off to on, and the driving NMOS tube 14 corresponding to the output control terminal A and the driving PMOS tube 13 corresponding to the output control terminal B will switch from on to off. Due to the existence of the switching dead zone, there is also the risk of short circuit.

[0057] In order to avoid short circuit caused by overlapping dead zones of the driving NMOS tube 14 and the driving PMOS tube 13 of the same driving circuit 1, a logic interlock module 15 can be added to the gate driving position of the driving NMOS tube 14 and the driving PMOS tube 13. That is, the first small signal NMOS tube and the second small signal NMOS tube (Q3 and Q4) and the third resistor and the fourth resistor (R3 and R4) are introduced. Among them, VGS1 (MAX) of Q4 is less than VGS2 (MIN) of Q2. Since the conduction condition of NMOS is that the corresponding gate-source voltage is greater than the rated VGS, VGS has a certain range. Under extreme conditions, the gate-source voltage of NMOS is greater than VGS (MAX) before it can be fully turned on, and less than VGS (MIN) before it can be fully turned off. Since VGS1 (MAX) of Q4 is less than VGS2 (MIN) of Q2, the turn-on time of Q2 lags behind Q4, and the turn-off time of Q4 lags behind Q2.

[0058] Taking the output control terminal A as an example, when the driving PMOS tube 13----Q1 switches from on to off, and the driving NMOS tube 14----Q2 switches from off to on, that is, the voltage at point N in the figure switches from ground to the voltage divided by the power supply VDD through resistors R5 and R6. Based on the above analysis, Q4 is turned on before Q2, and after Q4 is turned on, the connection point between resistors R3 and R4 is in a grounded state, that is, the gate voltage of Q3 is 0V, and Q3 is turned off; the VDD level cannot eventually flow back to the ground through the voltage divided by resistors R1 and R2, so the gate level of Q1 is locked at VDD, and the voltage difference between the gate and the source is 0V, so Q1 is turned off, and then Q2 is turned on after the voltage between the gate and the source of Q2 is higher than the rated VGS2, which avoids Q2 and Q1 being turned on at the same time.

[0059] When the driving PMOS tube 13----Q1 switches from off to on, the driving NMOS tube 14----Q2 switches from on to off, that is, Figure 1 The voltage at point N in the circuit is switched from the power supply VDD to the ground through the voltage divider of resistors R5 and R6. Based on the above analysis, Q4 is turned off after Q2. After Q2 is turned off, Q4 is turned off after the voltage between the gate and source of Q4 is lower than the rated VGS1. After Q4 is turned off, the connection point of resistors R3 and R4 divides the VDD level, that is, the gate voltage of Q3 is the voltage divider of R3 and R4, which is higher than the rated VGS of Q3, and Q3 is turned on; the VDD level finally flows back to the ground through the voltage divider of resistors R1 and R2, and the gate level of Q1 is the voltage divider of resistors R1 and R2 to VDD. At this time, Q1 is turned on, which avoids Q2 and Q1 from being turned on at the same time.

[0060] In one embodiment, please refer to the attached Figure 2 , Figure 2 1 is a schematic diagram of the main structure block diagram of a DC commutation controller according to an implementation of an embodiment of the present application. Figure 2 As shown, the first control module 11 can be an NMOS tube (Q5), and the second control module 12 can be an optocoupler (E2); the fourth end of the second control module 12 is connected to the common control signal. The on and off control of Q5 is realized through the logic interlock module 15 and the input control signal. It should be noted that, in addition to Q5, Figure 2 The DC commutation controller in Figure 1 The structures of the DC commutation controllers in the embodiment are the same and will not be described here for simplicity.

[0061] It should be pointed out that although the various steps in the above embodiments are described in a specific order, those skilled in the art can understand that in order to achieve the effect of the present application, different steps do not have to be executed in such an order. They can be executed simultaneously (in parallel) or in other orders. These changes are within the scope of protection of the present application.

[0062] Further, it should be understood that since the setting of each module is only for illustrating the functional units of the device of the present application, the physical devices corresponding to these modules may be the processor itself, or a part of the software in the processor, a part of the hardware, or a part of the combination of software and hardware. Therefore, the number of each module in the figure is only schematic.

[0063] It is understood by those skilled in the art that each module in the device can be adaptively split or merged. Such splitting or merging of specific modules will not cause the technical solution to deviate from the principle of the present application, and therefore, the technical solutions after splitting or merging will fall within the protection scope of the present application.

[0064] So far, the technical solutions of the present application have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present application is obviously not limited to these specific embodiments. Without departing from the principles of the present application, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the protection scope of the present application.

Claims

1. A DC commutation controller, characterized in that: The DC commutation controller includes two drive circuits with the same structure; The driving circuit includes a first control module, a second control module, a driving PMOS tube, a driving NMOS tube and a logic interlocking module; The logic interlock module is used to realize that after one of the driving PMOS tube and the driving NMOS tube in the same driving circuit is turned off, the other is turned on again; The first end of the first control module is connected to a forward control signal, and the first end of the second control module is connected to a reverse control signal; The second end of the first control module is connected to the gate of the driving PMOS tube, and the third end of the first control module is connected to the logic interlock module; The second end of the second control module is connected to the driving voltage, and the third end of the second control module is connected to the gate of the driving NMOS tube; the source of the driving PMOS tube is connected to the driving voltage, and the source of the driving NMOS tube is grounded; The drain of the driving PMOS tube is connected to the drain of the driving NMOS tube to form an output control terminal of the driving circuit.

2. The DC commutation controller according to claim 1, characterized in that: The logic interlock module includes a first small signal NMOS tube and a second small signal NMOS tube, the drain of the first small signal NMOS tube is connected to the third end of the first control module, the gate of the first small signal NMOS tube is connected to the drain of the second small signal NMOS tube, the sources of the first small signal NMOS tube and the second small signal NMOS tube are grounded, and the gate of the second small signal NMOS tube is connected to the gate of the driving NMOS tube.

3. The DC commutation controller according to claim 2, characterized in that: The logic interlock module also includes a third resistor and a fourth resistor, the first ends of the third resistor and the fourth resistor are both connected to the gate of the first small signal NMOS tube, the second end of the third resistor is connected to the driving voltage; the second end of the fourth resistor is grounded.

4. The DC commutation controller according to claim 1, characterized in that: The DC commutation controller also includes a first filter capacitor and a second filter capacitor; The first filter capacitor is arranged between the gate and the source of the driving PMOS tube; The second filter capacitor is arranged between the gate and the source of the driving NMOS tube.

5. The DC commutation controller according to claim 1, characterized in that: The DC commutation controller also includes a first voltage stabilizing diode and a second voltage stabilizing diode; The anode of the first voltage stabilizing diode is connected to the gate of the driving PMOS tube, and the cathode of the first voltage stabilizing diode is connected to the source of the driving PMOS tube; The anode of the second voltage stabilizing diode is connected to the source of the driving NMOS tube, and the cathode of the second voltage stabilizing diode is connected to the gate of the driving NMOS tube.

6. The DC commutation controller according to claim 1, characterized in that: The DC commutation controller further includes a first voltage-dividing resistor and a sixth voltage-dividing resistor; the first voltage-dividing resistor is arranged between the gate and the source of the driving PMOS tube; the sixth voltage-dividing resistor is arranged between the gate and the source of the driving NMOS tube.

7. The DC commutation controller according to claim 1, characterized in that: The DC commutation controller also includes a first voltage-dividing resistor and a fifth voltage-dividing resistor, wherein the first voltage-dividing resistor is arranged between the first end of the first control module and the gate of the driving PMOS tube, and the fifth voltage-dividing resistor is arranged between the second end of the second control module and the driving voltage.

8. The DC commutation controller according to claim 1, characterized in that: The first control module and the second control module are both photoelectric couplers; the fourth ends of the first control module and the second control module are both connected to a common control signal.

9. The DC commutation controller according to claim 1, characterized in that: The first control module is an NMOS tube, and the second control module is a photoelectric coupler; the fourth end of the second control module is connected to the common control signal.

10. The DC commutation controller according to any one of claims 1 to 9, characterized in that: The source of the driving PMOS tube is connected to the driving voltage, and the source of the driving NMOS tube is grounded.

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