PHEMT (Pseudomorphic High Electron Mobility Transistor) process-based inverter circuit for improving input low level
By designing an inverter circuit with pull-up and pull-down units in the PHEMT process, using a combination of metal oxide semiconductor field effect transistors and resistors, transistors or diodes, the problems of weak load capacity and fixed input voltage in the inverter circuit are solved. Higher noise resistance and lower power consumption are achieved.
Patent Information
- Application Number
- CN202323384834.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-12
- Publication Date
- 2024-12-24
- Estimated Expiration
- 2033-12-12
AI Technical Summary
The existing PHEMT integrated circuit inverter circuit has weak load capacity and fixed input voltage level, resulting in weak anti-interference ability and unable to meet high performance requirements.
A PHEMT process-based inverter circuit is designed, including a pull-up unit and a pull-down unit. The second metal oxide semiconductor field effect transistor is combined with a resistor, transistor or diode to form a pull-up and pull-down network that suppresses current, and improves the pull-up and pull-down network. Input low level range and noise immunity.
Effectively reduce current, improve input low-level range, enhance noise resistance, meet the design needs of PHEMT integrated circuits, and reduce chip area and cost.
Smart Images
Figure CN222234839U_ABST
Abstract
Description
Technical Field
[0001] The utility model is applied to the technical field of integrated circuits, and in particular relates to an inverter circuit of an integrated circuit in a PHEMT process. Background Art
[0002] As a commonly used logic circuit, the inverter is mainly used to convert the logic input signal and then output it in reverse, so it is widely used in the design of integrated circuits. Especially in RF integrated circuits on PHEMT process, the inverter is usually used in the logic decoder or signal buffer on PHEMT process.
[0003] With the continuous development of PHEMT integrated circuits and their application scenarios, the performance requirements for the cost, response speed, leakage current, etc. of the overall chip of PHEMT integrated circuits are becoming higher and higher. However, the existing inverter design scheme can no longer meet the actual needs.
[0004] See also Figure 1 , which is a schematic diagram of the structure of a traditional inverter circuit. As shown in the figure, the traditional inverter circuit includes a load resistor R1 and a metal oxide semiconductor field effect transistor M1. Among them, the input voltage Vin is applied to the gate G of the metal oxide semiconductor field effect transistor M1. Before reaching the threshold voltage (Vth) of the metal oxide semiconductor field effect transistor M1 (that is, the input voltage is at a low level), M1 is not turned on, and the output voltage Vout is equal to the power supply voltage Vdd; when the voltage applied to the gate G is greater than the threshold voltage (Vth) of the metal oxide semiconductor field effect transistor M1 (that is, the input voltage is at a high level), a conductive channel is generated between the source S and the drain D of M1, the metal oxide semiconductor field effect transistor M1 is turned on, and the output voltage Vout is 0.
[0005] Furthermore, the MOSFET M1 and the resistor R2 in the conventional inverter circuit jointly realize an inversion function.
[0006] Although this traditional Inverter circuit solution is simple to implement, it has weak load capacity and the high and low levels of the input voltage are fixed (determined by the threshold voltage (Vth) of the metal oxide semiconductor field effect transistor M1 itself). Therefore, the low level range of the input level is small, resulting in weak anti-interference and imaging capabilities for the input signal.
[0007] Furthermore, there is a big contradiction between the output current and the load capacity of the traditional Inverter circuit solution, that is, reducing the current can only increase the load resistance R1, and the load capacity is also reduced accordingly, and the response speed will also decrease. Utility Model Content
[0008] Aiming at the problem that the traditional Inverter circuit has weak load capacity and fixed high and low levels of input voltage, the purpose of the utility model is to provide an inverter circuit based on PHEMT process to improve the input low level, which can effectively improve the input low level range and load capacity.
[0009] In order to achieve the above-mentioned object, the utility model provides an inverter circuit for improving input low level based on PHEMT process, comprising a pull-up unit and a pull-down unit, wherein the pull-up unit comprises a second metal oxide semiconductor field effect transistor (M2) and a second resistor (R2); the pull-down unit comprises a first metal oxide semiconductor field effect transistor (M1) and a first resistor (R1), and a third resistor (R3);
[0010] The drain (D) of the second metal oxide semiconductor field effect transistor (M2) is connected to the power supply terminal (Vdd), a second resistor (R2) is connected between the gate (G) and the source (S), and the gate (G) of the second metal oxide semiconductor field effect transistor (M2) is connected to the drain (D) of the first metal oxide semiconductor field effect transistor (M1) as an output terminal (Vout) of the inverter circuit;
[0011] The gate (G) of the first metal oxide semiconductor field effect transistor (M1) is connected to the input terminal (Vin) through the first resistor (R1), connected to the source (S) through the third resistor (R3) and grounded.
[0012] Furthermore, the second metal oxide semiconductor field effect transistor (M2) is a PHEMT D-Mode device, and the threshold voltage is a negative value; the second metal oxide semiconductor field effect transistor (M2) cooperates with the second resistor (R2) to form a pull-up network for suppressing the Ids current of the second metal oxide semiconductor field effect transistor (M2).
[0013] Furthermore, the first metal oxide semiconductor field effect transistor (M1) is a PHEMT E-Mode device.
[0014] In order to achieve the above-mentioned object, the utility model provides an inverter circuit for improving input low level based on PHEMT process, comprising a pull-up unit and a pull-down unit, wherein the pull-up unit comprises a second metal oxide semiconductor field effect transistor (M2) and a second resistor (R2); the pull-down unit comprises a triode and a first resistor (R1), and a third resistor (R3);
[0015] The drain (D) of the second metal oxide semiconductor field effect transistor (M2) is connected to the power supply terminal (Vdd), a second resistor (R2) is connected between the gate (G) and the source (S), and the gate (G) of the second metal oxide semiconductor field effect transistor (M2) is connected to the collector (C) of the transistor as the output terminal (Vout) of the inverter circuit;
[0016] The base of the transistor is connected to the input terminal (Vin) through a first resistor (R1), and is connected to the emitter (E) of the transistor through a third resistor (R3) and is grounded.
[0017] In order to achieve the above-mentioned object, the utility model provides an inverter circuit for improving input low level based on PHEMT process, comprising a pull-up unit and a pull-down unit, wherein the pull-up unit comprises a second metal oxide semiconductor field effect transistor (M2) and a second resistor (R2); the pull-down unit comprises a first metal oxide semiconductor field effect transistor (M1) and at least one diode (VD);
[0018] The drain (D) of the second metal oxide semiconductor field effect transistor (M2) is connected to the power supply terminal (Vdd), a second resistor (R2) is connected between the gate (G) and the source (S), and the gate (G) of the second metal oxide semiconductor field effect transistor (M2) is connected to the drain (D) of the first metal oxide semiconductor field effect transistor (M1) as an output terminal (Vout) of the inverter circuit;
[0019] The gate (G) of the first metal oxide semiconductor field effect transistor (M1) is connected to the input terminal (Vin) through at least one diode (VD), and the source (S) is connected to the ground.
[0020] Furthermore, a plurality of diodes (VD) are connected in series in sequence.
[0021] The inverter circuit solution for improving the input low level based on the PHEMT process provided by the utility model can effectively reduce the current and increase the input low level range, thereby reducing power consumption and enhancing the anti-noise and interference capabilities of the entire circuit, and can better meet the design requirements for PHEMT integrated circuits in practical applications.
[0022] Furthermore, the inverter circuit solution for improving input low level based on PHEMT technology provided by the utility model can effectively improve the circuit load capacity.
[0023] Furthermore, the inverter circuit solution for improving input low level based on PHEMT technology provided by the utility model has a small chip footprint and low cost. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] The present invention is further described below in conjunction with the accompanying drawings and specific implementations.
[0025] Figure 1 is the schematic diagram of a conventional inverter circuit;
[0026] Figure 2 It is a schematic diagram of an inverter circuit for improving input low level based on PHEMT technology in Example 1 of the utility model;
[0027] Figure 3 It is a schematic diagram of an inverter circuit for improving input low level based on PHEMT technology in Example 2 of the utility model;
[0028] Figure 4 This is a schematic diagram of an inverter circuit for improving input low level based on PHEMT technology in Example 3 of the utility model. DETAILED DESCRIPTION
[0029] In order to make the technical means, creative features, objectives and effects achieved by the present invention easy to understand, the present invention is further described below with reference to specific illustrations.
[0030] The utility model aims to solve the problems existing in traditional inverter circuits and provides an inverter circuit solution based on the PHEMT process, which occupies a smaller chip area, consumes lower current, and has better anti-noise ability, thereby better meeting the design requirements for PHEMT integrated circuits in practical applications.
[0031] Example 1
[0032] See also Figure 2 , which is a schematic diagram of an inverter circuit for improving input low level based on PHEMT process given in this example.
[0033] The inverter circuit for improving input low level based on the PHEMT process comprises two parts: a pull-up unit I and a pull-down unit II.
[0034] The pull-up unit I includes a second metal oxide semiconductor field effect transistor M2 (hereinafter referred to as M2) and a second resistor R2; and the pull-down unit II includes a first metal oxide semiconductor field effect transistor M1 (hereinafter referred to as M1), a first resistor R1 and a third resistor R3.
[0035] Furthermore, the drain D of the second metal oxide semiconductor field effect transistor M2 is connected to the power supply terminal Vdd, and the second resistor R2 is connected between the gate G and the source S; the gate G of the second metal oxide semiconductor field effect transistor M2 is connected to the drain D of the first metal oxide semiconductor field effect transistor M1 as the output terminal Vout of the inverter circuit; the gate G of the first metal oxide semiconductor field effect transistor M1 is connected to the input terminal Vin through the first resistor R1, and is connected to the source S through the third resistor R3 and is grounded.
[0036] Furthermore, the threshold voltage Vgs_th of the metal oxide semiconductor field effect transistor M2 in the pull-up unit I is a negative value, the drain D of M2 is connected to Vdd, the second resistor R2 is connected between the gate G and the source S, and the gate G of the metal oxide semiconductor field effect transistor M2 is connected to the drain D of the metal oxide semiconductor field effect transistor M1 as the output Vout of the inverter.
[0037] In this example, the second metal oxide semiconductor field effect transistor M2 is a PHEMT D-Mode device, and the threshold voltage of the second metal oxide semiconductor field effect transistor M2 is generally a negative value Vgs_th<0V.
[0038] Furthermore, the negative value characteristic of the threshold voltage Vgsth of the PHEMTD-mode device is innovatively utilized between the metal oxide semiconductor field effect transistor M2 and the second resistor R2, and a pull-up network for suppressing the Ids current of M2 is formed in cooperation with the second resistor R2.
[0039] The Ids current here is the current between the drain D and the source S generated by the second MOSFET M2 .
[0040] The suppression pull-up network formed here is formed by connecting a second resistor R2 between the source and the gate of the second metal oxide semiconductor field effect transistor (M2) to form a suppression pull-up network. This structure can limit the drain-source current Ids of the second metal oxide semiconductor field effect transistor M2, thereby achieving the purpose of reducing the inverter current.
[0041] Specifically, when the second resistor R2 is connected in series to the source of the metal oxide semiconductor field effect transistor M2, due to the resistor voltage division, the gate voltage Vg of the metal oxide semiconductor field effect transistor M2 decreases as the Ids current of M2 and M1 increases, thereby suppressing the conduction of M2 Ids, thereby suppressing the circuit of the utility model from reducing the current in the high level input (low level output) mode and reducing power consumption.
[0042] As a further preference, the metal oxide semiconductor field effect transistor M2 (i.e., the PHEMT D-Mode device) in this example preferably uses the smallest device allowed in the PHEMT process; at the same time, the second resistor R2 preferably uses any resistor in the range of 0 to 5kOhm allowed in the PHEMT process, thereby enabling the formed pull-up unit chip to occupy a small area and have low cost.
[0043] The metal oxide semiconductor field effect transistor M1 in the pull-down unit II in the inverter circuit given in this example is a PHEMT E-Mode device, and its threshold voltage Vgsth is a positive value. Based on such a metal oxide semiconductor field effect transistor M1, when the gate-source voltage Vg of the metal oxide semiconductor field effect transistor M1 is less than the threshold voltage Vgsth, its input voltage Vin is a low level; when the gate-source voltage Vg of the metal oxide semiconductor field effect transistor M1 is greater than the threshold voltage Vgsth, its input voltage Vin is a high level.
[0044] Furthermore, the metal oxide semiconductor field effect transistor M1 in the pull-down unit II cooperates with the first resistor R1 and the third resistor R3; wherein the gate G and source S of the metal oxide semiconductor field effect transistor M1 are connected to both ends of the third resistor R3, and the input Vin is connected to the gate G of the metal oxide semiconductor field effect transistor M1 and both ends of the first resistor R1. In this way, the first resistor R1 and the third resistor R3 of the first metal oxide semiconductor field effect transistor M1 cooperate to divide the input voltage Vin, so that the gate voltage Vg of the first metal oxide semiconductor field effect transistor M1 can be reduced, thereby playing a role in improving the input low level of the inverter.
[0045] In this way, the first resistor R1 and the third resistor R3 divide the input voltage Vin, thereby effectively improving the input low level range of the inverter circuit formed, thereby enhancing the anti-noise and interference capabilities of the inverter circuit formed.
[0046] Example 2
[0047] See also Figure 3 , which is a schematic diagram of an inverter circuit for improving input low level based on PHEMT process given in this example.
[0048] The inverter circuit for improving the input low level based on the PHEMT process given in this example also includes two parts in structure: a pull-up unit I and a pull-down unit II.
[0049] The pull-up unit I has the same structure as the pull-up unit I in the solution of embodiment 1, including a second metal oxide semiconductor field effect transistor M2 and a second resistor R2;
[0050] Compared with the pull-down unit II in the embodiment 1, the pull-down unit II uses a triode (BJT or HBT) to replace the first metal oxide semiconductor field effect transistor M1, and also includes a first resistor R1 and a third resistor R3.
[0051] Furthermore, the drain D of the second metal oxide semiconductor field effect transistor M2 is connected to the power supply terminal Vdd, and the second resistor R2 is connected between the gate G and the source S; the gate G of the second metal oxide semiconductor field effect transistor M2 is connected to the collector C of the transistor Q1 as the output terminal Vout of the inverter circuit;
[0052] The base of the transistor Q1 is connected to the input terminal Vin through the first resistor R1 , and is connected to the emitter E of the transistor Q1 through the third resistor R3 and is grounded.
[0053] The construction mechanism of the pull-up unit 1 in this example is the same as that in Embodiment 1, and will not be described in detail here.
[0054] The transistor Q1 in the pull-down unit II in the inverter circuit given in this example is specifically an NPN transistor.
[0055] In the inverter circuit thus formed, the input low level range can also be improved by the cooperation of the first resistor R1 and the third resistor R3. That is, the first resistor R1 and the third resistor R3 cooperate to divide the input voltage Vin, thereby reducing the base voltage of the NPN transistor Q1, making it more difficult for the base and emitter voltage Vbe of the transistor Q1 to reach the threshold voltage (generally 0.7V-1.3V) of the NPN transistor Q1, thereby improving the low level range of the input voltage.
[0056] As a further priority, the transistors used in this example preferably use the smallest unit allowed by the process, thereby minimizing the chip area occupied by the formed pull-down unit II.
[0057] Example 3
[0058] See also Figure 4 , which is a schematic diagram of an inverter circuit for improving input low level based on PHEMT process given in this example.
[0059] The inverter circuit for improving the input low level based on the PHEMT process given in this example also includes two parts in structure: a pull-up unit I and a pull-down unit II.
[0060] The pull-up unit I includes a second metal oxide semiconductor field effect transistor M2 and a second resistor R2; and the pull-down unit II includes a first metal oxide semiconductor field effect transistor M1, a first resistor R1, and N diodes VDn.
[0061] Furthermore, the drain D of the second metal oxide semiconductor field effect transistor M2 is connected to the power supply terminal Vdd, and the second resistor R2 is connected between the gate G and the source S; the gate G of the second metal oxide semiconductor field effect transistor M2 is connected to the drain D of the first metal oxide semiconductor field effect transistor M1 as the output terminal Vout of the inverter circuit;
[0062] The gate G of the first metal oxide semiconductor field effect transistor M1 is connected to the first resistor R1 through N diodes VDn, and the N diodes VDn are connected in series in sequence. The cathode of the N diodes VDn connected in series is connected to the gate G of the first metal oxide semiconductor field effect transistor M1, and the anode is connected to one end of the first resistor R1. The other end of the first resistor R1 is connected to the input terminal Vin, and the source S of the first metal oxide semiconductor field effect transistor M1 is directly grounded.
[0063] The construction mechanism of the pull-up unit 1 in this example is the same as that in Embodiment 1, and will not be described in detail here.
[0064] The metal oxide semiconductor field effect transistor M1 in the pull-down unit II in the inverter circuit given in this example is a PHEMT E-Mode device, and its threshold voltage Vgsth is a positive value. Thus, when the gate-source voltage Vg of the metal oxide semiconductor field effect transistor M1 is less than the threshold voltage Vgsth, the input voltage Vin is a low level; when the gate-source voltage Vg of the metal oxide semiconductor field effect transistor M1 is greater than the threshold voltage Vgsth, the input voltage Vin is a high level.
[0065] Furthermore, the metal oxide semiconductor field effect transistor M1 in the pull-down unit II cooperates with the first resistor R1 and the N series-connected diodes VDn. The first resistor R1 is connected to the input Vin as a gate resistor, and N diodes VDn are connected in series between the gate G of the metal oxide semiconductor field effect transistor M1 and the first resistor R1. In this way, each time the input voltage Vin passes through a diode VD, the threshold voltage of a diode will be reduced, thereby reducing the gate voltage Vg of the metal oxide semiconductor field effect transistor M1. The gate voltage at this time is:
[0066] Vg=Vin-N*Vthd;
[0067] Thus, before the gate voltage Vg of M1 is greater than or equal to Vthm, the input voltage Vin can be used as a low level, where Vthd is the diode threshold voltage, and Vthm is the threshold voltage of the metal oxide semiconductor field effect transistor.
[0068] The inverter circuit formed in this way can also effectively increase the low level range of the input level.
[0069] The above shows and describes the basic principle, main features and advantages of the utility model. Those skilled in the art should understand that the utility model is not limited by the above embodiments. The above embodiments and descriptions are only for explaining the principle of the utility model. Without departing from the spirit and scope of the utility model, the utility model may have various changes and improvements, which fall within the scope of the utility model to be protected. The scope of protection of the utility model is defined by the attached claims and their equivalents.
Claims
1. An inverter circuit for improving input low level based on PHEMT process, characterized in that: The invention comprises a pull-up unit and a pull-down unit, wherein the pull-up unit comprises a second metal oxide semiconductor field effect transistor (M2) and a second resistor (R2); the pull-down unit comprises a first metal oxide semiconductor field effect transistor (M1), a first resistor (R1) and a third resistor (R3); The drain (D) of the second metal oxide semiconductor field effect transistor (M2) is connected to the power supply terminal (Vdd), a second resistor (R2) is connected between the gate (G) and the source (S), and the gate (G) of the second metal oxide semiconductor field effect transistor (M2) is connected to the drain (D) of the first metal oxide semiconductor field effect transistor (M1) as an output terminal (Vout) of the inverter circuit; The gate (G) of the first metal oxide semiconductor field effect transistor (M1) is connected to the input terminal (Vin) through the first resistor (R1), connected to the source (S) through the third resistor (R3) and grounded.
2. The inverter circuit for improving input low level based on PHEMT process according to claim 1, characterized in that: The second metal oxide semiconductor field effect transistor (M2) is a PHEMT D-Mode device, and the threshold voltage is a negative value; the second metal oxide semiconductor field effect transistor (M2) cooperates with the second resistor (R2) to form a pull-up network for suppressing the Ids current of the second metal oxide semiconductor field effect transistor (M2).
3. The inverter circuit for improving input low level based on PHEMT process according to claim 1, characterized in that: The first metal oxide semiconductor field effect transistor (M1) is a PHEMT E-Mode device.
4. An inverter circuit for improving input low level based on PHEMT process, characterized in that: It comprises a pull-up unit and a pull-down unit, wherein the pull-up unit comprises a second metal oxide semiconductor field effect transistor (M2) and a second resistor (R2); the pull-down unit comprises a triode and a first resistor (R1) and a third resistor (R3); The drain (D) of the second metal oxide semiconductor field effect transistor (M2) is connected to the power supply terminal (Vdd), a second resistor (R2) is connected between the gate (G) and the source (S), and the gate (G) of the second metal oxide semiconductor field effect transistor (M2) is connected to the collector (C) of the transistor as the output terminal (Vout) of the inverter circuit; The base of the transistor is connected to the input terminal (Vin) through a first resistor (R1), and is connected to the emitter (E) of the transistor through a third resistor (R3) and is grounded.
5. An inverter circuit for improving input low level based on PHEMT process, characterized in that: The invention comprises a pull-up unit and a pull-down unit, wherein the pull-up unit comprises a second metal oxide semiconductor field effect transistor (M2) and a second resistor (R2); the pull-down unit comprises a first metal oxide semiconductor field effect transistor (M1) and at least one diode (VD); The drain (D) of the second metal oxide semiconductor field effect transistor (M2) is connected to the power supply terminal (Vdd), a second resistor (R2) is connected between the gate (G) and the source (S), and the gate (G) of the second metal oxide semiconductor field effect transistor (M2) is connected to the drain (D) of the first metal oxide semiconductor field effect transistor (M1) as an output terminal (Vout) of the inverter circuit; The gate (G) of the first metal oxide semiconductor field effect transistor (M1) is connected to the input terminal (Vin) through at least one diode (VD), and the source (S) is connected to the ground.
6. The inverter circuit for improving input low level based on PHEMT process according to claim 5, characterized in that: Multiple diodes (VD) are connected in series.