Image sensor and electronic device

Abstract

An image sensor and an electronic device, the image sensor having a pixel region, a peripheral logic region located at the periphery of the pixel region, and a transition region located between the pixel region and the peripheral logic region, the transition region comprising an interception circuit structure, the interception circuit structure comprising an interception doping region and a potential providing structure, the potential providing structure is at least used for providing a preset potential for the interception doping region and attracting peripheral electrons. A transition region is arranged between a pixel region and a peripheral logic region, an interception circuit structure is arranged in the transition region, and a potential providing structure of the interception circuit structure can be used for providing a preset potential for an interception doping region and attracting peripheral electrons during image acquisition; therefore, the phenomenon that the number of electrons in a peripheral circuit is increased under the dark condition due to light emission, heat emission or stress difference is avoided, and the influence of peripheral electrons on a pixel array in a pixel area is avoided. As the interception circuit structure is arranged to intercept the peripheral electrons, the number of the virtual pixel units can be reduced, and even the virtual pixel units do not need to be arranged.

Description

Technical Field

[0001] The utility model relates to the technical field of image sensors, in particular to an image sensor and electronic equipment. Background Art

[0002] In the camera module, the image sensor is the core component, which determines the imaging quality of the camera and the structure and specifications of other components, and accounts for about 52% of the cost of the camera module. The image sensor is a semiconductor device that can convert optical images into electrical signals. Image sensors can be roughly divided into charge coupled devices (CCD) and complementary metal oxide semiconductor image sensors (CMOS Image Sensor, CIS). Among them, the CCD image sensor is integrated on the single crystal silicon material, and the pixel signal moves row by row and column by column and is amplified at the edge exit position. The advantages of the CCD image sensor are high image sensitivity and low noise, but the integration of the CCD image sensor with other devices is difficult, and the power consumption of the CCD image sensor is high. Among them, the CMOS image sensor is integrated on the metal oxide semiconductor material, and each pixel point is equipped with a signal amplifier, and the pixel signal can be directly scanned and exported. In contrast, the CMOS image sensor has the advantages of simple process, easy integration with other devices, small size, light weight, low power consumption, and low cost, and gradually replaces the position of CCD. At present, CMOS image sensors are widely used in digital cameras, camera phones, digital video cameras, medical imaging devices (such as gastroscopes), automotive imaging devices and other fields.

[0003] Image sensors can be divided into front-illuminated and back-illuminated (BSI) image sensors according to the different paths of incident light entering the photodiode. Front-illuminated refers to an image sensor in which the incident light enters the photodiode from the side close to the circuit connection layer, while back-illuminated refers to an image sensor in which the incident light enters the photodiode from the side away from the circuit connection layer. In order to increase the area of ​​the photodiode in the image sensor and reduce the loss of incident light in the dielectric layer, we can use the back-illuminated image sensor process, that is, the incident light enters the photodiode from the back of the silicon wafer, thereby reducing the loss of incident light in the dielectric layer and improving the sensitivity of the pixel unit.

[0004] like Figure 1As shown, in the prior art, whether it is a front-illuminated image sensor or a back-illuminated image sensor, both include a pixel area and a peripheral logic area located outside the pixel area. For an image sensor, the characteristics of the pixel area used for photosensitivity directly determine the performance of the final image sensor. In the design of a conventional image sensor, in order to ensure that the pixel array in the pixel area outputs images normally, a virtual pixel area is usually designed in the outer circle of the pixel area. There are some virtual pixel units (dummy pixels) in the virtual pixel area. For example, based on the area occupied and the corresponding width, the influence of the increase in the number of electrons in the peripheral circuit in the peripheral logic area due to light emission, heat generation or stress difference in the absence of light can be eliminated, and the image of the pixel array is prevented from being shading when there is no light, so as to affect the final imaging quality. The virtual pixel unit can also be directly used as a sacrificial pixel, or can be used as a clamping circuit, etc. However, this usually requires many circles of virtual pixel units, which makes the utilization rate of the image sensor low, and the chip area increases, and the cost increases. Utility Model Content

[0005] In order to overcome the shortcomings and deficiencies in the prior art, the purpose of the present invention is to provide an image sensor and an electronic device to solve the problem in the prior art that there are many virtual pixel units, resulting in low utilization rate of the image sensor.

[0006] The purpose of the utility model is achieved through the following technical solutions:

[0007] The utility model provides an image sensor, the image sensor comprising a pixel area, a peripheral logic area located outside the pixel area, and a transition area located between the pixel area and the peripheral logic area, wherein:

[0008] The transition region includes an interception circuit structure, which includes an interception doping region and a potential providing structure, wherein the potential providing structure is at least used to provide a preset potential to the interception doping region and attract peripheral electrons.

[0009] In one embodiment, the potential providing structure includes a reference potential providing transistor, an output end of the reference potential providing transistor is connected to the intercepting doping region, and is used to provide a preset potential to the intercepting doping region.

[0010] In one embodiment, the potential providing structure also includes an enable transistor, the input end of the enable transistor is connected to the output end of the reference potential providing transistor, the output end of the enable transistor is connected to the interception doping region, and the reference potential providing transistor provides a preset potential to the interception doping region through the enable transistor.

[0011] In one embodiment, the pixel area includes a plurality of pixel units arranged in an array, each of the pixel units includes a floating diffusion area and a reset module, the intercepting doping area corresponds to the floating diffusion area, and the potential providing structure corresponds to the reset module.

[0012] In one embodiment, the interception circuit structure corresponds to the pixel unit, and the interception circuit structure further includes at least one of a photoelectric conversion unit, a transfer transistor, a source follower transistor, and a pixel selection transistor.

[0013] In one embodiment, the gate of each transistor in the interception circuit structure, the drain of the reset transistor in the potential providing structure, and the drain of the source follower transistor are all coupled to the power supply voltage, and the source of the pixel selection transistor is floating so that each transistor in the interception circuit structure is in the on state.

[0014] In one embodiment, the interception circuit structure is multiple and distributed in a ring shape in the transition area, and the multiple interception circuit structures and the multiple pixel units in the pixel area are arranged in an array.

[0015] In one embodiment, the transition zone further includes a virtual pixel unit, and the virtual pixel units are multiple and distributed in a ring shape in the transition zone, and the multiple virtual pixel units, the multiple interception circuit structures and the multiple pixel units are arranged in an array.

[0016] In one embodiment, the transition zone further includes a virtual pixel unit, and the virtual pixel units are multiple and distributed in a straight line in the transition zone, and the multiple virtual pixel units, the multiple interception circuit structures and the multiple pixel units are arranged in an array.

[0017] In one embodiment, the interception circuit structure surrounds a side of the transition region close to the peripheral logic region.

[0018] In one embodiment, the dummy pixel unit surrounds a side of the transition region close to the pixel region.

[0019] In one embodiment, the linear virtual pixel unit is located on a side of the transition region close to the pixel region.

[0020] In one embodiment, the interception circuit structure is multiple and is linearly distributed in a preset side region of the transition region, and the interception circuit structure is close to a side of the peripheral logic region where electrons are generated.

[0021] In one embodiment, the transition region has a plurality of rows / columns of the interception circuit structures, and the interception circuit structures in two adjacent rows / columns are staggered.

[0022] In one embodiment, the transition region further includes a virtual pixel unit, and a plurality of the virtual pixel units and a plurality of the interception circuit structures are distributed in the transition region in a ring shape.

[0023] The present application also provides an electronic device, which includes the image sensor as described above.

[0024] The beneficial effects of the utility model are as follows: by setting a transition zone between the pixel area and the peripheral logic area, an interception circuit structure is provided in the transition zone, and the potential providing structure of the interception circuit structure can be used to provide a preset potential to the interception doping area and attract peripheral electrons, thereby avoiding an increase in the number of electrons in the peripheral circuit in the absence of light due to light emission, heat generation or stress difference, so as to avoid the influence of peripheral electrons on the pixel array in the pixel area; since the interception circuit structure is set to intercept peripheral electrons based on a preset potential to absorb electrons, the width of the interception circuit structure can be set to be relatively narrow, and the effect of intercepting peripheral electrons is much better than that of virtual pixel units. Therefore, the number of virtual pixel units can be reduced, and there is no need to set virtual pixel units that block peripheral electron interference, thereby reducing the chip area and reducing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a schematic diagram of the planar structure of an image sensor in the prior art;

[0026] Figure 2 This is the basic circuit diagram of the image sensor;

[0027] Figure 3 It is a basic connection diagram of transistors in the pixel area of ​​an image sensor;

[0028] Figure 4 This is one of the schematic diagrams of the planar structure of the image sensor in the first embodiment of the present utility model;

[0029] Figure 5 This is the second schematic diagram of the planar structure of the image sensor in the first embodiment of the utility model;

[0030] Figure 6 This is a connection diagram of transistors in the interception circuit structure of the first embodiment of the utility model;

[0031] Figure 7 This is a schematic diagram of an electrical signal of a transistor in an interception circuit structure of a first embodiment of the utility model;

[0032] Figure 8 It is a schematic diagram of the planar structure of the image sensor in the second embodiment of the utility model;

[0033] Fig. 9It is a schematic diagram of the planar structure of the image sensor in the third embodiment of the present utility model;

[0034] Fig.10 It is a schematic diagram of the planar structure of the image sensor in the fourth embodiment of the present utility model. DETAILED DESCRIPTION

[0035] In order to further explain the technical means and effects adopted by the present invention to achieve the predetermined purpose of the present invention, the specific implementation methods, structures, features and effects of the image sensor and electronic device proposed by the present invention are described in detail below in conjunction with the accompanying drawings and preferred embodiments:

[0036] Figure 2 This is the basic circuit diagram of the image sensor. Figure 2 As shown, the image sensor 100 includes a read circuit 104 and a control circuit 108 connected to a pixel array 102, a functional logic circuit 106 connected to the read circuit 104, and performs logic control on the reading of the pixel circuit; the read circuit 104 and the control circuit 108 are connected to a state register 112 to implement the reading control of the pixel array 102. The pixel array 101 includes a plurality of pixel units in rows (R1, R2, R3 ... Ry) and columns (C1, C2, C3 ... Cx), and the pixel signals output by the pixel array 102 are output to the read circuit 104 via column lines.

[0037] In one embodiment, after each pixel unit acquires image data, the image data is read out using the readout circuit 104 in the readout mode specified by the status register 112, and then transmitted to the functional logic circuit 106. In a specific application, the readout circuit 104 may include an analog-to-digital conversion (ADC) circuit, an amplification circuit, and others. In some application embodiments, the status register 112 may include a programmed selection system to determine whether the readout system is read out through a rolling exposure mode (rolling shutter) or a global exposure mode (global shutter). The functional logic circuit 106 may only store image data or image data applied or processed with image effects. In one application example, the readout circuit 104 may read out along the readout column lines (such as Figure 2 ) to read out image data one row at a time, or various other methods may be used to read out image data. The operation of the control circuit 108 may be determined by the current setting of the status register 112. For example, the control circuit 108 generates a shutter signal for controlling image acquisition. In some application examples, the shutter signal may be a global exposure signal so that all pixels of the pixel array 102 simultaneously acquire their image data through a single acquisition window. In some other application examples, the shutter signal may be a rolling exposure signal, and each pixel row is continuously read through the acquisition window.

[0038] Figure 3 This is a connection diagram of a transistor in an image sensor. Figure 3 As shown, each sensor pixel circuit 200 includes a light sensing element 210 (e.g., a photodiode, PD) and a pixel support circuit 211. The photodiode 210 may be a buried photodiode used in current image sensors. In one embodiment, the pixel support circuit 211 includes a reset transistor (RST) 220, a source follower transistor (SF) 225, and a pixel select transistor (SEL) 230, connected to a transfer transistor (TX) 215 and the photodiode 210 as shown in the figure. In another embodiment, not shown, the pixel support circuit 211 includes a reset transistor 220, a gain control transistor (DCG) 240, a source follower transistor 225, a pixel select transistor 230 disposed on a circuit chip, and connected to the photodiode 210 in another chip based on the transfer transistor 215. During operation, the light sensing element 210 generates photocharges in response to incident light during exposure. The transfer transistor 215 is connected to a transfer signal that controls the transfer transistor 215 to transfer the charge accumulated in the photodiode 210 to the floating diffusion region (FD) 217. In one embodiment, the transfer transistor 215 can be a MOSFET (metal oxide semiconductor field effect transistor). The reset transistor 220 is connected between VDD and the floating diffusion region 217, and responds to the reset signal RST to reset the sensor pixel circuit 200 (for example, discharge or charge the floating diffusion region 217 and the photodiode 210 to the current voltage). The floating diffusion region 217 is connected to the gate of the source follower transistor 225. The source follower transistor 225 is connected between VDD and the pixel selection transistor 230 to respond to the potential of the floating diffusion FD region 217 and output it. The pixel selection transistor 230 connects the pixel circuit output from the source follower transistor 225 to the readout bit line PIXOUT in response to the pixel selection control signal.

[0039] [Example 1]

[0040] like Figures 4 to 6 As shown, an image sensor provided by the first embodiment of the utility model comprises a pixel region, a peripheral logic region located outside the pixel region, and a transition region located between the pixel region and the peripheral logic region, wherein:

[0041] The transition region includes an interception circuit structure 32 , which includes an interception doping region 321 and a potential providing structure, wherein the potential providing structure is at least used to provide a preset potential to the interception doping region 321 and attract peripheral electrons.

[0042] The present application sets a transition zone between the pixel area and the peripheral logic area, and an interception circuit structure 32 is provided in the transition zone. The potential providing structure of the interception circuit structure 32 can be used to provide a preset potential to the interception doping area 321 and attract peripheral electrons, thereby avoiding an increase in the number of electrons in the peripheral circuit in the absence of light due to light emission, heat generation or stress difference, so as to avoid the influence of peripheral electrons on the pixel array in the pixel area; since the interception circuit structure 32 is set to intercept peripheral electrons based on a preset potential to absorb electrons, the width of the interception circuit structure 32 can be set to be relatively narrow, and the effect of intercepting peripheral electrons is much better than that of the virtual pixel unit 33. Therefore, the number of virtual pixel units 33 can be reduced, and there is no need to set a virtual pixel unit 33 for blocking peripheral electron interference, thereby reducing the chip area and reducing costs.

[0043] In one example, the potential providing structure includes a reference potential providing transistor 322, the output end of which is electrically connected to the interception doping region 321 and is used to provide a preset potential to the interception doping region 321. In a further optional example, the reference potential providing transistor 322 may be a reset transistor (RST), which provides a preset potential to the interception doping region 321.

[0044] In one example, the potential providing structure further includes an enabling transistor 323, the input end of the enabling transistor 323 is connected to the output end of the reference potential providing transistor 322, the output end of the enabling transistor 323 is connected to the intercepting doping region 321, and the reference potential providing transistor 322 provides a preset potential to the intercepting doping region 321 through the enabling transistor 323, that is, the enabling transistor 323 is arranged between the reference potential providing transistor 322 and the intercepting doping region 321, and whether the reference potential providing transistor 322 provides the preset potential to the intercepting doping region 321 can be controlled by turning the enabling transistor 323 on and off. In a further optional example, the enabling transistor 323 can be a gain control transistor (DCG), and the reference potential providing transistor 322 provides a preset potential to the intercepting doping region 321 through the gain control transistor.

[0045] In one example, the intercepting doping region 321 can be a doping region, for example, an N-type doping region, so that a preset potential can be applied based on a potential providing structure to absorb peripheral electrons, such as a preset potential can be provided based on a reset transistor or based on a reset transistor and a gain control transistor. In a further optional example, the intercepting doping region 321 can be a floating diffusion region FD, so that a preset potential is applied based on a reference potential providing transistor 322 or a reference potential providing transistor 322 and an enabling transistor 323. The preset potential is based on actual design to absorb peripheral electrons, for example, it can be a 2.8V power supply voltage.

[0046] It should be noted that the reference potential providing transistor 322 here can be a reset transistor (RST), the enable transistor 323 can be a gain control transistor (DCG), and the interception doping region 321 can be a floating diffusion region FD, which means that in the device structure, the structure of the elements in the interception circuit structure 32 is similar to the structure of the above-mentioned transistors in the pixel unit in the pixel area, for example, the reset transistor (RST) and the gain control transistor (DCG) are NMOS transistors, and the floating diffusion region FD is an N-type doping region.

[0047] In one example, the pixel area includes a plurality of pixel units 31 arranged in an array, each pixel unit 31 includes a floating diffusion region and a reset module, the interception doping region 321 corresponds to the floating diffusion region (FD), and the potential providing structure corresponds to the reset module. The reset module can be a reset transistor (RST) and / or a gain control transistor (DCG), that is, the interception doping region 321 of the interception circuit structure 32 corresponds to the floating diffusion region (FD) of the pixel support circuit 211, and is manufactured through the same process. The potential providing structure corresponds to the reset transistor (RST) and / or the gain control transistor (DCG) of the pixel support circuit 211, and is manufactured through the same process, for example, the reference potential providing transistor 322 of the potential providing structure corresponds to the reset transistor (RST) of the pixel support circuit 211, and is manufactured through the same process; the enabling transistor 323 of the potential providing structure corresponds to the gain control transistor (DCG) of the pixel support circuit 211, and is manufactured through the same process. Here, “made by the same process” may mean that the prepared structures are the same. Furthermore, the same mask plate is used for preparation, and the corresponding process steps and parameters in the preparation process are the same.

[0048] Furthermore, the interception circuit structure 32 corresponds to the pixel unit 31, that is, the interception circuit structure 32 corresponds to the corresponding transistor in the pixel unit 31, and is manufactured by the same process, so that the interception circuit structure 32 in the transition area and the pixel unit 31 in the pixel area are manufactured at the same time, without the need to adopt an additional manufacturing process for manufacturing. In one example, the pixel unit 21 also includes a photoelectric conversion unit (PD), a transfer transistor (TX), and a source follower transistor (SF). Further, the pixel unit 31 may also include a pixel selection transistor (SEL). Correspondingly, the interception circuit structure 32 also includes at least one of a photoelectric conversion unit (PD), a transfer transistor (TX), a source follower transistor (SF), and a pixel selection transistor (SEL). In a specific example, the interception circuit structure 32 has the same structure as the pixel unit 31, that is, the transistors included in the two are the same, and the corresponding transistors and layout layouts are the same when prepared in the semiconductor substrate. Among them, the input end of the transmission transistor (TX) in the interception circuit structure 32 is connected to the interception doping area 321, and the output end of the transmission transistor (TX) is connected to the photoelectric conversion unit (PD); the control end of the source follower transistor (SF) is connected to the interception doping area 321, and the output end of the source follower transistor (SF) is connected to the input end of the pixel selection transistor (SEL), and the output end of the pixel selection transistor (SEL) can be suspended, that is, open circuit.

[0049] Of course, each pixel unit 31 also includes a photoelectric conversion unit (photodiode, PD), a transfer transistor (TX), a source follower transistor (SF) and a pixel selection transistor (SEL). The pixel support circuit of the pixel unit 31 can refer to Figure 3 . Among them, the photoelectric conversion unit (PD) in the interception circuit structure 32 corresponds to the photoelectric conversion unit (PD) in the pixel unit 31, and is manufactured through the same process; the transmission transistor (TX) in the interception circuit structure 32 corresponds to the transmission transistor (TX) in the pixel unit 31, and is manufactured through the same process; the source follower transistor (SF) in the interception circuit structure 32 corresponds to the source follower transistor (SF) in the pixel unit 31, and is manufactured through the same process; the pixel selection transistor (SEL) in the interception circuit structure 32 corresponds to the pixel selection transistor (SEL) in the pixel unit 31, and is manufactured through the same process.

[0050] In one example, the gate of each transistor in the interception circuit structure 32 and the drain of the reset transistor in the potential providing structure are connected to the power supply voltage (VDD), so that each transistor in the interception circuit structure 32 can be in the on state at least when the image sensor is capturing an image, such as in at least one stage of global reset, exposure and readout. For example, the gates of the reset transistor (RST), the gain control transistor (DCG), the transmission transistor (TX), and the pixel selection transistor (SEL) in the interception circuit structure 32 are all connected to the power supply voltage, and the drain of the reset transistor (RST) and the drain of the source follower transistor (SF) are all connected to the power supply voltage (VDD), wherein the gate of the source follower transistor (SF) is connected to the power supply voltage (VDD) through the reset transistor (RST) and the gain control transistor (DCG), and the source of the pixel selection transistor (SEL) is suspended, so that each transistor in the interception circuit structure 32 is in the on state, and the entire interception circuit structure 32 is the power supply voltage (VDD), that is, each node in the corresponding circuit has a potential equivalent to the power supply voltage, and at least the interception doping region 321 has a high potential to attract and intercept peripheral electrons. By connecting the gates of each transistor in the interception circuit structure 32 to the power supply voltage, there is no need to set up an additional control circuit to control the switching state of each transistor in the interception circuit structure 32, thereby simplifying the circuit. Of course, in other embodiments, a control circuit and a control driving signal may be additionally provided to control the switch state of each transistor in the interception circuit structure 32. Of course, a gain control transistor may not be provided.

[0051] In one example, the transition zone is arranged in a ring shape at the periphery of the pixel zone, and further, the peripheral logic zone is arranged in a ring shape at the periphery of the transition zone, wherein the peripheral logic zone may include analog or digital related circuits corresponding to the pixel array, and may be designed based on the requirements of the existing image sensor. Specifically, the shape of the transition zone may be a ring structure formed by a complete circle of areas, or a ring structure formed by discontinuous sub-areas, that is, other structures may be interspersed between adjacent sub-areas of the transition zone, and of course, the transition zone may also be located only in a part of the periphery of the pixel zone, for example, only on the upper side of the pixel zone.

[0052] In one example, if Figure 5 As shown, the transition zone is arranged in a ring shape at the periphery of the pixel zone, and the interception circuit structure 32 is multiple and distributed in a ring shape in the transition zone. The multiple interception circuit structures 32 and the multiple pixel units 31 of the pixel zone are arranged in an array together, so that the peripheral electrons around the edge of the pixel zone can be intercepted. Among them, the pixel zone is a rectangular structure, and a pixel array is arranged in the pixel zone, and the pixel array is composed of multiple pixel units 31. The peripheral logic zone is a rectangular frame structure and surrounds the periphery of the pixel zone. The transition zone is a rectangular frame structure and is arranged between the pixel zone and the peripheral logic zone.

[0053] [Example 2]

[0054] Figure 8 FIG. 1 is a schematic diagram of the planar structure of the image sensor in the second embodiment of the present utility model. Figure 8 As shown, the image sensor provided by the second embodiment of the present invention is the same as that provided by the first embodiment ( Figures 4 to 7 ) are substantially the same, except that, in this embodiment:

[0055] The transition zone also includes a virtual pixel unit 33, which is multiple and distributed in a ring shape in the transition zone. The multiple virtual pixel units 33, the multiple interception circuit structures 32 and the multiple pixel units 31 are arranged in an array. In one example, the interception circuit structure 32 surrounds the side of the transition zone close to the peripheral logic area, that is, the interception circuit structure 32 is set in the outermost circle of the transition zone, and further, the virtual pixel unit 33 surrounds the side of the transition zone close to the pixel area. By setting the interception circuit structure 32 to intercept peripheral electrons, there is no need to set a large number of virtual pixel units 33 to eliminate peripheral electrons. Therefore, the number of virtual pixel units 33 can be greatly reduced, and the utilization rate of the image sensor can be improved.

[0056] Among them, the virtual pixel unit can be directly used as a sacrificial pixel, or can be used as a clamping circuit. Of course, it can also be used to further improve the influence of the electronics of the peripheral circuit on the pixel area. The virtual pixel unit can have the same transistor structure as the pixel unit in the pixel area in the semiconductor substrate. Of course, it can also be a circuit structure that is additionally arranged according to different needs. In addition, in other embodiments, the arrangement shape of the virtual pixel unit in the transition zone is not limited to the above-mentioned annular arrangement, and can be arranged at the required position outside the pixel area according to actual needs. Thus, the transition zone composed of the virtual pixel unit and the interception circuit structure is reduced in area relative to the Dummy zone with the same effect in the prior art.

[0057] It should be understood by those skilled in the art that the rest of the structure and working principle of this embodiment are the same as those of the first embodiment and will not be described in detail here.

[0058] [Example 3]

[0059] Fig. 9 FIG. 1 is a schematic diagram of the planar structure of the image sensor in the third embodiment of the present utility model. Fig. 9 As shown, the image sensor provided in the third embodiment of the present invention is the same as that in the first embodiment ( Figures 4 to 7 ) are substantially the same, except that, in this embodiment:

[0060] The interception circuit structures 32 are multiple and linearly distributed in the preset side area of ​​the transition area, and the interception circuit structures 32 are close to the side where the peripheral logic area generates electrons. In practice, since more electrons are not generated all around the peripheral logic area, it is possible that only one side of the peripheral logic area or part of the circuit area will generate more electrons. Therefore, the interception circuit structure 32 can be set on the side of the transition area close to the side where the peripheral logic area generates electrons, thereby reducing the number of interception circuit structures 32.

[0061] In one example, the transition zone further includes a virtual pixel unit 33, and a plurality of virtual pixel units 33 and a plurality of interception circuit structures 32 are distributed in a ring shape in the transition zone. For example, one side area of ​​the transition zone is provided with the interception circuit structure 32, and the other side areas are provided with virtual pixel units 33, so that the width of the transition zone can be further reduced to improve the utilization rate of the image sensor.

[0062] It should be understood by those skilled in the art that the rest of the structure and working principle of this embodiment are the same as those of the first embodiment and will not be described in detail here.

[0063] [Example 4]

[0064] Fig.10 FIG. 1 is a schematic diagram of the planar structure of the image sensor in the fourth embodiment of the present utility model. Fig.10 As shown, the image sensor provided by the fourth embodiment of the present invention is the same as that provided by the third embodiment ( Fig. 9 ) are substantially the same, except that, in this embodiment:

[0065] The transition region has multiple rows / columns of interception circuit structures 32, and the interception circuit structures 32 in two adjacent rows / columns are staggered. For example, two columns of interception circuit structures 32 are arranged in the preset side region of the interception circuit structure 32, and the two columns of interception circuit structures 32 are staggered, and the staggered distribution can increase the interception effect of the interception circuit structure 32 on peripheral electrons.

[0066] It should be understood by those skilled in the art that the rest of the structure and working principle of this embodiment are the same as those of the third embodiment, and will not be described in detail here.

[0067] The present application also provides a control method of an image sensor, which is used to control the above-mentioned image sensor. The control method includes:

[0068] The control potential providing structure provides a preset potential to the interception doping region 321 and attracts peripheral electrons. For example, the control reference potential providing transistor 322 (reset transistor (RST)) and the enable transistor 323 (gain control transistor (DCG)) provide a power supply voltage to the interception doping region 321, so that the entire interception circuit structure 32 is the power supply voltage (VDD) to attract and intercept peripheral electrons. The above control process can occur during the image acquisition process, such as in at least one of the global reset stage, the exposure stage, and the readout stage. Of course, the above control can also further occur in the idle stage.

[0069] In one example, when the image sensor is capturing an image, each transistor in the interception circuit structure 32 is in an on state at any time. For example, the gates of each transistor in the interception circuit structure 32 can be connected to the power supply voltage (VDD), so that each transistor in the interception circuit structure 32 is in an on state at any time. Of course, each transistor in the interception circuit structure 32 can also be controlled to be in an on state at any time by additionally setting a control voltage.

[0070] In another embodiment, when the image sensor is collecting images, each transistor in the interception circuit structure 32 can also be turned on in different time periods, for example, only in the exposure phase and the readout phase (where Figure 7 The operation of the pixel area in the corresponding readout phase) controls each transistor in the interception circuit structure 32 to be in the on state. Since the peripheral logic area needs a certain amount of time to accumulate more peripheral electrons, when more peripheral electrons are accumulated, each transistor in the interception circuit structure 32 is controlled to be in the on state to attract and intercept the peripheral electrons. Compared with the real-time on state, the on state in time periods can reduce power consumption.

[0071] The utility model also provides an electronic device, including an image sensor as described in any one of the above schemes. For the electronic device of the utility model, for example, it can be a vehicle-mounted device, which includes an image sensor. The specific structure of the image sensor refers to the above embodiment. Since the vehicle-mounted device includes the technical solution of the above embodiment, it at least has all the beneficial effects brought by the technical solution of the above embodiment, which will not be repeated here. Of course, the electronic device provided by the utility model can also be monitoring equipment, machine vision, drones, mobile phones, cameras, etc.

[0072] In this document, the directional words such as up, down, left, right, front, and back are defined by the positions of the structures in the drawings and the positions of the structures relative to each other, just for the sake of clarity and convenience in expressing the technical solution. It should be understood that the use of the directional words should not limit the scope of protection claimed in this application. It should also be understood that the terms "first" and "second" used in this document are only used to distinguish names and are not used to limit quantity and order.

[0073] The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with the profession can make some changes or modifications to the technical contents disclosed above without departing from the scope of the technical solution of the present invention, which are equivalent embodiments of equivalent changes. However, any simple modification, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the protection scope of the technical solution of the present invention.

Claims

1. An image sensor, characterized in that: The image sensor comprises a pixel region, a peripheral logic region located at the periphery of the pixel region, and a transition region located between the pixel region and the peripheral logic region, wherein: The transition region includes an interception circuit structure, which includes an interception doping region and a potential providing structure, wherein the potential providing structure is at least used to provide a preset potential to the interception doping region and attract peripheral electrons.

2. The image sensor according to claim 1, characterized in that The potential providing structure includes a reference potential providing transistor, the output end of which is connected to the intercepting doping region and is used to provide a preset potential to the intercepting doping region.

3. The image sensor according to claim 2, characterized in that The potential providing structure also includes an enable transistor, the input end of the enable transistor is connected to the output end of the reference potential providing transistor, the output end of the enable transistor is connected to the interception doping region, and the reference potential providing transistor provides a preset potential to the interception doping region through the enable transistor.

4. The image sensor according to claim 1, characterized in that The pixel area includes a plurality of pixel units arranged in an array, each of the pixel units includes a floating diffusion area and a reset module, the intercepting doping area corresponds to the floating diffusion area, and the potential providing structure corresponds to the reset module.

5. The image sensor according to claim 4, characterized in that: The interception circuit structure corresponds to the pixel unit, and the interception circuit structure also includes at least one of a photoelectric conversion unit, a transfer transistor, a source follower transistor, and a pixel selection transistor.

6. The image sensor according to claim 5, characterized in that The gates of each transistor in the interception circuit structure, the drain of the reset transistor in the potential providing structure, and the drain of the source follower transistor are all coupled to the power supply voltage, and the source of the pixel selection transistor is floatingly set so that each transistor in the interception circuit structure is in the on state.

7. The image sensor according to any one of claims 1 to 6, characterized in that: The interception circuit structures are multiple and distributed in a ring shape in the transition area. The multiple interception circuit structures and the multiple pixel units in the pixel area are arranged in an array.

8. The image sensor according to claim 7, characterized in that: The transition zone also includes virtual pixel units, which are multiple and distributed in a ring or straight line in the transition zone. The multiple virtual pixel units, the multiple interception circuit structures and the multiple pixel units are arranged in an array.

9. The image sensor according to claim 8, characterized in that: The interception circuit structure surrounds a side of the transition area close to the peripheral logic area, and / or the virtual pixel unit surrounds a side of the transition area close to the pixel area or is located at a side of the transition area close to the pixel area.

10. The image sensor according to any one of claims 1 to 6, characterized in that: The interception circuit structures are multiple and are distributed in a linear shape in a preset side area of ​​the transition area. The interception circuit structures are close to the side where electrons are generated in the peripheral logic area.

11. The image sensor according to claim 10, characterized in that: The transition area has a plurality of rows / columns of the interception circuit structures, and the interception circuit structures in two adjacent rows / columns are staggered.

12. The image sensor according to claim 11, characterized in that: The transition region further includes a virtual pixel unit, and a plurality of the virtual pixel units and a plurality of the interception circuit structures are distributed in the transition region in a ring shape.

13. An electronic device, characterized in that: The electronic device comprises the image sensor as claimed in any one of claims 1-12.

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