Signal accumulation circuit and electronic equipment

Abstract

The embodiment of the utility model discloses a signal accumulation circuit and electronic equipment, and the signal accumulation circuit comprises a capacitor and a signal latch circuit. A negative plate of the capacitor serves as a circuit input end to sequentially receive input signals, and a positive plate of the capacitor is connected with an input end of the signal latch circuit; the input end of the signal latch circuit is connected with the capacitor positive plate, and the output end of the signal latch circuit is used as a circuit output end to output accumulated signals; wherein the accumulation signal is an accumulation result of the input signals which are input for multiple times; according to the embodiment of the invention, accumulation processing of an unknown number of input signals is realized.

Description

Technical Field

[0001] The present disclosure relates to the technical field of signal processing, and in particular to a signal accumulation circuit and an electronic device. Background Art

[0002] An adder is a device that generates the sum of numbers. A device that takes the addend and the augend as input and the sum and the carry as output is a half adder. If the addend, the augend and the carry of the low-order bit are input, and the sum and the carry are output, it is a full adder. It is often used as a computer arithmetic logic unit to perform logical operations, shifts and instruction calls. In electronics, an adder is a digital circuit that can perform digital addition calculations. Currently, common analog signal addition circuits usually include several input terminals and one output terminal, and several analog voltage signals are respectively input to the corresponding input terminals, and then the sum of these analog voltages is obtained at the output terminal. This circuit structure is only applicable to the case where the number of signals to be added is determined; for the case where the number of signals to be added is uncertain, this circuit structure cannot handle it. Utility Model Content

[0003] According to one aspect of an embodiment of the present disclosure, there is provided a signal accumulation circuit, comprising: a capacitor and a signal latch circuit;

[0004] The negative plate of the capacitor serves as a circuit input terminal to sequentially receive input signals, and the positive plate of the capacitor is connected to the input terminal of the signal latch circuit;

[0005] The input end of the signal latch circuit is connected to the positive plate of the capacitor, and the output end serves as a circuit output end to output an accumulated signal; wherein the accumulated signal is an accumulated result of the input signals input multiple times.

[0006] Optionally, the signal latch circuit includes a voltage buffer and a signal latch control switch connected in parallel;

[0007] The signal latch control switch is turned on or off according to the control of the external latch signal. In response to the signal latch control switch being turned off, the input signal is transmitted from the negative plate of the capacitor to the positive plate of the capacitor; in response to the signal latch control switch being closed, the accumulated signal of the positive plate of the capacitor is latched through the voltage buffer.

[0008] Optionally, it further comprises: a first reset switch and a second reset switch;

[0009] The positive plate of the capacitor is grounded through the first reset switch, the first reset switch is controlled to be closed or opened through a first reset signal, and the positive plate of the capacitor is reset in response to the first reset switch being closed;

[0010] The negative plate of the capacitor is grounded through the second reset switch, the second reset switch is controlled to be closed or opened by a second reset signal, and the negative plate of the capacitor is reset in response to the second reset switch being closed.

[0011] Optionally, it also includes: a signal carry circuit;

[0012] The input end of the signal carry circuit is connected to the output end of the signal latch circuit, and in response to the accumulation signal reaching a preset condition, the carry result is output through the output end of the signal carry circuit.

[0013] Optionally, the signal carry circuit comprises: a comparator; the carry result is a carry signal;

[0014] The positive input terminal of the comparator is connected to the output terminal of the signal latch circuit, and the negative input terminal receives a preset threshold signal. In response to the accumulated signal being greater than the preset threshold signal, the carry signal is output through the output terminal of the comparator.

[0015] Optionally, the circuit further comprises: a third reset switch and a fourth reset switch;

[0016] The positive plate of the capacitor is grounded through the third reset switch, the closing or opening of the third reset switch is controlled by the carry signal, and the positive plate of the capacitor is reset in response to the carry signal being at a high level;

[0017] The negative plate of the capacitor is grounded through the fourth reset switch, the closing or opening of the second reset switch is controlled by the carry signal, and in response to the carry signal being at a high level, the negative plate of the capacitor is reset.

[0018] Optionally, the source of the third reset switch is grounded, the drain is connected to the positive plate of the capacitor, and the gate is connected to the output end of the comparator;

[0019] The source of the fourth reset switch is grounded, the drain is connected to the negative plate of the capacitor, and the gate is connected to the output end of the comparator.

[0020] Optionally, the signal carry circuit further comprises: a multi-bit carry signal counter; the carry result is a multi-bit carry signal;

[0021] The input end of the multi-bit carry signal counter is connected to the output end of the comparator, and is used to accumulate and count multiple carry signals output by the comparator to obtain the multi-bit carry signal. The output end of the multi-bit carry signal counter outputs the multi-bit carry signal.

[0022] According to another aspect of the embodiments of the present disclosure, there is provided an electronic device, comprising: a processor, and a memory communicatively connected to the processor, and further comprising the signal accumulation circuit as described in any one of the above embodiments;

[0023] The memory stores computer-executable instructions;

[0024] The processor executes computer-executable instructions stored in the memory to control the signal accumulation circuit.

[0025] Optionally, the electronic device is included in any one of the following: a pulse camera, a high-speed camera, an audio / video player, a navigation device, a fixed-position terminal, an entertainment unit, a smart phone, a communication device, a device in a motor vehicle, a camera, a sports or wearable camera, a detection device, a flight device, a medical device, a security device.

[0026] A signal accumulation circuit and an electronic device provided based on the above-mentioned embodiment of the present disclosure include: a capacitor and a signal latch circuit; the negative plate of the capacitor serves as a circuit input terminal to sequentially receive input signals, and the positive plate of the capacitor is connected to the input terminal of the signal latch circuit; the input terminal of the signal latch circuit is connected to the positive plate of the capacitor, and the output terminal serves as a circuit output terminal to output an accumulated signal; wherein the accumulated signal is the accumulated result of the input signals input multiple times; the signal latch circuit is used to control the external latch signal so that the negative plate of the capacitor receives the input signal and transmits it to the positive plate of the capacitor, and latches the accumulated signal of the positive plate of the capacitor; the signal accumulation circuit provided in this embodiment only provides one input terminal, and the input signals to be accumulated are received sequentially through the input terminal. Since all input signals are input into the circuit through one input terminal, there is no limit on the number of accumulated signals, thereby realizing the accumulation processing of unknown number of input signals.

[0027] The technical solution of the present disclosure is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings, which constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0029] The present disclosure may be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0030] Figure 1 is a circuit structure diagram of a signal accumulation circuit provided by an exemplary embodiment of the present disclosure;

[0031] Figure 2is a circuit structure diagram of a signal accumulation circuit provided by another exemplary embodiment of the present disclosure;

[0032] Figure 3 is a circuit structure diagram of a signal accumulation circuit provided by another exemplary embodiment of the present disclosure;

[0033] Figure 4 is a circuit structure diagram of a signal accumulation circuit provided by another exemplary embodiment of the present disclosure;

[0034] Figure 5 is a circuit structure diagram of a signal accumulation circuit provided by yet another exemplary embodiment of the present disclosure;

[0035] Figure 6 is a schematic diagram of a flow chart of a signal accumulation circuit performing signal accumulation in an optional embodiment of the present disclosure;

[0036] Figure 7 is a circuit structure diagram of a signal accumulation circuit provided by yet another exemplary embodiment of the present disclosure;

[0037] Figure 8 is a schematic diagram of a flow chart of a signal accumulation circuit performing signal accumulation in another optional embodiment of the present disclosure;

[0038] Fig. 9 A block diagram of an electronic device according to an embodiment of the present disclosure is illustrated. DETAILED DESCRIPTION

[0039] Below, the exemplary embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure, and it should be understood that the present disclosure is not limited to the exemplary embodiments described here.

[0040] It should be noted that the relative arrangement of components and steps, the numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.

[0041] Those skilled in the art can understand that the terms "first" and "second" in the embodiments of the present disclosure are only used to distinguish different steps, devices or modules, etc., and neither represent any specific technical meaning nor indicate the necessary logical order between them.

[0042] It should also be understood that in the embodiments of the present disclosure, “plurality” may refer to two or more than two, and “at least one” may refer to one, two, or more than two.

[0043] It should also be understood that any component, data or structure mentioned in the embodiments of the present disclosure can generally be understood as one or more, unless explicitly limited or otherwise indicated in the context.

[0044] In addition, the term "and / or" in this disclosure is only a description of the association relationship of associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this disclosure generally indicates that the previous and next associated objects are in an "or" relationship. The data referred to in this disclosure may include unstructured data such as text, images, and videos, and may also be structured data.

[0045] It should also be understood that the description of the various embodiments in the present disclosure focuses on the differences between the various embodiments, and the same or similar aspects thereof can be referenced to each other, and for the sake of brevity, they will not be described one by one.

[0046] At the same time, it should be understood that for the convenience of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0047] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present disclosure, its application, or uses.

[0048] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0049] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0050] In the process of implementing the present disclosure, the inventors found that the analog signal adder including several input terminals and one output terminal in the prior art is only applicable to the case where the number of signals to be added is determined, and when the number of signals to be added is uncertain, this adding circuit is no longer applicable. Therefore, in order to solve the signal addition problem when the number of signals to be added is uncertain, the inventors propose the following technical solution.

[0051] Figure 1 FIG. 1 is a schematic diagram of a circuit structure of a signal accumulation circuit provided by an exemplary embodiment of the present disclosure. Figure 1 As shown, the signal accumulation circuit provided in this embodiment includes: a capacitor 110 and a signal latch circuit 120;

[0052] The negative plate of the capacitor 110 serves as a circuit input terminal to sequentially receive input signals, and the positive plate of the capacitor 110 is connected to the input terminal of the signal latch circuit 120 .

[0053] A capacitor is made up of two conductors placed close to each other with a non-conductive insulating medium in between. When a voltage is applied between the two plates of a capacitor, the capacitor will store charge. The capacitance of a capacitor is numerically equal to the ratio of the charge on one conductive plate to the voltage between the two plates.

[0054] Optionally, the input signal may be any analog signal, for example, a voltage signal, a current signal, a numerical signal, etc. In an optional example, the input signal is a voltage signal output by a pixel unit in a pulse sensor.

[0055] The input terminal of the signal latch circuit 120 is connected to the positive plate of the capacitor, and the output terminal serves as the circuit output terminal to output the accumulated signal.

[0056] The accumulated signal is the accumulated result of the input signals inputted multiple times.

[0057] The signal latch circuit 120 is used to control the external latch signal so that the negative plate of the capacitor receives the input signal and transmits it to the positive plate of the capacitor, and latches the accumulated signal of the positive plate of the capacitor.

[0058] In this embodiment, the external latch signal can be determined according to the input frequency of the input signal. In the time between each two input signal receptions, the signal latch circuit is controlled by the external latch signal to latch the accumulated signal of the positive plate of the capacitor; when a new input signal is received, the latching is stopped, so that the new input signal is transmitted to the positive plate of the capacitor 110 through the negative plate of the capacitor 110, so that the new input signal is accumulated on the positive plate of the capacitor 110 based on the original accumulated signal (if the input signal has not been received before, it is 0 at this time), and a new accumulated signal (the sum of the original accumulated signal and the new input signal) is obtained on the positive plate of the capacitor 110, and the new accumulated signal is latched in the positive plate of the capacitor 110 through the control of the external latch signal, so that the accumulation calculation can be continued based on the latched new accumulated signal when the input signal is received next time.

[0059] The above-mentioned embodiment of the present disclosure provides a signal accumulation circuit and an electronic device, comprising: a capacitor and a signal latch circuit; the negative plate of the capacitor serves as a circuit input terminal to sequentially receive input signals, and the positive plate of the capacitor is connected to the input terminal of the signal latch circuit; the input terminal of the signal latch circuit is connected to the positive plate of the capacitor, and the output terminal serves as a circuit output terminal to output an accumulated signal; wherein the accumulated signal is the accumulated result of the input signals input multiple times; the signal latch circuit is used to control the external latch signal so that the negative plate of the capacitor receives the input signal and transmits it to the positive plate of the capacitor, and latches the accumulated signal of the positive plate of the capacitor; the signal accumulation circuit provided in this embodiment provides only one input terminal, and sequentially receives the input signals to be accumulated through the input terminal. Since all input signals are input into the circuit through one input terminal, there is no limit on the number of accumulated signals, thereby realizing the accumulation processing of unknown number of input signals.

[0060] Figure 2 FIG. 1 is a circuit structure diagram of a signal accumulation circuit provided by another exemplary embodiment of the present disclosure. Figure 2 As shown, the signal latch circuit 120 in the signal accumulation circuit provided in this embodiment includes a voltage buffer 121 and a signal latch control switch 122 connected in parallel.

[0061] The signal latch control switch 122 is turned on or off according to the control of the external latch signal. In response to the signal latch control switch 122 being turned off, the input signal is transmitted from the negative plate of the capacitor 110 to the positive plate of the capacitor 110; in response to the signal latch control switch 122 being closed, the accumulated signal of the positive plate of the capacitor 110 is latched through the voltage buffer 121.

[0062] like Figure 2As shown, when the signal latch control switch 122 is closed, the input and output ends of the voltage buffer 121 are short-circuited together. At this time, the signal Vc1 of the positive plate of the capacitor is latched, and no matter how the signal Vc2 of the negative plate of the capacitor changes, the signal Vc1 of the positive plate of the capacitor does not change; when the signal latch control switch 122 is disconnected, the signal Vc1 of the positive plate of the capacitor will change with the change of the signal Vc2 of the negative plate of the capacitor; for example, the signal Vc1 of the positive plate of the original capacitor is V1, and the input signal received by the signal Vc2 of the negative plate of the capacitor is V2. When the signal latch control switch 122 is disconnected, due to the conservation of capacitor charge, the signal Vc1 of the positive plate of the capacitor will rise from V1 to V1+V2, thereby realizing the accumulation of the input signal. The voltage buffer in this embodiment is a common circuit unit in analog circuits, and its basic characteristic is that the output signal is always equal to the input signal. The internal circuit structure of the voltage buffer can be of various designs and is existing technology, so it is not elaborated. Those skilled in the art should understand that all voltage buffers that can achieve the output signal always being equal to the input signal can be applied to the embodiments provided in the present disclosure.

[0063] Figure 3 FIG. 1 is a circuit structure diagram of a signal accumulation circuit provided by another exemplary embodiment of the present disclosure. Figure 3 As shown, the signal accumulation circuit provided in this embodiment further includes: a first reset switch 130 and a second reset switch 140 .

[0064] The positive plate of the capacitor 110 is grounded GND through the first reset switch 130 , and the first reset switch 130 is controlled to be closed or opened by the first reset signal. In response to the first reset switch 130 being closed, the positive plate of the capacitor 110 is reset.

[0065] In this embodiment, the positive plate of the capacitor 110 is connected to the ground terminal GND through the first reset switch 130. When the first reset switch 130 is closed (for example, the first reset switch is a field effect transistor, and the first reset switch is closed when the first reset signal is at a high level), the positive plate of the capacitor 110 is reset through the voltage of the ground terminal GND, so that the signal of the positive plate of the capacitor 110 is restored to 0, so that the signal can be accumulated at the positive plate of the capacitor 110 without being affected by other signals. Usually, the first reset signal only controls the closing of the first reset switch 130 before the signal accumulation circuit performs a signal accumulation, so as to achieve the initial reset of the positive plate of the capacitor 110.

[0066] The negative plate of the capacitor 110 is grounded GND through the second reset switch 140 , and the second reset switch 140 is controlled to be closed or opened by the second reset signal. In response to the second reset switch 140 being closed, the negative plate of the capacitor 110 is reset.

[0067] In this embodiment, the negative plate of the capacitor 110 and the ground terminal GND are connected by the second reset switch 140, and the second reset switch 140 is closed by the control of the second reset signal (for example, the second reset switch is a field effect transistor, and the second reset switch is closed when the second reset signal is at a high level), and the negative plate of the capacitor 110 is reset by the voltage of the ground terminal GND, so that the signal of the negative plate of the capacitor 110 is restored to 0, thereby resetting the signal receiving end. Optionally, the negative plate of the capacitor 110 can be reset before each input signal is received. By resetting the negative plate of the capacitor 110, the input signal received each time is not interfered by other signals, thereby improving the accuracy of the accumulated result.

[0068] Figure 4 FIG. 1 is a circuit structure diagram of a signal accumulation circuit provided by another exemplary embodiment of the present disclosure. Figure 4 As shown, the signal accumulation circuit provided in this embodiment also includes: a signal carry circuit 150.

[0069] The input end of the signal carry circuit 150 is connected to the output end of the signal latch circuit 120 , and in response to the accumulated signal reaching a preset condition, the carry result is output through the output end of the signal carry circuit 150 .

[0070] Since the capacitor has a certain capacity, if the accumulated signal is only relied on the positive plate of the capacitor 110, due to the limitation of the capacitor capacity, only a small number of signals can be accumulated and summed, which limits the application scope of the signal accumulation circuit provided in this embodiment. Therefore, the embodiment of the present disclosure proposes a signal carry circuit 150, so that when the accumulated signal of the positive plate of the capacitor 110 reaches a preset condition (for example, greater than a preset threshold), the signal carry circuit 150 accumulates the carry number (which can be one or more bits) to obtain a carry result, and outputs the carry result through the output end of the signal carry circuit 150. The carry increases the size of the signal that can be accumulated by the signal accumulation circuit, and expands the application scope of the signal accumulation circuit. In addition, after each carry digit is accumulated by the signal carry circuit 150, the positive plate and the negative plate of the capacitor 110 can be reset (since the previous accumulation result has been represented by the carry digit, the positive plate is cleared at this time to continue the calculation), and the input signals to be accumulated are continued to be received until all the input signals to be accumulated are input, or the accumulation result of the input signal reaches the upper capacity limit of the signal carry circuit 150 and the positive plate of the capacitor 110. At this time, the accumulation result of all input signals can be obtained by simultaneously outputting the carry result and the accumulation signal. The base of the carry digit in this embodiment can be set according to the actual application scenario, including but not limited to: binary, decimal, etc.

[0071] Figure 5FIG. 1 is a circuit structure diagram of a signal accumulation circuit provided by another exemplary embodiment of the present disclosure. Figure 5 As shown, the signal carry circuit 150 in the signal accumulation circuit provided in this embodiment includes: a comparator 151; and a carry result is a carry signal.

[0072] The positive input terminal of the comparator 151 is connected to the output terminal of the signal latch circuit 120 , and the negative input terminal receives a preset threshold signal Vth. In response to the accumulated signal being greater than the preset threshold signal Vth, a carry signal is output through the output terminal of the comparator 151 .

[0073] In this embodiment, the signal carry circuit 150 can be implemented by a comparator 151, and only a single-digit carry can be implemented at this time; the accumulated signal input at the positive input terminal is compared with the preset threshold signal Vth input at the negative input terminal by the comparator 151. When the accumulated signal is greater than the preset threshold signal Vth, the output terminal of the comparator 151 outputs a high-level carry signal. When the accumulated signal is less than the preset threshold signal Vth, the signal at the output terminal of the comparator 151 is a low level (that is, no carry signal is output).

[0074] like Figure 5 As shown, the signal accumulation circuit provided in this embodiment further includes: a third reset switch 160 and a fourth reset switch 170;

[0075] The positive plate of the capacitor 110 is grounded through the third reset switch 160, and the closing or opening of the third reset switch 160 is controlled by the carry signal. In response to the carry signal being at a high level, the positive plate of the capacitor 110 is reset;

[0076] The negative plate of the capacitor 110 is grounded through the fourth reset switch 170 , and the closing or opening of the second reset switch 170 is controlled by the carry signal. In response to the carry signal being at a high level, the negative plate of the capacitor 110 is reset.

[0077] In this embodiment, after the accumulation signal carries, if it is necessary to continue to accumulate the input signal inputted subsequently, it is necessary to clear the accumulation signal currently accumulated on the positive plate of the capacitor 110 (the accumulation signal has been represented by the carry signal). Therefore, in this embodiment, the positive plate of the capacitor 110 is reset by controlling the third reset switch 160 to be turned on by the carry signal. In addition, in order to prevent the input signal from being disturbed, while resetting the positive plate of the capacitor 110, the negative plate of the capacitor 110 is reset by controlling the fourth reset switch 170 by the carry signal. Optionally, the third reset switch 160 and the fourth reset switch 170 can be field effect transistors. In this case, the source of the third reset switch 160 is grounded, the drain is connected to the positive plate of the capacitor 110, and the gate is connected to the output end of the comparator 110; the source of the fourth reset switch 170 is grounded, the drain is connected to the negative plate of the capacitor 110, and the gate is connected to the output end of the comparator 110. Therefore, the third reset switch 160 and the fourth reset switch 170 are controlled to be turned on by receiving a high level signal at the gate terminal.

[0078] Figure 6 FIG. 1 is a flow chart of a signal accumulation circuit performing signal accumulation in an optional embodiment of the present disclosure. Figure 6 As shown, the signal accumulation process includes the following stages:

[0079] S1, initial reset stage: control the first reset switch 130 and the second reset switch 140 to be closed, and the signal latch control switch 122, the third reset switch 160 and the fourth reset switch 170 to be opened, and the voltage Vc1 of the upper plate (corresponding to the positive plate in the above embodiment) and the voltage Vc2 of the lower plate (corresponding to the negative plate in the above embodiment) of the capacitor are both reset to zero level (GND), and the output signal of the signal accumulation circuit is also zero level.

[0080] S2, signal input stage: including two situations, when the input signal is the first input signal: the signal latch control switch 122, the first reset switch 130, the second reset switch 140, the third reset switch 160 and the fourth reset switch 170 are all disconnected, the first input signal V1 is input to the lower plate of the capacitor, and the voltage Vc2 of the lower plate of the capacitor rises from zero level to V1. At this time, since the signal latch control switch 122 is disconnected, the signal of the upper plate of the capacitor is not latched. Based on the conservation of capacitor charge, the voltage Vc1 of the upper plate of the capacitor also rises from zero level to V1. Therefore, the accumulated signal is also V1. When the input signal is not the first input signal, when the nth input signal Vn is received, the signal latch control switch 122, the first reset switch 130, the second reset switch 140, the third reset switch 160 and the fourth reset switch 170 are all disconnected; the nth input signal Vn is input to the lower plate of the capacitor, and the lower plate voltage Vc2 of the capacitor rises from zero level to Vn. At this time, since the signal latch control switch 122 is disconnected, the signal on the upper plate of the capacitor is not latched. Based on the conservation of capacitor charge, the upper plate voltage Vc1 of the capacitor also rises by Vn from the previous accumulated signal Vm (which is the accumulated sum of all previous input signals). Therefore, the new accumulated signal is Vm+Vn.

[0081] S3, carry judgment stage: after obtaining the accumulated signal Vm+Vn, determine whether the accumulated signal Vm+Vn is greater than the preset threshold signal Vth. When the accumulated signal Vm+Vn is greater than the preset threshold signal Vth, execute the S7 signal carry stage; when the accumulated signal Vm+Vn is not greater than the preset threshold signal Vth, enter the S4 signal latch stage.

[0082] S4, signal latching stage: after receiving the first input signal, the signal latching control switch 122 is closed, at which time the input and output of the voltage buffer 121 are short-circuited together, the accumulated signal V1 (or Vm+Vn) is latched in the positive plate of the capacitor, and the positive plate voltage Vc1 of the capacitor and the output signal are latched and fixed at V1 (or Vm+Vn). The first reset switch 130, the second reset switch 140, the third reset switch 160 and the fourth reset switch 170 are disconnected.

[0083] S5, input reset stage: the signal latch control switch 122 and the second reset switch 140 are closed, the first reset switch 130, the third reset switch 160 and the fourth reset switch 170 are opened, the negative plate voltage Vc2 of the capacitor is reset to zero level, and the positive plate voltage Vc1 of the capacitor is latched by the voltage buffer 121. The voltage buffer 121 will inject charge into the positive plate of the capacitor, so that the voltage Vc1 of the positive plate of the capacitor continues to maintain at V1 (or Vm+Vn).

[0084] S6. Determine whether there are still input signals that have not been accumulated. If there are still input signals that have not been accumulated, return to execute S2 signal input stage; if there are no input signals that have not been accumulated, enter S8 calculation result output stage.

[0085] S7, signal carry stage: output carry signal and perform carry reset, control the third reset switch 160 and the fourth reset switch 170 to be turned on by the high level carry signal, and reset the upper plate voltage Vc1 of the capacitor and the negative plate voltage Vc2 of the capacitor to zero level.

[0086] S8, calculation result output stage: output the carry signal obtained in the S7 stage and / or the accumulated signal obtained in the S5 stage. Specifically, three situations may be included: the first one, when it is determined through the carry judgment that the signal carries into the stage and no new input signal continues to be received, in this case, the accumulated result only includes the carry signal, and only the carry signal is output at this time; the second one, when it is determined through the carry judgment that the carry is not executed, and no new input signal continues to be received subsequently, in this case, the accumulated result only includes the accumulated signal but not the carry signal, and only the accumulated signal is output at this time; the third one, when it is determined through the carry judgment that the signal carries into the stage and new input signals continue to be received, at this time, not only the carry signal but also the accumulated signal obtained based on the new input signal is included, and in this case, the carry signal and the accumulated signal are output.

[0087] Figure 7 FIG. 1 is a circuit structure diagram of a signal accumulation circuit provided by yet another exemplary embodiment of the present disclosure. Figure 7 As shown, the signal carry circuit 150 in the signal accumulation circuit provided in this embodiment further includes: a multi-bit carry signal counter 152; and the carry result is a multi-bit carry signal.

[0088] The input end of the multi-bit carry signal counter 152 is connected to the output end of the comparator 110 and is used to accumulate and count the multiple carry signals output by the comparator 110 to obtain a multi-bit carry signal. The output end of the multi-bit carry signal counter 152 outputs the multi-bit carry signal.

[0089] Optionally, the multi-bit carry signal counter 152 is also used to perform a reset according to a counter reset signal.

[0090] In this embodiment, in order to further improve the calculation range of the signal accumulation circuit, a multi-bit carry signal counter 152 is added after the comparator to realize multi-bit counting of the carry signal, which can further expand the calculation range of the addition operation. The multi-bit carry signal counter can be a digital counter in the prior art. After the multi-bit carry signal counter 152 is added, before the first counting is performed, or after the counting result is output, it is necessary to control the multi-bit carry signal counter 152 to reset through an external reset control signal, so as to accumulate the carry signal next time.

[0091] Optionally, the signal accumulation circuit including the multi-bit carry signal counter 152 in the above embodiment performs the signal accumulation counting process in a substantially similar manner. Figure 6 The process provided is similar to Figure 6 The main differences include: 1. The multi-bit carry signal counter needs to be reset in the initial reset stage; 2. The judgment condition for calculation overflow is changed from the original single carry to the maximum value that the carry signal can count when the multi-bit carry signal counter 152 reaches. In an optional example, Figure 8 FIG. 1 is a flow chart of a signal accumulation circuit performing signal accumulation in another optional embodiment of the present disclosure. Figure 8 As shown, the signal accumulation process includes the following stages:

[0092] S1, initial reset stage: control the first reset switch 130 and the second reset switch 140 to close, the signal latch control switch 122, the third reset switch 160 and the fourth reset switch 170 to open, and the voltage Vc1 of the upper plate (corresponding to the positive plate in the above embodiment) and the voltage Vc2 of the lower plate (corresponding to the negative plate in the above embodiment) of the capacitor are both reset to zero level (GND), and the output signal of the signal accumulation circuit is also zero level. And reset the multi-bit carry signal counter.

[0093] S2, signal input stage: including two situations, when the input signal is the first input signal: the signal latch control switch 122, the first reset switch 130, the second reset switch 140, the third reset switch 160 and the fourth reset switch 170 are all disconnected, the first input signal V1 is input to the lower plate of the capacitor, and the voltage Vc2 of the lower plate of the capacitor rises from zero level to V1. At this time, since the signal latch control switch 122 is disconnected, the signal of the upper plate of the capacitor is not latched. Based on the conservation of capacitor charge, the voltage Vc1 of the upper plate of the capacitor also rises from zero level to V1. Therefore, the accumulated signal is also V1. When the input signal is not the first input signal, when the nth input signal Vn is received, the signal latch control switch 122, the first reset switch 130, the second reset switch 140, the third reset switch 160 and the fourth reset switch 170 are all disconnected; the nth input signal Vn is input to the lower plate of the capacitor, and the lower plate voltage Vc2 of the capacitor rises from zero level to Vn. At this time, since the signal latch control switch 122 is disconnected, the signal on the upper plate of the capacitor is not latched. Based on the conservation of capacitor charge, the upper plate voltage Vc1 of the capacitor also rises by Vn from the previous accumulated signal Vm (which is the accumulated sum of all previous input signals). Therefore, the new accumulated signal is Vm+Vn.

[0094] S3, carry judgment stage: after obtaining the accumulated signal Vm+Vn, determine whether the accumulated signal Vm+Vn is greater than the preset threshold signal Vth. When the accumulated signal Vm+Vn is greater than the preset threshold signal Vth, execute the S6 signal carry stage; when the accumulated signal Vm+Vn is not greater than the preset threshold signal Vth, enter the S4 signal latch stage.

[0095] S4, signal latching stage: after receiving the first input signal, the signal latching control switch 122 is closed, at which time the input and output of the voltage buffer 121 are short-circuited together, the accumulated signal V1 (or Vm+Vn) is latched in the positive plate of the capacitor, and the positive plate voltage Vc1 of the capacitor and the output signal are latched and fixed at V1 (or Vm+Vn). The first reset switch 130, the second reset switch 140, the third reset switch 160 and the fourth reset switch 170 are disconnected.

[0096] S5, input reset stage: the signal latch control switch 122 and the second reset switch 140 are closed, the first reset switch 130, the third reset switch 160 and the fourth reset switch 170 are opened, the negative plate voltage Vc2 of the capacitor is reset to zero level, and the positive plate voltage Vc1 of the capacitor is latched by the voltage buffer 121. The voltage buffer 121 will inject charge into the positive plate of the capacitor, so that the voltage Vc1 of the positive plate of the capacitor continues to maintain at V1 (or Vm+Vn).

[0097] S6, signal carry stage: output carry signal and perform carry reset, control the third reset switch 160 and the fourth reset switch 170 to be turned on by the high-level carry signal, reset the upper plate voltage Vc1 of the capacitor and the negative plate voltage Vc2 of the capacitor to zero level; input the carry signal into the multi-bit carry signal counter 152, accumulate the carry signal through the multi-bit carry signal counter 152, and obtain the multi-bit carry signal.

[0098] S7, determine whether the multi-bit carry signal reaches the maximum value that the multi-bit carry signal counter 152 can count. If the multi-bit carry signal reaches the maximum value that the multi-bit carry signal counter 152 can count, execute S9; if the multi-bit carry signal does not reach the maximum value that the multi-bit carry signal counter 152 can count, execute S8.

[0099] S8, determining whether it still includes input signals that have not been accumulated. If it still includes input signals that have not been accumulated, returning to execute S2 signal input stage; if it does not include input signals that have not been accumulated, entering S9 calculation result output stage.

[0100] S9, calculation result output stage: output the carry signal obtained in the S7 stage and / or the accumulated signal obtained in the S5 stage. Specifically, three situations may be included: the first one, when it is determined through the carry judgment that no new input signal continues to be received after entering the signal carry stage, in this case, the accumulated result only includes the carry signal, and only the carry signal is output at this time; the second one, when it is determined through the carry judgment that no carry is performed, and no new input signal continues to be received subsequently, in this case, the accumulated result only includes the accumulated signal but not the carry signal, and only the accumulated signal is output at this time; the third one, when it is determined through the carry judgment that new input signal continues to be received after entering the signal carry stage, at this time, not only the carry signal but also the accumulated signal obtained based on the new input signal is included, and in this case, the carry signal and the accumulated signal are output.

[0101] Determine whether the multi-bit carry signal reaches the maximum count value of the multi-bit carry signal counter 152, and if so,

[0102] Determine whether it still includes input signals that have not been accumulated. If it still includes input signals that have not been accumulated, return to the execution signal input stage; if it does not include input signals that have not been accumulated, enter the calculation result output stage.

[0103] Calculation result output stage: output carry signal and / or accumulation signal.

[0104] According to another aspect of the embodiments of the present disclosure, there is provided an electronic device, comprising: a processor, and a memory communicatively connected to the processor, and further comprising the signal accumulation circuit described in any one of the above embodiments;

[0105] The memory stores computer-executable instructions;

[0106] The processor executes computer-executable instructions stored in the memory to control the signal accumulation circuit.

[0107] The electronic device provided by the present disclosure may be incorporated into any of the following: pulse cameras, high-speed cameras, audio / video players, navigation devices, fixed-position terminals, entertainment units, smart phones, communication devices, devices in motor vehicles, cameras, sports or wearable cameras, detection equipment, flight equipment, medical equipment, security equipment, etc.

[0108] The electronic device provided by the present disclosure can be applied to any of the following: pulse cameras, high-speed cameras, audio / video players, navigation equipment, fixed-position terminals, entertainment units, smart phones, communication equipment, equipment in motor vehicles, cameras, sports or wearable cameras, detection equipment, flight equipment, medical equipment, security equipment, etc.

[0109] Below, reference Fig. 9 The electronic device according to the embodiment of the present disclosure is described. The electronic device may be any one or both of the first device and the second device, or a stand-alone device independent of them, and the stand-alone device may communicate with the first device and the second device to receive the collected input signals from them.

[0110] Fig. 9 A block diagram of an electronic device according to an embodiment of the present disclosure is illustrated.

[0111] like Fig. 9 As shown, the electronic device includes one or more processors and memory.

[0112] The processor may be a central processing unit (CPU) or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device to perform desired functions.

[0113] The memory may store one or more computer program products, and the memory may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, a random access memory (RAM) and / or a cache memory (cache), etc. The non-volatile memory may include, for example, a read-only memory (ROM), a hard disk, a flash memory, etc. One or more computer program products may be stored on the computer-readable storage medium, and the processor may run the computer program product to implement the signal accumulation circuit and / or other desired functions of the various embodiments of the present disclosure described above.

[0114] In one example, the electronic device may further include: an input device and an output device, and these components are interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0115] In addition, the input device may also include, for example, a keyboard, a mouse, and the like.

[0116] The output device can output various information to the outside, including determined distance information, direction information, etc. The output device can include, for example, a display, a speaker, a printer, a communication network and a remote output device connected thereto, and the like.

[0117] Of course, to simplify, Fig. 9 Only some of the components related to the present disclosure in the electronic device are shown, and components such as a bus, an input / output interface, etc. are omitted. In addition, according to specific application situations, the electronic device may further include any other appropriate components.

[0118] In addition to the above-mentioned methods and devices, an embodiment of the present disclosure may also be a computer program product, which includes computer program instructions, which, when executed by a processor, enable the processor to execute the steps in the signal accumulation circuit according to various embodiments of the present disclosure described in the above part of this specification.

[0119] The computer program product may be written in any combination of one or more programming languages ​​to write program code for performing the operations of the disclosed embodiments, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0120] In addition, an embodiment of the present disclosure may also be a computer-readable storage medium having computer program instructions stored thereon, which, when executed by a processor, enables the processor to execute the steps in the signal accumulation circuit according to various embodiments of the present disclosure described in the above part of this specification.

[0121] The computer readable storage medium can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium can include, for example, but is not limited to, a system, device or device of electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination of the above. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0122] The basic principles of the present disclosure are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present disclosure are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present disclosure. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, and are not limitations. The above details do not limit the present disclosure to the necessity of adopting the above specific details to be implemented.

[0123] Each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the system embodiment, since it basically corresponds to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0124] The block diagrams of the devices, apparatuses, equipment, and systems involved in this disclosure are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As will be appreciated by those skilled in the art, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including," "comprising," "having," and the like are open words, referring to "including but not limited to," and can be used interchangeably therewith. The words "or" and "and" used herein refer to the words "and / or," and can be used interchangeably therewith, unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to," and can be used interchangeably therewith.

[0125] The method and apparatus of the present disclosure may be implemented in many ways. For example, the method and apparatus of the present disclosure may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above order of steps for the method is for illustration only, and the steps of the method of the present disclosure are not limited to the order specifically described above, unless otherwise specifically stated. In addition, in some embodiments, the present disclosure may also be implemented as a program recorded in a recording medium, which includes machine-readable instructions for implementing the method according to the present disclosure. Therefore, the present disclosure also covers a recording medium storing a program for executing the method according to the present disclosure.

[0126] It should also be noted that in the apparatus, device and method of the present disclosure, each component or each step can be decomposed and / or recombined. Such decomposition and / or recombination should be regarded as equivalent solutions of the present disclosure.

[0127] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the aspects shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

[0128] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present disclosure to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. A signal accumulation circuit, characterized in that: include: a capacitor and a signal latch circuit; The negative plate of the capacitor serves as a circuit input terminal to sequentially receive input signals, and the positive plate of the capacitor is connected to the input terminal of the signal latch circuit; The input end of the signal latch circuit is connected to the positive plate of the capacitor, and the output end serves as a circuit output end to output an accumulated signal; wherein the accumulated signal is an accumulated result of the input signals input multiple times.

2. The circuit according to claim 1, characterized in that The signal latch circuit includes a voltage buffer and a signal latch control switch connected in parallel; The signal latch control switch is turned on or off according to the control of the external latch signal, and in response to the signal latch control switch being turned off, the input signal is transmitted from the negative plate of the capacitor to the positive plate of the capacitor; In response to the signal latch control switch being closed, the accumulated signal of the positive plate of the capacitor is latched by the voltage buffer.

3. The circuit according to claim 1 or 2, characterized in that Also includes: a first reset switch and a second reset switch; The positive plate of the capacitor is grounded through the first reset switch, the first reset switch is controlled to be closed or opened through a first reset signal, and the positive plate of the capacitor is reset in response to the first reset switch being closed; The negative plate of the capacitor is grounded through the second reset switch, the second reset switch is controlled to be closed or opened by a second reset signal, and the negative plate of the capacitor is reset in response to the second reset switch being closed.

4. The circuit according to claim 3, characterized in that Also includes: Signal carry circuit; The input end of the signal carry circuit is connected to the output end of the signal latch circuit, and in response to the accumulation signal reaching a preset condition, the carry result is output through the output end of the signal carry circuit.

5. The circuit according to claim 4, characterized in that The signal carry circuit comprises: a comparator; the carry result is a carry signal; The positive input terminal of the comparator is connected to the output terminal of the signal latch circuit, and the negative input terminal receives a preset threshold signal. In response to the accumulated signal being greater than the preset threshold signal, the carry signal is output through the output terminal of the comparator.

6. The circuit according to claim 5, characterized in that The circuit further comprises: a third reset switch and a fourth reset switch; The positive plate of the capacitor is grounded through the third reset switch, and the closing or opening of the third reset switch is controlled by the carry signal; The negative plate of the capacitor is grounded via the fourth reset switch, and the closing or opening of the second reset switch is controlled by the carry signal.

7. The circuit according to claim 6, characterized in that The source of the third reset switch is grounded, the drain is connected to the positive plate of the capacitor, and the gate is connected to the output end of the comparator; The source of the fourth reset switch is grounded, the drain is connected to the negative plate of the capacitor, and the gate is connected to the output end of the comparator.

8. The circuit according to claim 5, characterized in that The signal carry circuit further comprises: a multi-bit carry signal counter; the carry result is a multi-bit carry signal; The input end of the multi-bit carry signal counter is connected to the output end of the comparator, and is used to accumulate and count multiple carry signals output by the comparator to obtain the multi-bit carry signal. The output end of the multi-bit carry signal counter outputs the multi-bit carry signal.

9. An electronic device, characterized in that: include: A processor, and a memory communicatively connected to the processor, further comprising the signal accumulation circuit according to any one of claims 1 to 8; The memory stores computer-executable instructions; The processor executes computer-executable instructions stored in the memory to control the signal accumulation circuit.

10. The electronic device according to claim 9, characterized in that: The electronic device is any one of the following: a pulse camera, a high-speed camera, an audio / video player, a navigation device, a fixed-position terminal, an entertainment unit, a smart phone, a communication device, a device in a motor vehicle, a camera, a sports or wearable camera, a detection device, a flight device, a medical device, and a security device.

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