Double-layer memory packaging structure

Abstract

The utility model relates to a double-layer memory packaging structure, which comprises a carrier plate including an upper carrier plate and a lower carrier plate, the upper carrier plate is connected to the upper end of the lower carrier plate, and the upper carrier plate is electrically connected with the lower carrier plate; and the chip set is arranged at the upper end of the carrier plate and comprises a high-bit-element chip set and a low-bit-element chip set, the high-bit-element chip set is arranged at the upper end of the upper carrier plate, and the low-bit-element chip set is connected with the upper end of the lower carrier plate. By the adoption of the structure, stacking of multiple layers of chips is achieved, and the problem of heating in the storage process is solved.

Description

Technical Field

[0001] The utility model relates to the technical field of memory stacks, and in particular to a double-layer memory packaging structure. Background Art

[0002] With the rapid development of science and technology, the demand for high performance, miniaturization and low power consumption of electronic devices is increasing. In traditional packaging design or circuit design, when a circuit design with multiple layers of chip stacks is required, it is difficult to detect the damage of the chip during die bonding due to the large number of chips. In addition, due to the excessive complexity of the wiring on the circuit, the anti-noise area is small during wiring, which is prone to signal interference or signal delay problems, resulting in limited transmission frequency.

[0003] Therefore, there is an urgent need to provide a double-layer memory packaging structure to solve the above problems. Utility Model Content

[0004] The purpose of the utility model is to overcome the shortcomings and defects of the prior art, provide a double-layer memory packaging structure, realize the stacking of multiple layers of chips, and reduce the heating problem during the storage process.

[0005] The purpose of this utility model is achieved through the following technical solutions:

[0006] A double-layer memory packaging structure, characterized by comprising:

[0007] A carrier board, comprising an upper carrier board and a lower carrier board, wherein the upper carrier board is connected to the upper end of the lower carrier board, and the upper carrier board and the lower carrier board are electrically connected;

[0008] The chipset is arranged at the upper end of the carrier board, and the chipset comprises a high-bit chipset and a low-bit chipset. The high-bit chipset is arranged at the upper end of the upper carrier board, and the low-bit chipset is connected to the upper end of the download board.

[0009] Optionally, a connecting bridge is provided between the upload board and the download board, the upper end of the connecting bridge is connected to the lower end of the upload board, and the lower end of the connecting bridge is connected to the upper end of the download board.

[0010] Optionally, the double-layer memory packaging structure further includes a gasket, which is disposed between the low-bit chipset and the upper loading board.

[0011] Optionally, two adjacent groups of chips are connected by wire welding.

[0012] Optionally, the high-bit chipset includes multiple groups of high-bit chips, which are stacked on the upper end of the upload board; the low-bit chipset includes multiple groups of low-bit chips, which are stacked on the upper end of the download board.

[0013] Optionally, the high-bit chips are provided in 8-16 groups, and the low-bit chips are provided in 8-16 groups.

[0014] Optionally, the high-bit chipset is connected to the upper loading board by die bonding through a die bonding machine, and the low-bit chipset is connected to the lower loading board by die bonding through a die bonding machine.

[0015] Optionally, a FOW gasket is provided above the download board, and the upper upload board is provided above the FOW gasket, and signal conduction is achieved between the upper upload board and the download board through the FOW gasket.

[0016] Compared with the prior art, the utility model has the following beneficial effects:

[0017] In the utility model, the double-layer memory packaging structure includes a carrier board, the carrier board includes an upper upload board and a download board, wherein the upper upload board is arranged at the upper end of the download board, and the upper upload board and the download board are electrically connected, so that signals can be transmitted and exchanged between the upper upload board and the download board; a chipset is arranged on the carrier board, and the chipset includes a high-bit chipset and a low-bit chipset, the upper end of the upper upload board is provided with a high-bit chipset, and the upper end of the download board is provided with a low-bit chipset. Through the separation design of the high-bit chipset and the low-bit chipset, the problem of data anomalies can be effectively reduced, the problem of excessive heat generation during the storage process can be reduced, and better EMS anti-noise capability can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is the structural principle diagram of the utility model.

[0019] Figure 2 This is a schematic diagram of the packaging principle in the utility model.

[0020] The above drawings include the following reference numerals:

[0021] 1. Carrier board, 11. Uploader board, 12. Download board, 21. High-bit chipset, 211. High-bit chip, 22. Low-bit chipset, 221. Low-bit chip, 31. Connecting bridge, 32. Gasket, 4. Lead wire. DETAILED DESCRIPTION

[0022] The present invention is further described in detail below in conjunction with embodiments and drawings, but the implementation manner of the present invention is not limited thereto.

[0023] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "provided with", "connected", etc. should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the technical field of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0025] The technical solution of the utility model proposes a double-layer memory packaging structure.

[0026] Reference Figure 1 and Figure 2 , in this embodiment, includes:

[0027] The carrier board 1 includes an upper carrier board 11 and a lower carrier board 12. The upper carrier board 11 is connected to the upper end of the lower carrier board 12, and the upper carrier board 11 and the lower carrier board 12 are electrically connected.

[0028] The chipset is disposed on the upper end of the carrier board 1 , and includes a high-bit chipset 21 and a low-bit chipset 22 . The high-bit chipset 21 is disposed on the upper end of the upper carrier board 11 , and the low-bit chipset 22 is connected to the upper end of the download board 12 .

[0029] Optionally, in this embodiment, the double-layer memory packaging structure includes a carrier board 1, the carrier board 1 includes an upper upload board 11 and a download board 12, wherein the upper upload board 11 is arranged at the upper end of the download board 12, and the upper upload board 11 and the download board 12 are electrically connected, so that signals can be transmitted and exchanged between the upper upload board 11 and the download board 12; a chipset is provided on the carrier board 1, and the chipset includes a high-bit chipset 21 and a low-bit chipset 22, the high-bit chipset 21 is provided at the upper end of the upper upload board 11, and the low-bit chipset 22 is provided at the upper end of the download board 12, wherein the high-bit chipset 21 generally refers to a chipset for processing high-bandwidth data (for example, high-definition video, complex graphics, etc.), these chipsets generally need to process a large amount of data, and therefore have a higher data processing capability, and they are generally used in high-performance computing, high-end games, multimedia applications and other fields. Compared with the high-bit chipset 21, the low-bit chipset 22 processes relatively fewer data bits and is usually used for simpler tasks, such as basic input, output and control. The upload board 11 and the download board 12 are of different sizes, and the size of the upload board 11 is larger than that of the download board 12. At the same time, the high-bit chipset 21 is stacked on the upload board 11, and the low-bit chipset 22 is stacked on the download board 12. The separation design of the high-bit chipset 21 and the low-bit chipset 22 can effectively reduce data anomalies and the problem of excessive heat generation during storage, and can achieve better EMS noise resistance. The separation design of high bits and low bits can achieve more layers of chip stacking, and the design of the two-layer carrier board 1 allows the high-stack chip to have better structural support when stacking.

[0030] In this embodiment, a connecting bridge 31 is provided between the upper upload board 11 and the download board 12, the upper end of the connecting bridge 31 is connected to the lower end of the upper upload board 11, and the lower end of the connecting bridge 31 is connected to the upper end of the download board 12, that is, the upper upload board 11 and the download board 12 are connected through the connecting bridge 31, and the setting of the connecting bridge 31 can provide support for the upper upload board 11, so that there is a certain space between the upper upload board 11 and the download board 12, which can reduce the heat generated during the storage process. Further, in this embodiment, the double-layer memory packaging structure also includes a gasket 32, which is located between the low-bit chipset 22 and the upper upload board 11. Through the setting of the gasket 32, the risk of short circuit or electric shock caused by direct contact between the upper upload board 11 and the download board 12 is avoided, and the setting of the gasket 32 ​​can also provide support, so that the contact between the upper upload board 11 and the download board 12 is more stable.

[0031] In the present embodiment, welding points are provided at both ends of the chip, and the two adjacent groups of chips are connected by welding with leads 4, that is, two adjacent groups of high-bit chips 211 and two adjacent groups of low-bit chips 221 are connected by welding with leads 4. In the prior art, two adjacent groups of chips are usually provided with connection holes, and the connection of the two adjacent groups of chips is achieved by passing wires through the connection holes. This not only makes the wiring complex and occupies a large area, but also easily causes a short circuit or functional failure of the chipset. By welding the welding points with leads 4, it is not necessary to open connection holes for the upper and lower chips, and it is not necessary to align the positions of the upper and lower chips for connection, and the setting of the wires is convenient and flexible.

[0032] In this embodiment, the high-bit chip set 21 includes multiple groups of high-bit chips 211, and the multiple groups of high-bit chips 211 are stacked on the upper end of the upper loading board 11; the low-bit chip set 22 includes multiple groups of low-bit chips 221, and the multiple groups of low-bit chips 221 are stacked on the upper end of the download board 12. Furthermore, the high-bit chips 211 are provided with 8-16 groups, and the low-bit chips 221 are provided with 8-16 groups. Through the separate design of the carrier board 1, the upper loading board 11 can support the stacking of 8-16 groups of chips, and the download board 12 can support the stacking of 8-16 groups of chips. Then, the two adjacent groups of chips are wire-welded 4 by a wire bonding machine, and then the signal pins of the two carrier boards 1 are matched to complete a 16-32-bit wide high-speed, high-capacity, and high-stacked storage chip.

[0033] In this embodiment, the high-bit chipset 21 is connected to the upper board 11 by a die bonding machine, that is, a plurality of high-bit chips 211 are stacked by welding leads 4, and a plurality of low-bit chips 221 are stacked by welding leads 4; the die bonding machine fixes the high-bit chips 211 stack on the upper end of the upper board 11 and the low-bit chips 221 stack on the upper end of the download board 12 by adhesive or solder. During the die bonding process, it is necessary to ensure the alignment accuracy and fit between the chip and the carrier 1 to ensure the subsequent circuit connection and signal transmission quality.

[0034] The steps of packaging the chip stack are as follows: a die bonding process is performed on the chip stack of the upper loading board 11 and the chip stack of the downloading board 12, so that the high-bit chipset 21 can be fixed on the upper loading board 11, and the low-bit chipset 22 can be fixed on the downloading board 12, and then a plastic or elastic material is filled between the chip stack and the carrier 1 to fill the gap; the product is then placed in a vacuum for 120° baking, and after the baking is completed, the chip stack is subjected to a lead 4 welding process, and further, the product is subjected to AOI and ICT tests, and the defects and performance of the chip stack product are detected, and subsequent operations are performed if they meet the standards; after the test is completed, the product is subjected to a three-dimensional steel mesh ball implantation process, and the carrier 1 is combined, and after completion, it is placed in a vacuum for 120° baking, and laser welding is used at the same time. Subsequently, the chip stack is packaged through a molding process, laser printing and laser cutting, and finally, the finished product is functionally tested, and the packaging is completed if it meets the test standards.

[0035] The above-mentioned embodiments only express the implementation methods of the utility model, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent of the utility model. It should be pointed out that, for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the utility model, and these all belong to the protection scope of the utility model. Therefore, the protection scope of the utility model patent shall be based on the attached claims.

Claims

1. A double-layer memory packaging structure, characterized in that: include: A carrier board, comprising an upper carrier board and a lower carrier board, wherein the upper carrier board is connected to the upper end of the lower carrier board, and the upper carrier board and the lower carrier board are electrically connected; The chipset is arranged at the upper end of the carrier board, and the chipset comprises a high-bit chipset and a low-bit chipset. The high-bit chipset is arranged at the upper end of the upper carrier board, and the low-bit chipset is connected to the upper end of the download board.

2. A double-layer memory packaging structure according to claim 1, characterized in that: A connecting bridge is provided between the upload board and the download board, the upper end of the connecting bridge is connected to the lower end of the upload board, and the lower end of the connecting bridge is connected to the upper end of the download board.

3. The double-layer memory packaging structure according to claim 1, characterized in that: The double-layer memory package structure further comprises a gasket, which is arranged between the low-bit chipset and the upper loading board.

4. The double-layer memory packaging structure according to claim 1, characterized in that: Two adjacent groups of chips are connected by wire welding.

5. The double-layer memory packaging structure according to claim 1, characterized in that: The high-bit chip set includes multiple groups of high-bit chips, which are stacked on the upper end of the upload board; the low-bit chip set includes multiple groups of low-bit chips, which are stacked on the upper end of the download board.

6. A double-layer memory packaging structure according to claim 4, characterized in that: The high-bit chips are provided in 8-16 groups, and the low-bit chips are provided in 8-16 groups.

7. A double-layer memory packaging structure according to claim 4, characterized in that: The high-bit chipset is connected to the upper loading board by a die bonding machine, and the low-bit chipset is connected to the downloading board by a die bonding machine.

8. The double-layer memory packaging structure according to claim 1, characterized in that: A FOW gasket is arranged above the download board, and the upper upload board is arranged above the FOW gasket, and signal conduction is achieved between the upper upload board and the download board through the FOW gasket.

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