Plastic package chip packaging structure capable of effectively reducing warping of fan-out type plate-level packaging substrate

Abstract

The utility model discloses a plastic package chip packaging structure capable of effectively reducing warping of a fan-out type plate-level packaging substrate. The plastic package chip packaging structure comprises the following steps: S1, forming an adhesive film layer on a bearing plate; s2, placing a chip on the bearing plate with the adhesive film layer; s3, placing a small plastic package filling block on the other bearing plate with the adhesive film layer; s4, integrating the structures obtained in S2 and S3 through a plastic packaging process to obtain a complex; s5, removing the bearing plates and the adhesive film layers on the front and back surfaces of the complex; s6, forming a first insulating layer on the surface of the composite chip; s7, forming a first metal redistribution layer on the first composite insulating layer; s8, forming a second insulating layer on the composite first metal redistribution layer; s9, forming a second metal redistribution layer on the second composite insulating layer; s10, completing reballing on the second metal rewiring layer of the composite body; and S11, cutting to obtain a single Die. According to the structure, the chip packaging process under the condition of smaller warping degree of the packaging substrate can be realized, the packaging efficiency can be greatly improved, and the processing cost is remarkably reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor chip packaging, and in particular to a plastic-encapsulated chip packaging structure which can effectively reduce the warping of a fan-out type board-level packaging substrate. Background Art

[0002] As the requirements for functional integration, large storage space, high reliability and miniaturized packaging of mobile consumer electronic products such as mobile phones, computers, and digital cameras become increasingly higher, the overall development trend of miniaturized, lightweight, high-performance, multi-functional, high-reliability and low-cost electronic products means that the number of transistors on a single chip is no longer the main challenge, but the development of more advanced packaging to meet the needs of light, thin, short, small and system integration. Fan-out Wafer Level Package (FOWLP) is a type of wafer-level packaging. It is the main advanced packaging process for a large number of input / output ports (I / O) and high integration flexibility (multi-chip integration in vertical and horizontal directions). It is mostly used for multi-chip, ultra-thin packaging and three-dimensional system-level packaging. At the same time, the emergence of FOWLP technology has greatly increased the number of I / Os in the package, which is in line with the development direction of chip multi-functionality. However, due to the increasing market demand, in order to break through the existing methods, combine the PCB board-level production concept with the semiconductor wafer-level packaging method, and break the size limitation of the original wafer, it is necessary to propose a packaging technology that can accommodate more I / O numbers, reduce chip size and thickness, and integrate more heterogeneous chips to meet the packaging miniaturization requirements, which can effectively reduce production costs, improve production efficiency, and ultimately be applied to consumer, high-speed computing, and professional electronic products.

[0003] Based on the above multiple packaging requirements, Fan-out Panel Level Package (FOPLP) technology came into being. The difference between the FOPLP process and FOWLP is that it uses a larger panel instead of a wafer, and there are differences in the materials, equipment, and line width and line spacing of the product. The emergence of FOPLP technology can effectively achieve a larger overall package, further increase the packaging efficiency, reduce the packaging cost, and have a broader development prospect. At present, the size of FOPLP samples has gradually developed from the initial 300*300mm to 500*500mm, 600*600mm, and even larger package sizes. Compared with FOWLP technology, FOPLP technology has the advantages of lower cost, flexible design, good electrothermal performance, diverse business models, and a wide range of applications. However, the existing FOPLP technology uses plastic encapsulation to embed the chip. In the subsequent process, due to the uneven force of the fan-out packaging structure, the board-level product has a more serious warping problem, which greatly reduces the manufacturing efficiency and increases the production cost. Therefore, how to effectively reduce the warpage of fan-out panel-level packaging substrates during the manufacturing process has always been a hot issue that needs to be urgently solved in FOPLP technology. Summary of the invention

[0004] In order to solve the above technical problems, the purpose of the present invention is to provide a plastic-encapsulated chip packaging structure that effectively reduces the warping of the fan-out board-level packaging substrate. A new type of composite body formed by integrating two carrier boards with pasted chips (or small filling pieces) through a plastic encapsulation process can effectively reduce the warping degree of the packaging substrate; the chip packaging structure can realize the chip packaging process under a smaller packaging substrate warping degree, which can greatly improve the packaging efficiency and significantly reduce the processing cost.

[0005] In order to achieve the above technical objectives and the above technical effects, the present invention provides a plastic-encapsulated chip packaging structure that effectively reduces the warping of a fan-out type panel-level packaging substrate, comprising:

[0006] The adhesive film assembly includes a carrier plate and an adhesive film layer bonded to the carrier plate; the adhesive film assembly is divided into a lower surface of the carrier plate and an upper surface of the adhesive film layer;

[0007] A chip assembly is placed on the upper surface of an adhesive film layer of an adhesive film assembly to form a chip assembly structure, wherein the chip assembly includes a chip and a chip conductive structure, the chip front side faces downward, and the chip conductive structure is bonded to the upper surface of the adhesive film layer;

[0008] A plastic encapsulation filling block is placed on the upper surface of the adhesive film layer of another adhesive film assembly to form a plastic encapsulation filling block structure;

[0009] A plastic encapsulation structure in which the chip component structure and the plastic encapsulation filling small block structure are integrated together by plastic encapsulation, a plastic encapsulation layer is formed between the chip component structure and the plastic encapsulation filling small block structure, and the chip and the plastic encapsulation filling small block are arranged facing each other;

[0010] The double-sided carrier plate and the adhesive film layer of the plastic-sealed structure are removed to obtain a composite structure, wherein the composite structure comprises a back side of the structure and a front side of the structure;

[0011] A first insulating layer is arranged on the front side of the composite structure to form a conductive through-hole structure; a first metal redistribution is arranged on the conductive through-hole structure; a second insulating layer is arranged on the first metal redistribution structure to form a conductive through-hole structure; a second metal redistribution is arranged on the conductive through-hole structure of the second insulating layer, and ball planting is completed on the second metal redistribution structure, wherein the ball is a conductive solder ball.

[0012] Furthermore, the ball implant structure is cut into individual dies.

[0013] Furthermore, during the plastic packaging integration process of the plastic packaging structure, the chip carrier plate with adhesive must be placed at the bottom; the solid plastic packaging material is evenly sprinkled on the surface of the chip carrier plate with adhesive and the back of the chip; and the carrier plate with small plastic packaging filling pieces must be placed at the top.

[0014] Furthermore, the material of the supporting plate is metal, silicon-based, glass or other materials, and the size of the supporting plate is 300*300mm, 450*450mm, 500*500mm, 600*600mm or other sizes; preferably, the material of the supporting plate is steel plate, and the size of the supporting plate is 600*600mm.

[0015] Furthermore, the material of the plastic-encapsulated filling small pieces is silicon-based, glass or other materials; preferably, the material of the filling small pieces is silicon-based.

[0016] Furthermore, the material of the insulating layer is epoxy resin, silicon oxide insulating material or other insulating materials; preferably, the material of the insulating layer is photosensitive epoxy resin.

[0017] Furthermore, the material of the metal redistribution layer is one or a combination of two or more of aluminum, copper, gold, platinum, nickel, and tin; preferably, the material of the metal redistribution layer of the insulating layer is copper.

[0018] The beneficial effects of the present invention are mainly the following four points: (1) two carrier plates with pasted chips (or filling small pieces) are integrated together through a plastic encapsulation process to form a new composite body, forming a new plastic encapsulation process (i.e., two carrier plates are plastic encapsulated at the same time, and the carrier plates are located on both sides of the plastic encapsulation); (2) the stress generated by the filling small pieces embedded in the back of the plastic encapsulation layer is used to offset the stress generated by the chip embedded in the front of the plastic encapsulation layer, so as to effectively reduce the warping of the fan-out type board-level packaging substrate, so as to ensure the smooth completion of the entire packaging process; (3) the thickness, size, pasting density and pasting position of the filling small pieces embedded in the back of the plastic encapsulation layer can be optimized through relevant simulation to ensure that the packaging substrate has less warping; (4) the filling small pieces embedded in the back of the plastic encapsulation layer have no effect on the front chip cutting process, that is, during the cutting process, the cutting can be carried out avoiding the position of the filling small pieces, or cutting can be carried out from the position where the filling small pieces are placed, and the cutting method is relatively flexible. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A structural diagram of forming an adhesive film layer on a carrier plate.

[0020] Figure 2 For Figure 1 Structural diagram of a chip pasted on the structure shown.

[0021] Figure 3 For another Figure 1 Structural diagram of a small piece of plastic-encapsulated filling pasted on the structure shown.

[0022] Figure 4 For the general Figure 2 and Figure 3 The structure shown is integrated together through the plastic packaging process.

[0023] Figure 5 Structural diagram for removing the double-sided carrier board and adhesive film layer.

[0024] Figure 6 For Figure 5 A first insulating layer is formed on the structure and a conductive via structure is formed.

[0025] Figure 7 For Figure 6 A structural diagram of a first metal redistribution is formed on the structure shown.

[0026] Figure 8 For Figure 7 A second insulating layer is formed on the structure and a conductive via structure is formed.

[0027] Fig. 9 For Figure 8 A structural diagram of a second metal redistribution is formed on the structure shown.

[0028] Fig.10 For Fig. 9 The structural diagram of the ball implantation is completed on the structure shown.

[0029] Fig.11 For Fig.10 Structural diagram of the structure shown in the figure for cutting. DETAILED DESCRIPTION

[0030] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0031] (1) forming an adhesive film layer on a carrier plate to obtain Figure 1 The structure shown in FIG. 10 is a carrier plate, 11 is an adhesive film layer, 201 is a lower surface of the carrier plate, and 202 is an upper surface of the adhesive film layer.

[0032] (2) Figure 1 Paste the chip on the structure shown (make sure the chip Pad faces downward), and get the following Figure 2 The structure shown in FIG. 12 is a chip, and 13 is a chip conductive structure (ie, Al Pad).

[0033] (3) In another Figure 1 Paste a small plastic filling block on the structure shown in the figure to obtain Figure 3 The structure shown in FIG. 301 is a small plastic-encapsulated filling block.

[0034] (4) Figure 2 and Figure 3 The structures shown are integrated together through the plastic packaging process to obtain Figure 4 The structure shown. 14 is a plastic sealing layer. Special attention should be paid to the following during the plastic sealing process: ① The chip carrier plate with adhesive obtained in step (2) must be placed at the bottom; ② The solid plastic sealing material is evenly sprinkled on the surface of the chip carrier plate 202 with adhesive obtained in step (2) and the back of the chip; ③ The carrier plate with plastic sealing filling blocks obtained in step (3) must be placed at the top.

[0035] (5) removing the double-sided support plate and adhesive film layer of the structure obtained in step (4) to obtain Figure 5 The structure shown in FIG. 203 is the back side of the newly obtained structure, and 204 is the front side of the newly obtained structure.

[0036] (6) Figure 5 A first insulating layer is formed on the structure shown in FIG. 1 and a conductive through-hole structure is formed to obtain a structure as shown in FIG. Figure 6 The structure shown in FIG. 15 is a first insulating layer, 205 is an upper surface of the first insulating layer, and 206 is a conductive through-hole structure formed on the first insulating layer.

[0037] (7) Figure 6 A first metal redistribution is formed on the structure shown in FIG. Figure 7The structure shown in FIG. 16 is the first metal redistribution wiring.

[0038] (8) Figure 7 A second insulating layer is formed on the structure shown in FIG. 1 and a conductive through-hole structure is formed to obtain Figure 8 The structure shown in FIG. 17 is the second insulating layer, 207 is the upper surface of the first insulating layer, and 208 is the conductive through-hole structure formed on the first insulating layer.

[0039] (9) Figure 8 A second metal redistribution (i.e., pad) is formed on the structure shown in FIG. Fig. 9 The structure shown in FIG. 18 is the second metal redistribution wiring.

[0040] (10) Fig. 9 The ball implantation process is completed on the structure shown in the figure, and the Fig.10 The structure shown in FIG. 19 is a conductive structure (solder ball).

[0041] (11) Yes Fig.10 The structure shown is cut to obtain Fig.11 The structure shown.

[0042] The following three points must be ensured in the plastic encapsulation process of the fan-out type board-level packaging substrate: ① The carrier board with the chip attached obtained in step (2) must be placed at the bottom; ② The solid plastic encapsulation material is evenly sprinkled on the surface of the carrier board 202 with the chip attached obtained in step (2) and the back of the chip; ③ The carrier board with the plastic encapsulation filling small pieces obtained in step (3) must be placed at the top. The two carrier boards are integrated together at one time through plastic encapsulation, and the chip and the filling small pieces are ensured to be distributed on different surfaces of the plastic encapsulation layer (i.e., the upper surface and the lower surface). In the plastic encapsulation process of the fan-out type board-level packaging substrate, there are usually only two plastic encapsulation methods: ① The carrier board with the chip attached is placed at the bottom, and the solid plastic encapsulation material is evenly sprinkled on the carrier board. Under high temperature conditions, the solid plastic encapsulation material melts and embeds the chip to form a plastic encapsulation layer; ② The liquid plastic encapsulation material is placed at the bottom, and the carrier board with the chip attached is placed at the top. Under high temperature conditions, the carrier board is immersed in the liquid plastic encapsulation material, and the chip is embedded to form a plastic encapsulation layer after cooling. The method proposed in this embodiment to integrate two carrier plates together at one time through a plastic encapsulation process and to ensure that the chip and the filling pieces are distributed on different surfaces (ie, the upper surface and the lower surface) of the plastic encapsulation layer is also a new type of plastic encapsulation process.

[0043] It is worth noting that: in the description of the present invention, the meaning of "multiple" is two or more than two, unless otherwise clearly and specifically defined. In the present invention, unless otherwise clearly stipulated and defined, the terms "install", "connect", "connect", "fix" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection; the circuits described in the present invention are all commonly used circuits in the art, and other related components are all existing commonly used components. For ordinary technicians in the art, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances.

[0044] It is obvious to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential features of the present invention. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-restrictive, and the scope of the present invention is defined by the appended claims rather than the above description, and it is intended that all changes that fall within the meaning and scope of the elements of the claims be included in the present invention. Any reference numeral in a claim should not be regarded as limiting the claim to which it relates.

Claims

1. A plastic-encapsulated chip packaging structure that effectively reduces the warpage of a fan-out type panel-level packaging substrate, characterized in that: include: The adhesive film assembly includes a carrier plate and an adhesive film layer bonded to the carrier plate; the adhesive film assembly is divided into a lower surface of the carrier plate and an upper surface of the adhesive film layer; A chip assembly is placed on the upper surface of an adhesive film layer of an adhesive film assembly to form a chip assembly structure, wherein the chip assembly includes a chip and a chip conductive structure, the chip front side faces downward, and the chip conductive structure is bonded to the upper surface of the adhesive film layer; A plastic encapsulation filling block is placed on the upper surface of the adhesive film layer of another adhesive film assembly to form a plastic encapsulation filling block structure; A plastic encapsulation structure in which the chip component structure and the plastic encapsulation filling small block structure are integrated together by plastic encapsulation, a plastic encapsulation layer is formed between the chip component structure and the plastic encapsulation filling small block structure, and the chip and the plastic encapsulation filling small block are arranged facing each other; The double-sided carrier plate and the adhesive film layer of the plastic-sealed structure are removed to obtain a composite structure, wherein the composite structure comprises a back side of the structure and a front side of the structure; A first insulating layer is arranged on the front side of the composite structure to form a conductive through-hole structure; a first metal redistribution is arranged on the conductive through-hole structure; a second insulating layer is arranged on the first metal redistribution to form a conductive through-hole structure; a second metal redistribution is arranged on the conductive through-hole structure of the second insulating layer, and a ball implantation process is completed on the second metal redistribution, wherein the ball is a conductive solder ball.

2. The plastic-encapsulated chip packaging structure for effectively reducing the warpage of the fan-out type panel-level packaging substrate as claimed in claim 1, characterized in that: The ball implant structure is cut to obtain a single Die.

3. The plastic-encapsulated chip packaging structure for effectively reducing the warpage of the fan-out type panel-level packaging substrate as claimed in claim 1, characterized in that: During the plastic packaging integration process of the plastic packaging structure, the chip carrier board with adhesive must be placed at the bottom; the solid plastic packaging material is evenly sprinkled on the surface of the chip carrier board with adhesive and the back of the chip; the carrier board with small plastic packaging filling pieces must be placed at the top.

4. A plastic-encapsulated chip packaging structure that effectively reduces the warpage of a fan-out type panel-level packaging substrate according to claim 1, characterized in that: The material of the carrier board is metal, silicon-based or glass; the material of the small plastic-encapsulated filling block is silicon-based or glass.

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