Wiring substrate

Abstract

In order to obtain a high-frequency module with less warping, small size, and high connection reliability, a wiring substrate is provided, which has: a core material made of glass, having a first surface, a second surface opposite to the first surface, and a through-hole passing through the first surface to the second surface; a first adhesion layer formed so as to adhere to the first surface and an inner wall of the through-hole, and further block a bottom of the through-hole on the second surface side; a second adhesion layer adhering to the second surface and the first adhesion layer blocking the bottom of the through-hole on the second surface side; a first wiring layer laminated on the first adhesion layer; and a second wiring layer laminated on the second adhesion layer, wherein in a case where a total area of the first wiring layer is set as A, and an area occupied by copper in the first wiring layer is set as B, a residual copper rate C of the first wiring layer is represented by C=B / A (%), C=70-100%, and a Young's modulus of a material of the first adhesion layer is 0.1-0.85 times a Young's modulus of a material of the first wiring layer.

Description

TECHNICAL FIELD

[0001] The present application relates to a wiring substrate. BACKGROUND

[0002] A wireless communication system that enables a high-function portable terminal such as a smartphone to be rapidly spread is supported by high functionality of an RF front-end module (RFFM). The RFFM is constituted by a filter / power amplifier (PA) / low noise amplifier (LNA) / RF switch. With integration of components, the circuit of the RFFM becomes complex, and the number of components tends to increase.

[0003] In particular, with miniaturization, thinness, and multifunctionalization of the RFFM, the number of components mounted on the RFFM increases, and in response to this, the demand for low-profile of the RFFM package increases. In order to achieve such low-profile of the RFFM package, it is known to adopt a thin multi-layer wiring substrate.

[0004] Conventionally, low-profile of the entire RFFM is widely achieved by a method of thinning the laminated resin of the thin multi-layer wiring substrate.

[0005] Here, as a thin multi-layer wiring substrate for mounting electronic components such as semiconductor chips, various shapes / structures of substrates have been proposed. For example, as shown in Patent Literature 1, a thin multi-layer wiring substrate is known that has a structure in which an inner layer wiring layer is centered and insulating layers are formed on both upper and lower sides of the inner layer wiring layer, and is connected to the inner layer wiring layer via via wirings formed on these insulating layers, respectively.

[0006] PRIOR ART DOCUMENTS

[0007] PATENT LITERATURE

[0008] Patent Literature 1: Japanese Patent Application Laid-Open No. 2011-134957 SUMMARY

[0009] PROBLEMS TO BE SOLVED BY THE INVENTION

[0010] In the thin multi-layer wiring substrate, there is a problem of how to ensure connection reliability. In particular, as the wiring substrate is thinned, warping of the substrate becomes more significant, and problems such as reduction in mounting yield and reduction in reliability occur.

[0011] The present application was made in view of the problem, and aims to provide a wiring substrate that, for example, can cope with low-profile of a high-function portable terminal, reduces warping of the substrate while being thin, and is excellent in connection reliability.

[0012] Means for solving the problem

[0013] To solve the above problem, a wiring substrate of a representative aspect of the present application has:

[0014] a core made of glass, which has a first surface, a second surface opposite to the first surface, and a through-hole passing through from the first surface to the second surface;

[0015] a first adhesion layer formed so as to adhere to the first surface and an inner wall of the through-hole and further plug a bottom of the second surface side of the through-hole;

[0016] a second adhesion layer adhering to the second surface and the first adhesion layer plugging the bottom of the second surface side of the through-hole;

[0017] a first wiring layer laminated on the first adhesion layer; and

[0018] a second wiring layer laminated on the second adhesion layer,

[0019] in a case where a total area of the first wiring layer is set as A and an area occupied by copper in the first wiring layer is set as B, a residual copper rate C of the first wiring layer is represented by C = B / A (%),

[0020] in a case where C = 70 to 100%, a Young's modulus of a material of the first adhesion layer is 0.1 to 0.85 times a Young's modulus of a material of the first wiring layer.

[0021] Effects of the Invention

[0022] According to the present application, it is possible to provide, for example, a wiring substrate which can cope with low-profile of high-function portable terminals, reduce warping of a substrate while being thin, and has excellent connection reliability.

[0023] The problem, configuration, and effect other than the above are made clear by the following embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 FIG. 1 is a cross-sectional view showing a capacitor included in an embodiment of the present application. Figure 1

[0025] Figure 2 FIG. 2 is a perspective view showing an inductor included in the embodiment of the present application. Figure 2

[0026] Figure 3 FIG. 3 is a circuit diagram showing a band-pass filter included in the embodiment of the present application. Figure 3 ​​​​​​

[0027] [ Figure 4 ] Figure 4 is a cross-sectional view showing a part of a wiring substrate having a band pass filter included in the present embodiment.

[0028] [ Figure 5 ] Figure 5 is a cross-sectional view showing one example of a wiring substrate related to the present embodiment.

[0029] [ Figure 6 ] Figure 6 is a cross-sectional view showing another example of a wiring substrate related to the present embodiment.

[0030] [ Figure 7 ] Figure 7 is a view showing a manufacturing process of a wiring substrate related to the present embodiment.

[0031] [ Figure 8 ] Figure 8 is a view showing a manufacturing process of a wiring substrate related to the present embodiment.

[0032] [ Figure 9 ] Figure 9 is a view showing a manufacturing process of a wiring substrate related to the present embodiment.

[0033] [ Figure 10 ] Figure 10 is a view showing a manufacturing process of a wiring substrate related to the present embodiment.

[0034] [ Figure 11 ] Figure 11 is a view showing a manufacturing process of a wiring substrate related to the present embodiment.

[0035] [ Figure 12 ] Figure 12 is a view showing a manufacturing process of a wiring substrate related to the present embodiment.

[0036] [ Figure 13 ] Figure 13 is a view showing a manufacturing process of a wiring substrate related to the present embodiment.

[0037] [ Figure 14 ] Figure 14 is a view showing a manufacturing process of a wiring substrate related to the present embodiment.

[0038] [ Figure 15 ] Figure 15 is a view showing a manufacturing process of a wiring substrate related to the present embodiment.

[0039] [ Figure 16 ] Figure 16 is a view showing a manufacturing process of a wiring substrate related to the present embodiment.

[0040] [ Figure 17 ] Figure 17 is a view showing a manufacturing process of a wiring substrate to which the present embodiment is applied.

[0041] [ Figure 18 ] Figure 18 is a view showing a manufacturing process of a wiring substrate to which the present embodiment is applied.

[0042] [ Figure 19 ] Figure 19 is a view showing a manufacturing process of a wiring substrate to which the present embodiment is applied.

[0043] [ Figure 20 ] Figure 20 is a view showing a manufacturing process of a wiring substrate to which the present embodiment is applied.

[0044] [ Figure 21 ] Figure 21 is a view showing a manufacturing process of a wiring substrate to which the present embodiment is applied. DETAILED DESCRIPTION

[0045] <EMBODIMENT>

[0046] Hereinafter, an embodiment of the present application will be described with reference to the drawings. Note that the embodiment described below is an example illustrating a device and a method for embodying the technical idea of the present application, and the technical idea of the present application is not limited to the contents described below in terms of the material, shape, structure, arrangement, and the like of the components. The technical idea of the present application can be changed in various ways within the technical scope defined in the claims.

[0047] Note that in this disclosure, "surface" refers not only to a surface of a plate-like member but also to an interface of a layer included in the plate-like member, which is substantially parallel to the surface of the plate-like member. In addition, "upper surface" and "lower surface" refer to surfaces shown on the upper side or the lower side in a drawing when the plate-like member or a layer included in the plate-like member is illustrated in the drawing.

[0048] In addition, "side surface" refers to a surface or a thickness portion of a layer included in the plate-like member. Furthermore, a part of a surface and a side surface are sometimes collectively referred to as an "end portion".

[0049] In addition, "upper side" refers to a direction of the vertically upper side when the plate-like member or the layer is horizontally placed. Furthermore, "upper side" and "lower side" opposite to each other are sometimes referred to as "Z-axis direction"; and a horizontal direction is sometimes referred to as "X-axis direction" or "Y-axis direction".

[0050] Further, "planar shape" and "plan view" mean the shape when a surface or a layer is viewed from above. Further, "cross-sectional shape" and "cross-sectional view" mean the shape when a plate-like member or a layer is cut in a certain direction and viewed from the horizontal direction.

[0051] Further, "central portion" means a portion other than the peripheral portion of a surface or a layer. Further, "central direction" means the direction from the peripheral portion of a surface or a layer toward the center of the planar shape of the surface or the layer.

[0052] "Residual film amount of the wiring layer" means the volume obtained by multiplying the pattern area of the wiring layer when the substrate is viewed from above by the film thickness of the wiring layer.

[0053] Further, "circuit element" means a passive element such as a resistor, a capacitor, an inductor, and a reactance, and preferably an element that becomes a constituent element of an LC circuit. The circuit element preferably serves as a component of an LC filter that constitutes a bandpass filter used for time division duplex communication (TDD) in a frequency band of at least 2 GHz or more within a multi-band communication. The LC filter can also be constituted as a low-pass filter, a high-pass filter, a diplexer, and the like; and a notch filter that removes noise of a specific frequency band.

[0054] In such a wiring substrate, a bandpass filter used for time division duplex communication (TDD) in a frequency band of at least 2 GHz or more within a multi-band communication is preferably constituted by an LC filter. The reactance element of the LC filter preferably has at least a part of its structure within the wiring substrate, and by mounting on the RF component wiring substrate other than the LC filter, a more compact wiring substrate can be achieved.

[0055] In the present embodiment, by embedding a circuit element in the wiring substrate, the region of the surface of the wiring substrate above the embedded circuit element can be used for mounting of other components, and thus a high-function and compact wiring substrate can be achieved.

[0056] Hereinafter, examples of a capacitor and an inductor as circuit elements that constitute an LC circuit will be described with respect to a substrate in which a glass plate is used as a core material, and a wiring layer and an insulating resin layer are formed on each of the two surfaces of the glass plate.

[0057] With respect to the capacitor, a structure in which a dielectric is sandwiched between two conductor plates is adopted. As an example of the capacitor, as shown in FIG. 1, a lower electrode 12 is laminated to form a conductor pattern on the upper side of a glass substrate not shown, or on an insulating resin layer 11 formed on the glass substrate, a dielectric layer 13 is laminated on the conductor pattern, and a conductor serving as an upper electrode 14 is further laminated thereon. The lower electrode 12 and the upper electrode 14 can also be a multilayer structure constituted by a seed layer and a conductive layer. Figure 1 ​

[0058] For the inductor, the same performance as the spiral coil can be built into a substrate having through-holes. In Figure 2 , a parallel flat glass plate having through-holes arranged in two rows is transparentized and illustrated. In Figure 2 , the wirings 21, 22 are formed in a manner that the opening portions of the through-holes adjacent to each other in the front and back surfaces of the glass plate are connected to each other, and a conductor layer is formed on the inner wall of the through-hole 23 that communicates the front and back surfaces of the glass plate, thereby forming a TGV.

[0059] Next, a band-pass filter (BPF) based on an LC circuit formed inside the substrate will be described. The basic circuit diagram of the BPF is shown in Figure 3 . Then, by appropriately setting the capacitance (hereinafter referred to as capacitance) of the capacitors and the inductance (hereinafter referred to as inductance) of the inductors in the circuit, only the frequency of the desired band can be passed, thereby exhibiting a band-pass effect of blocking the bands other than this.

[0060] Figure 4 A schematic diagram showing the state of the capacitors and inductors shown in the circuit diagram in which the Figure 3 are formed inside the wiring substrate is shown. The capacitors C1 to C3 as a whole are buried in the insulating resin layer 43 on the upper surface of the glass core 41, and in the case where connection to the electrodes outside the wiring substrate is desired, a via hole can be formed in the insulating resin layer 43, and connection is made via the conductor inside it.

[0061] As shown in Figure 4 , the inductors L1 to L3 can be connected to the TGV in the through-hole 23 formed inside the glass core 41 and the wirings 21, 22 on the front and back surfaces of the glass core 41, thereby making a solenoid coil. In Figure 4 , the details will be described later, and the symbols 42, 48 indicate the adhesion layers. The inductors L1 to L3 are mainly buried inside the glass core 41 and the insulating resin layer 43 on the front and back surfaces thereof, and as with the capacitors C1 to C3, conduction to the electrodes of the outermost layer of the wiring substrate can be made via the via hole inside the insulating resin layer 43. Note that the inductor L2 is a reactance element for an interference suppression adjustment circuit between band-pass filters.

[0062] <Example of Wiring Substrate>

[0063] Figure 5 is a cross-sectional view showing one example of the wiring substrate to which the present embodiment is applied.

[0064] The wiring substrate 30 of the present embodiment has a core material (also referred to as a glass core) 41 made of glass, which has a first surface 41a, a second surface 41b opposite to the first surface 41a, and a through-hole 44 that penetrates from the first surface 41a to the second surface 41b, a first adhesion layer 42 formed so as to adhere to the first surface 41a and the inner wall of the through-hole 44 and further plug the bottom of the second surface 41b side of the through-hole 44, a second adhesion layer 48 that adheres to the second surface 41b and the first adhesion layer 42 that plugs the bottom of the second surface 41b side of the through-hole 44, a first wiring layer 45 laminated on the first adhesion layer 42, and a second wiring layer 50 laminated on the second adhesion layer 48.

[0065] An insulating resin layer 43 is laminated on the first wiring layer 45 and the second wiring layer 50, and other wiring layers are formed thereon.

[0066] As described later, a dielectric layer 51, a seed layer 52, and an upper electrode 54 are formed on the first wiring layer 45, whereby a capacitor as shown in FIG. 6 is formed. Figure 1 In addition, an inductor as shown in FIG. 7 is formed by the first wiring layer 45, a conductor layer in a through via 61 that penetrates the insulating resin layer 43, and a wiring pattern 62. Although not particularly described, the capacitor and the inductor can be formed on either of the first wiring layer 45 and the second wiring layer 50. Figure 2 In addition, an inductor as shown in FIG. 7 is formed by the first wiring layer 45, a conductor layer in a through via 61 that penetrates the insulating resin layer 43, and a wiring pattern 62. Although not particularly described, the capacitor and the inductor can be formed on either of the first wiring layer 45 and the second wiring layer 50.

[0067] Figure 6 is a cross-sectional view showing another example of the wiring substrate 30 to which the present embodiment is applied. As shown in Figure 6 , a conductive member on one surface of the glass core 41 is connected to a high-frequency component 60 mounted on the wiring substrate 30, and a module substrate is formed by molding with a molding resin 58. At this time, a conductive member on the other surface of the glass core 41 can be connected to a mother substrate (not shown).

[0068] <Substrate manufacturing process>

[0069] Next, one example of a wiring substrate manufacturing process using a glass substrate will be described with reference to Figures 7 to 21 .

[0070] (Circuit design)

[0071] First, in order to perform circuit design, necessary capacitance and inductance are calculated using simulation software according to the frequency band of a passing or blocked electric wave. For example, for a frequency band of 3400 MHz or more and 3600 MHz or less, a capacitor of 0.5 pF or more and 1.0 pF or less and an inductor of 0.5 nH or more and 1.0 nH or less are necessary. Figure 3In the circuit configuration shown, the specifications of the elements used to achieve the desired characteristics are shown in Table 1, Table 2. Here, regarding the inductors Ll and L3, since the inductance is very small, it is not necessary to be in the shape of a coil, and the self-induction coefficient of one wire is sufficient, so the dimensions of the wire are shown in the table.

[0072] [Table 1]

[0073] C1 C2 C3 Inductance 5.37 pF 53.59 fF 35.07 pF Dielectric body SiN SiN SiN Relative dielectric constant 6.3 6.3 6.3 Dielectric body thickness 200 nm 200 nm 200 nm One side length 138.7 μm 13.9 μm 354.5 μm

[0074] [Table 2]

[0075] L1 L2 L3 Capacitance 385.4 pH 38.62 nH 59.01 pH Winding number 11 Coil width 1.6 mm Coil length 1.5 mm Coil thickness 0.3 mm Wiring length 1.33 mm 0.2 mm Wiring width 0.1 mm 0.1 mm Wiring thickness 15 μm 15 μm

[0076] For the BPF for the frequency band of 2499 MHz or more and 2690 MHz or less, the capacitance and inductance are also calculated by the same procedure to perform the necessary circuit design (numerical values are omitted).

[0077] (Joining of the glass core and the support, and formation of the seed layer in the through-hole)

[0078] According to the above circuit design, the necessary wiring substrate is fabricated. First, a glass core 41 of low expansion (thickness 300 μm, CTE: 3.5 ppm / K) is prepared, and then a through-hole 44 having an opening diameter of 80 μm to 100 μm is formed in the glass core 41. At the time of formation, as a first stage, a fragile portion is formed on the glass irradiated with a UV laser at a position where the through-hole 44 is desired to be formed; as a second stage, the entire glass plate is etched with a fluoric acid aqueous solution.

[0079] By this, the fragile portion is selectively etched, and the through-hole 44 of high precision is rapidly formed. Compared to the case where a glass epoxy substrate is used, the through-hole 44 having a higher-precision inner diameter and an inner peripheral surface having no unevenness can be formed.

[0080] Next, a support 47 having an adhesive layer 46 is attached. The support 47 is, for example, a substrate composed of a material having the property of transmitting light (transparency). The wavelength range of light transmitted by the support 47 can be, for example, 300 nm or more and 2000 nm or less, or 300 nm or more and 1100 nm or less. The support 47 can also have the property of transmitting a specific wavelength such as laser light.

[0081] The support 47 is preferably, for example, a glass substrate. As the glass, for example, quartz glass, borosilicate glass, non-alkali glass, soda glass, sapphire glass, or the like can be used. By setting the maximum height roughness Rz of the main surface 47a of the support 47 to 0.01 μm or more, the cost of the support 47 can be suppressed. By setting the maximum height roughness Rz of the main surface 47a of the support 47 to 5 μm or less, disconnection and short circuit of the first wiring layer 45 caused by the unevenness of the main surface 47a can be suppressed.

[0082] The adhesive layer 46 is a layer for adhering the support 47 and the glass core 41 to each other, and includes a peeling layer and a protective layer. The peeling layer is provided on the main surface of the support 47, and contains a resin that can be decomposed by irradiation of light. For example, in the case where the peeling layer is peeled using laser, as the resin included in the peeling layer, a resin that can be thermally decomposed by irradiation of laser of a predetermined wavelength can be used.

[0083] As the resin included in the peeling layer, for example, one of an epoxy resin, a urethane resin, a silicone resin, a polyester resin, an oxetane resin, and a maleimide resin, or a resin obtained by mixing two or more of these resins can be used. The thickness of the adhesive layer 46 is, for example, 20 μm or more and 100 μm or less.

[0084] (Formation of the first adhesion layer and the first wiring layer)

[0085] Further, as a part of the first adhesion layer 42 (seed layer) of the inner wall of the through-hole 44 of the glass core 41 and the lower side of the wiring layer, a two-layer film of a Ti film and a Cu film is formed in this order on the entire surface of the glass core 41 by sputtering, and the conductive property of the glass surface is obtained, thereby obtaining a configuration of Figure 7 .

[0086] Since the lower side opening of the through-hole 44 is shielded by the support 47, an adhesion layer film (a part of the first adhesion layer 42) is formed on the first surface 41a of the glass core 41, the inner wall of the through-hole 44, and the support 47 that plugs the lower side opening of the through-hole 44 by sputtering. The thickness of the film is set to 50 nm for the Ti film and 300 nm for the Cu film. As the target material for sputtering, Ni, Cr, or the like can be used. This is preferably selected by taking into consideration the adhesion to the substrate, film stress, process resistance, reliability, and the like.

[0087] Next, in order to compensate for the thin part of the sputtered film of the inner wall of the through-hole 44 and adjust the warpage of the substrate, electrolyticless nickel plating is performed, and an adhesion layer (the remaining part of the first adhesion layer 42) composed of Ti / Cu / Ni is formed. The entire front and back surfaces of the glass core 41 and the inside of the through-hole 44 are processed, and the plating thickness is set to 0.2 μm. According to the above-described manner, the first adhesion layer 42 is formed.

[0088] like Figure 8 As shown, the first bonding layer 42 is used as a seed layer, and the first wiring layer 45, including the wiring of the inductor, the lower electrode of the capacitor, and the pads for external connections, is formed using a semi-additive method. To form a conductor pattern on the first wiring layer 45, such as... Figure 9 As shown, a dry film resist layer 53 is formed by laminating (for example) Hitachi Chemical Co., Ltd., trade name RY-3525 (thickness 25μm) on the glass core 41.

[0089] The dry film resist layer 53 can be formed by coating a liquid resist. Then, the dry film resist layer 53 is exposed and developed using photolithography through a mask with a conductor pattern, i.e., a mask used to form a wiring pattern, thereby forming a wiring pattern (opening) on ​​the resist layer.

[0090] Next, copper is deposited in the opening using electroplating to form a first wiring layer 45 as a conductive component with a thickness of 15 μm. During this stage, copper is also deposited on the inner wall of the through-hole 44 of the glass core 41, forming part of the first wiring layer 45.

[0091] Next, the dry film resist is stripped. During this stage, as... Figure 10 As shown, the surface of the glass core 41 is partially covered by a first sealing layer 42 containing Ti / Cu / Ni and partially covered by a first wiring layer 45 of Cu. Figure 10 In the process, the lower electrode of the capacitor is formed at a predetermined position in the conductor pattern.

[0092] Therefore, by using a seed layer made of a material different from Cu, which serves as the main conductive layer, and forming a layer composed of Ti and Ni, the stress applied to the glass core 41 can be easily adjusted, thereby facilitating warpage adjustment. Furthermore, when forming the aforementioned dry film resist, warpage can be adjusted in greater detail by forming Cu-containing dummy wirings at desired locations.

[0093] like Figure 11 As shown, firstly, a SiN film with a thickness of 200 nm to 400 nm is formed on the entire surface of the capacitor side of the glass core 41 using the CVD film-forming method, thereby forming the dielectric layer 51 of the capacitor.

[0094] Furthermore, such as Figure 12 As shown, the seed layer 52 used in forming the upper electrode of the capacitor is formed by sputtering film deposition, with Ti film and Cu film of 50 nm and 300 nm respectively, sequentially deposited on the entire dielectric layer 51.

[0095] Next, as Figure 13As shown, in order to form the upper electrode of the capacitor, only the portion forming the upper electrode is made to be exposed from the dry film resist layer 53 in photolithography. Next, as shown in FIG. 6B, the upper electrode 54 having a thickness of 9 to 10 μm is formed by electroplating copper. Then, the dry film resist layer 53 is removed. At this time, in addition to the capacitor, a SiN layer or the like can also be laminated. Figure 14 As shown, the upper electrode 54 having a thickness of 9 to 10 μm is formed by electroplating copper. Then, the dry film resist layer 53 is removed. At this time, in addition to the capacitor, a SiN layer or the like can also be laminated.

[0096] Therefore, in order to remove the excess adhesion layer, plating seed layer, and the like, first, the upper electrode 54 of the capacitor is protected with a dry film resist (not shown) using photolithography.

[0097] Next, in order to remove the excess portion of the sputtered copper layer at the time of forming the upper electrode 54 of the capacitor, the substrate is processed using a wet etching method; in order to remove the excess portions of the Ti layer and SiN layer, the substrate is processed using a dry etching method.

[0098] More specifically, first, the sputtered Cu layer located at the uppermost portion of the excess portion is removed using an etching solution. Next, the sputtered Ti layer and CVD-deposited SiN layer thereunder are removed using dry etching. Then, the dry film resist protecting the upper electrode 54 of the capacitor is peeled off and removed.

[0099] Next, in order to remove the seed layer of the lower electrode of the capacitor and other conductive layers formed on the surface of the glass core 41, the substrate is processed using a wet etching process in the order of Ni, Ti. As a result, the sputtered Cu layer thereunder is also removed at the same time. On the other hand, as for the Cu layer forming the wiring, capacitor electrode, and the like, although it is somewhat dissolved in the etching solution, since it has a large thickness, it is not completely removed. Then, the sputtered Ti layer is removed using etching.

[0100] Figure 15 The configuration of the process up to this point is shown. At this stage, the glass core 41 is exposed at portions where no wiring, electrode, dummy pattern, and the like are formed. As a result, as shown in FIG. 7, the capacitor composed of the first wiring layer 45, dielectric layer 51, seed layer 52, and upper electrode 54 is formed on the surface of the glass core 41 (refer to FIG. 7). Figure 1 In addition, a portion of the continuous wiring forming the inductor can be formed and connected to the conductor layer TGV.

[0101] Next, an insulating resin (trade name "ABF-GX-T31R") manufactured by Ajinomoto Fine-Techno Co., Inc. is attached to the upper surface of the glass core 41, thereby forming an insulating resin layer (resin build-up layer) 43. As for the processing, the insulating resin is enclosed without a gap inside the through-hole 44 of the glass core 41 using a vacuum press lamination device. The thickness of the insulating resin layer 43 is set to about 35 μm so as to reliably bury the upper electrode 54 of the capacitor.

[0102] (Separation of the support)

[0103] Next, as shown in FIG. 6, laser light L is irradiated toward the adhesive layer 46 via the support 47 to separate the support 47. The laser light L can be irradiated to the entire support 47 or to a desired position of the support 47. In the manufacture of the wiring substrate, the laser light L is irradiated to the entire support 47 while being made to go straight back and forth from the viewpoint of reliably decomposing the resin within the adhesive layer 46. Figure 16

[0104] The laser light L can have a wavelength of 300 nm or more and 2000 nm or less, preferably a wavelength of 300 nm or more and 1500 nm or less, and more preferably a wavelength of 300 nm or more and 1100 nm or less, for example. As one example of a device that emits the laser light L, a YAG laser device that emits light of a wavelength of 1064 nm, a 2nd harmonic YAG laser device that emits light of a wavelength of 532 nm, or a semiconductor laser device that emits light of a wavelength of 780 nm or more and 1300 nm or less, or the like can be given.

[0105] The support 47 has transparency and transmits the laser light L. Therefore, the energy of the laser light L that has passed through the support 47 is absorbed by the adhesive layer 46. The energy of the laser light L that has been absorbed is converted into heat energy within the adhesive layer 46. By this heat energy, the resin of the adhesive layer 46 reaches a thermal decomposition temperature and is thermally decomposed. Thus, the force with which the adhesive layer 46 adheres the support 47 and the glass core 41 is weakened.

[0106] (Formation of the 2nd adhesion layer and the 2nd wiring layer)

[0107] Next, as shown in FIG. 6, laser light L is irradiated toward the adhesive layer 46 via the support 47 to separate the support 47. The laser light L can be irradiated to the entire support 47 or to a desired position of the support 47. In the manufacture of the wiring substrate, the laser light L is irradiated to the entire support 47 while being made to go straight back and forth from the viewpoint of reliably decomposing the resin within the adhesive layer 46. Figure 17

[0108] As shown in FIG. 7, the 2nd adhesion layer 48 is used as a seed layer, and the 2nd wiring layer 50, such as the wiring of the inductor, the lower electrode of the capacitor, the pad for external connection, and the like, is formed using a half-addition method. Further, in order to form a conductor pattern on the 2nd wiring layer 50, a dry film resist layer 53 is formed by laminating, for example, RY-3525 (thickness: 25 μm) manufactured by Hitachi Chemical Co., Ltd. on the lower surface of the glass core 41. Figure 18

[0109] ​​​The dry film resist layer 53 can be formed by coating a liquid resist. Then, the dry film resist layer 53 is exposed and developed using photolithography through a mask with a conductor pattern, i.e., a mask used to form a wiring pattern, thereby forming a wiring pattern (opening) on ​​the dry film resist layer 53.

[0110] Next, as Figure 19 As shown, copper is deposited at the opening using electroplating to form a second wiring layer 50, which serves as a conductive component, with a thickness of 15 μm. During this stage, copper plating is also deposited at the bottom of the through-hole 44 in the glass core 41 (the portion blocked by the first sealing layer 42).

[0111] Next, as Figure 20 As shown, wet etching is used to remove excess wiring portions from the substrate; dry etching is used to remove excess Ti layers from the substrate.

[0112] More specifically, firstly, the sputtered Cu layer on top of the excess portion is removed using an etchant. Next, the underlying sputtered Ti layer is removed using dry etching. Then, the dry film resist layer 53 protecting the second wiring layer 50 is stripped away.

[0113] Next, as Figure 21 As shown, an insulating resin (trade name "ABF-GX-T31R") manufactured by Ajinomoto Fine-Techno Co., Inc. is adhered to the underside of the glass core 41 to form an insulating resin layer (resin construction layer) 43. Regarding processing, the insulating resin is seamlessly embedded into the wiring pattern of the second wiring layer 50 using a vacuum pressing lamination apparatus. The thickness of the insulating resin layer 43 is set to approximately 35 μm to reliably bury the wiring pattern all the way up to the second wiring layer 50.

[0114] Furthermore, through laser processing, the insulating resin layer 43 is made to penetrate the desired conductive location, such as... Figure 5 As shown, a through hole 56 is formed to reach the wiring layer of the glass core. The diameter of the through hole 56 is preferably about 60 μm.

[0115] Although not illustrated, the insulating resin layers 43 on both sides of the glass core 41 are treated with an alkaline surface roughening solution to adjust the arithmetic surface roughness Ra = 60 nm. This is to improve the adhesion of the seed layer in subsequent processes.

[0116] Next, electroless copper plating is performed on the insulating resin layer 43 on both sides of the glass core 41 to form a conductive seed layer 57. Its thickness is preferably set to 0.6 μm. Through this process, a conductive seed layer 57 is formed not only on the front and back sides, but also on the inner wall of the hole previously formed by laser processing.

[0117] Although not shown, a dry film resist DR is attached to both surfaces of the substrate, and an opening portion is provided in a portion where a wiring is desired to be provided by using a photolithography method. Subsequently, plating is performed on the substrate, and a wiring having a thickness of 15 μm is formed. In addition, in this plating process, the inside of the through hole 56 in the insulating resin layer 43 is also filled with copper, and thus conduction to the second wiring layer 50 on the surface of the glass core 41 can be ensured.

[0118] Then, the unnecessary conductive seed layer is removed by etching. As described above, a basic wiring substrate 30 including a built-in element for an LC circuit as shown in FIG. 6 is completed. Note that, in the drawing, with respect to the built-up wirings on the lower side of the glass core 41, it is assumed that the capacitor and the inductor built in the wiring substrate are grounded as shown by the copper layer, but this is not necessarily required in the actual wiring substrate, and it is sufficient if the predetermined capacitor and inductor are grounded at the time of completion of the wiring substrate. Figure 5

[0119] Then, as necessary, the above process can be repeated to stack the insulating layer and the conductor wiring layer, and to mount electronic components. In addition, a planar (e.g., spiral) reactance element (coil) can be formed on the surface of the glass core 41 or the insulating resin layer 43. In addition, a through hole having electrical neutrality can be arranged between the reactance elements to reduce loss due to mutual induction, and a capacitor can be provided in the through hole.

[0120] Here, in a case where the total area of the first wiring layer 45 is set to A and the area occupied by copper in the first wiring layer 45 is set to B, the residual copper rate C of the first wiring layer 45 is represented by C = B / A (%), and here C = 70 to 100 %. Note that, in a case where there is a dummy wiring in the first wiring layer 45, C = 75 to 85 % is often considered in view of the dummy wiring. The influence of the first wiring layer 45 on the warpage of the wiring substrate 30 having a thin glass core is mainly generated by the residual copper rate C of the first wiring layer 45.

[0121] In the actual wiring substrate design, the residual copper rate has the greatest influence on the warpage of the substrate. Therefore, in order to make the residual copper rates of the front and back surfaces of the substrate not differ greatly, a dummy pattern or the like is formed, for example, in such a manner that the difference between the residual copper rates of the front and back surfaces is within 10 %. If this adjustment conforms to the design, the warpage of the substrate is not so large, but sometimes it is desired to further suppress the warpage of the substrate.

[0122] In this case, the present embodiment can be applied to the fine adjustment of the warpage.

[0123] ​As an example, by making the Young's modulus of the material of the first adhesion layer 42 (Ti = 106 GPa, Ni = 199.5 GPa) lower than the Young's modulus of the material of the first wiring layer 45 (Cu = 129.8 GPa), the rigidity of the first adhesion layer 42 is relatively increased, and the warpage of the wiring substrate 30 can be suppressed. However, when the Young's modulus of the first adhesion layer 42 is too low, cracks and the like can occur due to embrittlement.

[0124] Therefore, in the present embodiment, the Young's modulus of the material of the first adhesion layer 42 is set to 0.1 to 0.85 times the Young's modulus of the material of the first wiring layer 45. In this way, by setting the optimal Young's modulus, the warpage of the wiring substrate 30 can be effectively suppressed. The same adjustment is preferably performed in the second wiring layer 50 as well.

[0125] In addition, by adjusting the film thickness and the film thickness ratio of the first adhesion layer 42 and the first wiring layer 45, the film stress applied to the glass core 41 can be adjusted in more detail, and the warpage of the wiring substrate 30 can be adjusted.

[0126] In particular, when a desired wiring pattern is formed on the front and back surfaces of the glass core 41, the pattern and the film thickness of each layer are generally different, and thus become a main cause of warpage. According to the present embodiment, by making the configurations of the first adhesion layer 42 and the first wiring layer 45 different, the total film stress applied to the glass core 41 can be adjusted, and the warpage can be adjusted. Specifically, the number of films of the first adhesion layer 42 can be changed, and the film thickness of each layer of the first adhesion layer 42 can be changed, and the like.

[0127] Explanation of symbols

[0128] 11: Insulating resin layer, 12: Lower electrode of capacitor, 13: Dielectric layer of capacitor, 14: Upper electrode of capacitor, 21 / 22: Wires, 23: Through-hole, 30: Wiring substrate, 41: Glass core, 42: First adhesion layer, 43: Insulating resin layer, 44: Through-hole, 45: First wiring layer, 46: Adhesive layer, 47: Support, 48: Second adhesion layer, 50: Second wiring layer, 51: Dielectric layer, 52: Seed layer, 53: Dry film resist layer, 54: Upper electrode of capacitor, 56: Through-hole, 57: Conductive seed layer, 58: Mold resin, 60: High-frequency component.

Claims

1. A wiring substrate, characterized in that, have: A glass core material having a first surface, a second surface opposite to the first surface, and a through cavity extending from the first surface to the second surface; The first sealing layer is formed in such a way that it is sealed to the inner wall of the first surface and the through hole, and further blocks the bottom of the second surface side of the through hole; The second sealing layer is sealed to the bottom of the first sealing layer on the second surface and the side of the second surface that blocks the through hole; The first wiring layer is stacked on the first sealing layer; as well as A second wiring layer, which is stacked on top of the second sealing layer. With the total area of ​​the first wiring layer set as A and the area occupied by copper in the first wiring layer set as B, the residual copper rate C of the first wiring layer is represented by C = B / A (%). When C = 70-100%, the Young's modulus of the material of the first sealing layer is set to 0.1-0.85 times the Young's modulus of the material of the first wiring layer.

2. The wiring substrate according to claim 1, characterized in that, The first sealing layer comprises at least one of Ni, Ti, and Cr, and the first wiring layer comprises Cu.

3. The wiring substrate according to claim 1 or 2, characterized in that, A portion of the first sealing layer and the first wiring layer are formed by electroless plating.

4. The wiring substrate according to any one of claims 1 to 3, characterized in that, The first wiring layer has dummy wiring.

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