Semiconductor package substrate using dielectric racks to separate interconnect units

Abstract

The invention discloses a semiconductor package substrate for separating interconnection units by utilizing a dielectric frame, which comprises a crack suppression dielectric frame and a plurality of interconnection units, and each interconnection unit comprises a conductive column and an interface dielectric layer. The interconnection units are respectively formed in independent compartments defined by the crack inhibition dielectric frame. The interface dielectric layer laterally covers and surrounds the sidewall of the conductive pillar. Structural warping may be suppressed during coating of the interfacial dielectric layer by using a crack suppressing dielectric shelf instead of an existing metal shelf.

Description

Technical Field

[0001] The invention relates to a semiconductor package substrate, in particular to a semiconductor package substrate which utilizes a dielectric frame to separate interconnection units. Background Art

[0002] High-performance microprocessors and application-specific integrated circuits (ASICs) require high-performance and high-reliability substrates for signal interconnection. However, in existing resin laminate substrates, the electroplated copper layer is easily peeled off under stringent operating requirements, making such substrates unreliable in practical applications. In specific applications, ceramic materials (such as alumina or aluminum nitride) are favored due to their excellent electrical insulation, strong mechanical strength, low coefficient of thermal expansion (CTE) and effective thermal conductivity. Therefore, multilayer ceramic substrates, such as HTCC (high temperature co-fired ceramics) or LTCC (low temperature co-fired ceramics), have been developed to meet the needs of specific applications.

[0003] In addition to the above-mentioned resin laminate substrates and multilayer ceramic substrates, copper lead frame substrates have become another popular choice. They have obvious advantages such as high thermal conductivity, excellent electrical properties and simple manufacturing processes. However, further improvements are still needed to solve problems such as warping, cracking and other related issues. Such improvements are crucial to ensure the continued advancement and reliability of high-performance semiconductor devices. Summary of the invention

[0004] An object of the present invention is to provide an innovative semiconductor package substrate, which is a semiconductor package substrate that uses a dielectric frame to separate interconnection units, and has a crack-suppressing dielectric frame that defines a plurality of compartments, rather than a metal frame in an existing copper lead frame substrate, each compartment accommodating an interconnection unit. When manufacturing the semiconductor package substrate, compared with the existing metal frame, the crack-suppressing dielectric frame can reduce the warping caused by the subsequent coating of the interface dielectric layer, thereby improving the reliability of the substrate.

[0005] In accordance with the above and other objects, the present invention provides a semiconductor package substrate using a dielectric frame to separate interconnection units, comprising a crack suppression dielectric frame and a plurality of interconnection units, each interconnection unit being disposed in a corresponding one of the separated compartments defined by the crack suppression dielectric frame. Each interconnection unit comprises a conductive post and an interface dielectric layer. The crack suppression dielectric frame has a plurality of inner edges, each of which laterally surrounds a corresponding interconnection unit. The conductive posts are disposed in the compartments and separated from each other by the interface dielectric layer. The interface dielectric layer laterally covers and surrounds the sidewalls of the conductive posts and covers the inner edge of the crack suppression dielectric frame.

[0006] The semiconductor package substrate may further include a thermal pad, and the interface dielectric layer laterally covers and surrounds the sidewall of the thermal pad. Accordingly, the present invention can provide a group, wherein the semiconductor element overlaps the thermal pad of the semiconductor package substrate and is thermally connected to the thermal pad, and is electrically connected to the conductive pillar of the semiconductor package substrate through a wire.

[0007] The above and other features and advantages of the present invention will be further described and made clearer through the following detailed description of the preferred embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The detailed description of the preferred embodiments of the present invention will be more clearly understood in conjunction with the following drawings, in which:

[0009] Figure 1 A cross-sectional view of the conductive and heat conductive plate in the first embodiment of the present invention;

[0010] Figure 2 and Figure 3 They are respectively Figure 1 The structure further provides a cross-sectional view and a top perspective view of the crack-suppressing dielectric frame;

[0011] Figure 4 and Figure 5 They are respectively Figure 2 and Figure 3 The structure further provides a cross-sectional view and a top perspective view of the interface dielectric layer;

[0012] Figure 6 and Figure 7 They are respectively Figure 4 and Figure 5 The structure is further formed with conductive pillars and thermal pads to complete the cross-sectional view and bottom stereoscopic view of the semiconductor package substrate fabrication;

[0013] Figure 8 In the first embodiment of the present invention Figure 6 The structure further provides a cross-sectional view of the semiconductor element;

[0014] Fig. 9 In the first embodiment of the present invention Figure 8 The structure is further provided with a cross-sectional view of the encapsulation material;

[0015] Fig.10 and Fig.11 Respectively Fig. 9 The structure is divided into a cross-sectional view and a top perspective view of the individual units;

[0016] Fig.12 A cross-sectional view of a separate semiconductor assembly;

[0017] Fig.13is a cross-sectional view of another semiconductor assembly in the first embodiment of the present invention;

[0018] Fig.14 is a cross-sectional view of a semiconductor package substrate in a second embodiment of the present invention;

[0019] Fig.15 In the second embodiment of the present invention Fig.14 The structure further provides a cross-sectional view of the semiconductor element and packaging material;

[0020] Fig.16 In the second embodiment of the present invention, from Fig.15 A cross-sectional view of a semiconductor assembly with its structure isolated;

[0021] Fig.17 is a cross-sectional view of a semiconductor package substrate in a third embodiment of the present invention;

[0022] Fig.18 In the third embodiment of the present invention Fig.17 The structure further provides a cross-sectional view of the semiconductor element and packaging material;

[0023] Fig.19 In the third embodiment of the present invention, Fig.18 A cross-sectional view of a semiconductor assembly from which the assembly has not been separated;

[0024] Fig. 20 and Fig.21 They are respectively a cross-sectional view and a top stereoscopic view of a patterned conductive layer formed on a sacrificial carrier in a fourth embodiment of the present invention;

[0025] Fig. 22 In the fourth embodiment of the present invention Fig. 20 The structure further provides a cross-sectional view of the array of projections;

[0026] Fig.23 and Fig.24 They are respectively Fig. 22 The structure further provides a cross-sectional view and a top perspective view of the crack-suppressing dielectric frame;

[0027] Fig.25 and Fig.26 They are respectively Fig.23 and Fig.24 The structure further provides a cross-sectional view and a top perspective view of the interface dielectric layer;

[0028] Fig. 27 and Fig.28 They are respectively Fig.25 and Fig.26A cross-sectional view and bottom perspective view of the structure removing the sacrificial carrier to complete the production of the semiconductor package substrate;

[0029] Fig.29 is a cross-sectional view of a semiconductor package substrate combined with a sacrificial carrier in a fifth embodiment of the present invention;

[0030] Fig.30 In the fifth embodiment of the present invention Fig.29 A cross-sectional view of a structure removing a sacrificial carrier to complete the fabrication of a semiconductor package substrate;

[0031] Fig.31 is a cross-sectional view of a semiconductor package substrate in a sixth embodiment of the present invention;

[0032] Fig.32 In the sixth embodiment of the present invention Fig.31 The structure further provides a cross-sectional view of the semiconductor element and packaging material;

[0033] Fig.33 In the sixth embodiment of the present invention, Fig.32 A cross-sectional view of a semiconductor assembly with its structure isolated;

[0034] Fig.34 is a cross-sectional view of a semiconductor package substrate combined with a sacrificial carrier in a seventh embodiment of the present invention;

[0035] Fig.35 In the seventh embodiment of the present invention Fig.34 A cross-sectional view of a structure removing a sacrificial carrier to complete the fabrication of a semiconductor package substrate;

[0036] Fig.36 is a cross-sectional view of another aspect of a semiconductor package substrate in the seventh embodiment of the present invention;

[0037] Fig.37 FIG. 4 is a cross-sectional view of another semiconductor package substrate in the seventh embodiment of the present invention.

[0038] Explanation of reference numerals: 10 - conductive and heat conductive plate; 11 - convex portion; 13 - base; 14 - sacrificial carrier; 15 - patterned conductive layer; 20 - compartment; 21 - crack suppression dielectric frame; 21' - crack suppression dielectric subframe; 23 - interface dielectric layer; 25 - external dielectric layer; 31 - semiconductor element; 41 - wire; 51 - packaging material; 71 - first interconnection component; 72 - second interconnection component; 100 - semiconductor package substrate; 101 - semiconductor assembly; 102 - semiconductor assembly; 111 - conductive column; 113 - Thermal pad; 151-circuit portion; 153-frame portion; 200-semiconductor package substrate; 201-semiconductor assembly; 300-semiconductor package substrate; 301-semiconductor assembly; 400-semiconductor package substrate; 500-semiconductor package substrate; 600-semiconductor package substrate; 601-semiconductor assembly; 700-semiconductor package substrate; 700A-semiconductor package substrate; 700B-semiconductor package substrate; 1131-seat portion; 1133-fin portion; A-interconnect unit; C-recess; L-along the cutting line. DETAILED DESCRIPTION

[0039] Hereinafter, embodiments will be provided to explain the implementation of the present invention in detail. The advantages and effects of the present invention will be more prominent through the following description of the present invention. The attached drawings are simplified and used as examples. The number, shape and size of components shown in the drawings can be modified according to actual conditions, and the configuration of components may be more complicated. Other practices or applications can also be carried out in the present invention, and various adjustments and changes can be made based on various concepts and applications without departing from the spirit of the present invention.

[0040] [Example 1]

[0041] Figure 1-Figure 9 Schematic diagram of a method for manufacturing an un-isolated assembly in a first embodiment of the present invention, wherein each semiconductor element is electrically connected to a corresponding one of interconnection units of a semiconductor package substrate and the interconnection units are separated from each other by a crack suppression dielectric frame of the semiconductor package substrate.

[0042] Figure 1 1 is a cross-sectional view of an electrically conductive and thermally conductive plate 10 having an array of protrusions 11 formed thereon, the protrusions 11 being formed by, for example, single-side etching or plating and protruding from a base 13. The electrically conductive and thermally conductive plate 10 may have a thickness ranging from, for example, 0.15 mm to 0.3 mm (i.e., the combined thickness of the protrusions 11 and the base 13), and is typically made of copper, aluminum, alloy 42, iron, nickel, silver, gold, combinations thereof, alloys thereof, or any other suitable metal. In this embodiment, the electrically conductive and thermally conductive plate 10 is made of 0.25 mm thick copper, and the thickness of the base 13 is shown to be 50 microns.

[0043] Figure 2 and Figure 31 and 2 are a cross-sectional view and a top perspective view respectively showing a crack suppression dielectric frame 21. The crack suppression dielectric frame 21 may have a modulus of elasticity of less than 50 GPa and is placed and attached to the base 13 from above to define a plurality of independent compartments 20. The compartments 20 may be arranged in an NxM array, such as a 2x2 array as shown in this embodiment, and the protrusions 11 are present in the same number and arrangement in each compartment 20. Preferably, the crack suppression dielectric frame 21 includes a reinforcement to enhance the function of suppressing crack propagation through the crack suppression dielectric frame 21. For example, the crack suppression dielectric frame 21 may be made of an organic material (e.g., an epoxy-based material) with a glass reinforcement (e.g., fiberglass). In this illustration, the top surface of the crack suppression dielectric frame 21 is substantially coplanar with the top side of the protrusion 11.

[0044] Figure 4 and Figure 5 2 are a cross-sectional view and a top perspective view respectively provided with an interface dielectric layer 23. The interface dielectric layer 23 fills the remaining space in the compartment 20 to cover the sidewalls of the protrusion 11 and the top surface of the base 13 and the inner edge of the crack suppression dielectric frame 21. By replacing the metal frame currently used with the crack suppression dielectric frame 21 having an elastic modulus of less than 50 GPa, the structure warping caused by the coating of the interface dielectric layer 23 can be prevented. In some examples, the interface dielectric layer 23 may have an elastic modulus lower than that of the crack suppression dielectric frame 21 to absorb stress and thereby further reduce warping. In addition, the interface dielectric layer 23 may contain an electrically insulating filler with a coefficient of thermal expansion (CTE) of less than 20 ppm, which is dispersed in an organic material (e.g., an epoxy-based material) to slow down the internal expansion and contraction of the interface dielectric layer 23 during thermal cycles. In this illustration, the top surface of the interface dielectric layer 23 is substantially coplanar with the top side of the protrusion 11 and the top surface of the crack suppression dielectric frame 21.

[0045] Figure 6 and Figure 7 The figures are a cross-sectional view and a bottom stereogram respectively showing a conductive column 111 and an optional thermal pad 113 formed thereon. The base 13 of the conductive and thermally conductive plate 10 is patterned by, for example, etching, and selected portions of the base 13 are retained, each of which is integrally formed with the corresponding protrusion 11, thereby forming a conductive column 111 for vertical electrical connection and an optional thermal pad 113 for component placement. Metal patterning techniques include wet etching with an etching mask (not shown) thereon, electrochemical etching, laser-assisted etching, and combinations thereof. The conductive column 111 and the thermal pad 113 are separated from each other by the interface dielectric layer 23 and each has an upper portion laterally covered and surrounded by the interface dielectric layer 23 and a lower portion laterally extending below the bottom surface of the interface dielectric layer 23.

[0046] Thus, a semiconductor package substrate 100 is completed, which includes a plurality of interconnection units A and a crack suppression dielectric frame 21. Each interconnection unit A is disposed in a corresponding one of the independent compartments 20 defined by the crack suppression dielectric frame 21 and includes a conductive column 111, a thermal pad 113 and an interface dielectric layer 23.

[0047] Figure 8 To provide a semiconductor element 31 attached to Figure 6 The cross-sectional view of the semiconductor package substrate 100 is shown. Each semiconductor element 31 (shown as a chip) is placed from above and overlapped on the corresponding thermal pad 113 through a thermal conductive adhesive, and is electrically coupled to the corresponding conductive pillar 111 through a wire 41.

[0048] Fig. 9 The cross-sectional view is optionally provided with a sealing material 51. The sealing material 51 encapsulates the semiconductor element 31 and the wire 41 and covers the conductive pillar 111, the thermal pad 13, the crack suppression dielectric frame 21 and the interface dielectric layer 23 from above, and extends laterally to the outer periphery of the crack suppression dielectric frame 21.

[0049] At this stage, the unsingulated assembly is completed and includes the semiconductor package substrate 100 , the semiconductor element 31 electrically connected to the semiconductor package substrate 100 via the wire 41 , and the packaging material 51 covering the semiconductor element 31 .

[0050] Fig.10 and Fig.11 The encapsulation material 51 and the crack suppression dielectric frame 21 are cut along the cutting line "L" to cut the un-singulated assembly into individual pieces.

[0051] Fig.12 1 is a cross-sectional view of a separate semiconductor assembly 101. In this figure, the semiconductor assembly 101 includes an interconnect unit A, a crack suppression dielectric subframe 21', a semiconductor element 31, a wire 41 and a packaging material 51. The interconnect unit A includes a conductive column 111, a thermal pad 113 and an interface dielectric layer 23. The crack suppression dielectric subframe 21' is separated from the crack suppression dielectric frame 21 and surrounds the interconnect unit A. The conductive columns 111 are separated from each other and from the crack suppression dielectric subframe 21' by the interface dielectric layer 23. The interface dielectric layer 23 laterally covers and surrounds the sidewalls of the conductive columns 111 and the inner edge of the crack suppression dielectric subframe 21'. The semiconductor element 31 is thermally conductive to the thermal pad 113 through the thermal conductive adhesive and is electrically connected to the conductive column 111 through the wire 41. The packaging material 51 covers the semiconductor element 31 and extends laterally to the periphery of the crack suppression dielectric subframe 21'.

[0052] Fig.13FIG. 1 is a cross-sectional view of another semiconductor assembly according to the first embodiment of the present invention. The semiconductor assembly 102 is similar to Fig.12 The difference between the illustrated assembly and the crack suppression dielectric frame 21 is that the crack suppression dielectric frame 21 is completely removed during the singulation process. Therefore, the final semiconductor assembly 102 does not have any crack suppression dielectric frame after singulation, and the interface dielectric layer 23 and the packaging material 51 extend laterally to the periphery of the semiconductor assembly 102.

[0053] [Example 2]

[0054] Figure 14-15 Schematic diagram of the method for making an unisolated assembly in the second embodiment of the present invention. For the purpose of brief description, any description in the above embodiment 1 that can be used in the same application is included here, and there is no need to repeat the same description.

[0055] Fig.14 FIG. 2 is a cross-sectional view of a semiconductor package substrate 200 according to a second embodiment of the present invention. Figure 6 The difference of the structure shown is that an external dielectric layer 25 is further provided to cover the crack suppression dielectric frame 21 and the interface dielectric layer 23 from below, and the bottom surface of the external dielectric layer 25 is substantially coplanar with the bottom sides of the conductive pillars 111 and the thermal pads 113 .

[0056] Fig.15 To provide a semiconductor element 31 to be wired to Fig.14 The semiconductor package substrate 200 is shown in cross-sectional view and optionally provided with a packaging material 51 for packaging. The semiconductor element 31 is electrically connected to the semiconductor package substrate 200 via a wire 41 and is covered by the packaging material 51 .

[0057] Fig.16 For Fig.15 A cross-sectional view of a semiconductor assembly 201 that has not been separated from the assembly. The semiconductor assembly 201 includes a crack suppression dielectric subframe 21 ′, conductive pillars 111 , a thermal pad 113 , an interface dielectric layer 23 , an external dielectric layer 25 , a semiconductor element 31 , a wire 41 , and a packaging material 51 .

[0058] [Example 3]

[0059] Figure 17-Figure 18 For the purpose of brief description, any descriptions of the above embodiments that can be used in the same manner are included here, and there is no need to repeat the same descriptions.

[0060] Fig.17 FIG. 3 is a cross-sectional view of a semiconductor package substrate 300 according to a third embodiment of the present invention. Figure 6The structure shown in the figure is different in that each thermal pad 113 has a seat 1131 and a fin 1133, wherein the fin 1133 protrudes from the seat 1131 and is separated from each other by a gap filled with an interface dielectric layer 23, and the interface dielectric layer 23 laterally covers and surrounds the sidewalls of the fin 1133. The seat 1131 extends laterally below the bottom surface of the interface dielectric layer 23 and generally has a bottom side that is substantially coplanar with the bottom side of the conductive column 111. Each fin 1133 has a proximal end adjacent to the seat 1131 and a distal end opposite to the proximal end and substantially coplanar with the top side of each conductive column 111. Preferably, the distal end of each fin 1133 and the top side of each conductive column 111 have the same exposed surface to ensure that the solder balls subsequently attached to the distal end of the fin 1133 and the top side of the conductive column 111 have the same height, thereby avoiding false soldering.

[0061] Fig.18 A semiconductor element 31 is provided to couple to Fig.17 A cross-sectional view of a semiconductor package substrate 300 is shown, and optionally provided with a packaging material 51 for packaging. In this illustration, the semiconductor package substrate 300 is inverted, and each semiconductor element 31 is attached to the seat 1131 of the corresponding thermal pad 113 by a thermally conductive adhesive, and is electrically connected to the conductive column 111 via a wire 41, and is covered with a packaging material 51.

[0062] Fig.19 For Fig.18 A cross-sectional view of a semiconductor assembly 301 that has not been separated from the assembly. The semiconductor assembly 301 includes a crack suppression dielectric subframe 21 ′, conductive pillars 111 , thermal pads 113 , an interface dielectric layer 23 , a semiconductor element 31 , a conductive wire 41 , and a packaging material 51 .

[0063] [Example 4]

[0064] Figure 20-Figure 28 Schematic diagram of a method for manufacturing a semiconductor package substrate in a fourth embodiment of the present invention. For the purpose of brief description, any descriptions in the above embodiments that can be used in the same application are combined here, and there is no need to repeat the same descriptions.

[0065] Fig. 20 and Fig.21 1 and 2 are a cross-sectional view and a top perspective view of a patterned conductive layer 15 formed on a sacrificial carrier 14. The patterned conductive layer 15 is generally made of copper, aluminum, alloy 42, iron, nickel, silver, gold, combinations thereof, alloys thereof, or any other suitable metal, and can be deposited on the sacrificial carrier 14 by, for example, electrolytic plating. The patterned conductive layer 15 includes a circuit portion 151 and a frame portion 153. The frame portion 153 can define a compartment 20 of an NxM array (e.g., a 2x2 array shown in this embodiment). The circuit portion 151 generally has the same circuit pattern in each compartment 20.

[0066] Fig. 22 1 is a cross-sectional view of an array of protrusions 11. The protrusions 11 are deposited on the circuit portion 151 of the patterned conductive layer 15 by, for example, electrolytic plating. In this figure, the protrusions 11 are present in the same number and arrangement in each compartment 20, and include conductive pillars 111 for vertical electrical connection and thermal pads 113 for connecting components.

[0067] Fig.23 and Fig.24 1 and 2 are a cross-sectional view and a top perspective view respectively provided with a crack suppression dielectric frame 21. The crack suppression dielectric frame 21 is placed on and attached to the top surface of the frame portion 153 of the patterned conductive layer 15. Therefore, the compartment 20 is laterally surrounded by the crack suppression dielectric frame 21.

[0068] Fig.25 and Fig.26 A cross-sectional view and a top perspective view are provided respectively with an interface dielectric layer 23. The interface dielectric layer 23 fills the remaining space in the compartment 20 to cover the sidewalls of the protrusion 11, the unoccupied top surface of the sacrificial carrier 14 and the line portion 151 of the patterned conductive layer 15, and the inner edge of the crack suppression dielectric frame 21 and the frame portion 153 of the patterned conductive layer 15.

[0069] Fig. 27 and Fig.28 The cross-sectional view and bottom perspective view are respectively after removing the sacrificial carrier 14. The sacrificial carrier 14 can be completely removed by various techniques, such as wet chemical etching, electrochemical etching or laser, to reveal the patterned conductive layer 15 from below.

[0070] Accordingly, a semiconductor package substrate 400 is completed, which includes a conductive column 111, a thermal pad 113, a patterned conductive layer 15, an interface dielectric layer 23, and a crack suppression dielectric frame 21. The patterned conductive layer 15 is embedded in the interface dielectric layer 23 and has a bottom surface that is substantially coplanar with the bottom surface of the interface dielectric layer 23. The conductive column 111 and the thermal pad 113 are disposed on the top surface of the patterned conductive layer 15 and are laterally covered by the interface dielectric layer 23.

[0071] [Example 5]

[0072] Figure 29-Figure 30 Schematic diagram of a method for manufacturing a semiconductor package substrate in a fifth embodiment of the present invention. For the purpose of brief description, any descriptions in the above embodiments that can be used in the same application are combined here, and there is no need to repeat the same descriptions.

[0073] Fig.29 FIG. 5 is a cross-sectional view of a semiconductor package substrate 500 combined with a sacrificial carrier 14. The semiconductor package substrate 500 is similar to Figure 20-Figure 28The method shown is fabricated on a sacrificial carrier 14 , the difference being that the patterned conductive layer 15 includes a circuit portion 151 but does not have a frame portion, so the crack suppression dielectric frame 21 is directly placed on the sacrificial carrier 14 .

[0074] Fig.30 1 is a cross-sectional view after removing the sacrificial carrier 14. By removing the sacrificial carrier 14, the bottom surface of the crack suppression dielectric frame 21 is exposed from below and is substantially coplanar with the bottom surfaces of the interface dielectric layer 23 and the patterned conductive layer 15.

[0075] [Example 6]

[0076] Figure 31-Figure 32 Schematic diagram of the method for making a non-isolated assembly in the sixth embodiment of the present invention. For the purpose of brief description, any descriptions of the above embodiments that can be used in the same application are all included here, and there is no need to repeat the same descriptions.

[0077] Fig.31 FIG. 6 is a cross-sectional view of a semiconductor package substrate 600 according to a sixth embodiment of the present invention. Figure 6 The difference of the structure shown is that a portion of the thermal pad 113 is removed from above by etching, for example, to form a cavity C for placing the device. In this figure, the depth of the cavity C is less than the thickness of the interface dielectric layer 23, and the interface dielectric layer 23 has an inner surrounding sidewall exposed from the cavity C.

[0078] Fig.32 A semiconductor element 31 is provided to couple to Fig.31 The semiconductor package substrate 600 is shown in cross-sectional view and optionally provided with packaging material 51 for packaging. Each semiconductor element 31 is disposed in a corresponding cavity C and is placed on the thermal pad 113 by thermally conductive adhesive, and is electrically connected to the conductive pillar 111 by a wire 41. The packaging material 51 covers the semiconductor package substrate 600, the semiconductor element 31 and the wire 41 from above, and extends into the remaining space in the cavity C.

[0079] Fig.33 For Fig.32 A cross-sectional view of a semiconductor assembly 601 that has not been separated from the assembly. The semiconductor assembly 601 includes a crack suppression dielectric subframe 21 ′, conductive pillars 111 , thermal pads 113 , an interface dielectric layer 23 , a semiconductor element 31 , a conductive wire 41 , and a packaging material 51 .

[0080] [Example 7]

[0081] Figure 34-Figure 35 Schematic diagram of a method for manufacturing a semiconductor package substrate in the seventh embodiment of the present invention. For the purpose of brief description, any descriptions of the above embodiments that can be used in the same application are combined here, and there is no need to repeat the same descriptions.

[0082] Fig.34 FIG. 1 is a cross-sectional view of a semiconductor package substrate 700 combined with a sacrificial carrier 14. The semiconductor package substrate 700 includes a first interconnection component 71 and a second interconnection component 72 in a stacked configuration. Fig.29 As shown, a first interconnect component 71 combined with a sacrificial carrier 14 is fabricated, and then a patterned conductive layer 15 and a crack-suppressing dielectric frame 21 of a second interconnect component 72 are deposited on the first interconnect component 71, and then conductive pillars 111 and thermal pads 113 are formed and then an interface dielectric layer 23 is coated. The crack-suppressing dielectric frame 21 of the second interconnect component 72 is aligned with and disposed on the crack-suppressing dielectric frame 21 of the first interconnect component 71. The patterned conductive layer 15 of the second interconnect component 72 extends laterally on the top surface of the interface dielectric layer 23 of the first interconnect component 71 and is electrically coupled to the conductive pillars 111 and thermal pads 113 of the first interconnect component 71.

[0083] Fig.35 1 is a cross-sectional view after the sacrificial carrier 14 is removed. By removing the sacrificial carrier 14, the crack suppression dielectric frame 21, the patterned conductive layer 15 and the interface dielectric layer 23 of the first interconnection component 71 are exposed from below. In this figure, each of the first interconnection component 71 and the second interconnection component 72 may have a Fig.30 Although the semiconductor package substrate with a stacked structure in this embodiment is shown as having two interconnection components, it is understood that the semiconductor package substrate may include additional interconnection components as required.

[0084] Fig.36 FIG. 2 is a cross-sectional view of another semiconductor package substrate 700A according to the seventh embodiment of the present invention. The semiconductor package substrate 700A is similar to Fig.35 The structure shown is different in that the second interconnect assembly 72 does not include the crack suppression dielectric frame 21.

[0085] Fig.37 FIG. 2 is a cross-sectional view of another semiconductor package substrate 700B according to the seventh embodiment of the present invention. The semiconductor package substrate 700B is similar to Fig.35 The structure shown is different in that the first interconnect assembly 71 does not include the crack suppression dielectric frame 21.

[0086] The semiconductor package substrate and assembly described above are merely examples, and the present invention may be implemented through various other embodiments. In addition, the above embodiments may be mixed and matched with each other or with other embodiments based on design and reliability considerations. The semiconductor element may share or not share a thermal pad with other semiconductor elements. For example, the thermal pad may accommodate a single semiconductor element, or multiple semiconductor elements may be placed on a single thermal pad.

[0087] As shown in the above embodiments, the present invention constructs a unique semiconductor package substrate that exhibits improved reliability, wherein a crack suppression dielectric frame separates a plurality of compartments, each compartment accommodating an interconnect unit. The interconnect unit mainly includes a conductive column, an interface dielectric layer, an optional thermal pad, and an optional patterned conductive layer. In addition, the semiconductor package substrate may include a plurality of interconnect components in a stacked configuration. In one or more preferred embodiments, each interconnect component includes a conductive column, an interface dielectric layer, a patterned conductive layer, and an optional thermal pad, and at least one of the interconnect components further includes a crack suppression dielectric frame, which separates a plurality of compartments accommodating the interconnect unit, each interconnect unit is disposed in a corresponding compartment and includes a conductive column, an interface dielectric layer, a patterned conductive layer, and an optional thermal pad.

[0088] A crack suppression dielectric frame is used to replace the metal frame currently used to establish multiple separate compartments, and each compartment contains an interconnected unit. The top side of the crack suppression dielectric frame can be substantially coplanar with the top side of the conductive column, and the bottom side of the crack suppression dielectric frame can be located at a level between the top side and the bottom side of the conductive column, or substantially coplanar with the bottom side of the conductive column or the bottom surface of the patterned conductive layer adjacent to the bottom side of the conductive column. Compared with the commonly used metal frame, the crack suppression dielectric frame generally has an elastic modulus of less than 50GPa and can reduce the warping caused by the subsequent coating of the interface dielectric layer. Preferably, the crack suppression dielectric frame is made of an organic material without filler to prevent filler particles from causing the dielectric frame to be easily cracked. More preferably, the crack suppression dielectric frame is made of an organic material containing a reinforcement configured to inhibit crack propagation.

[0089] The interface dielectric layer covers and contacts and conformally coats the sidewalls of the conductive pillars and optional thermally conductive pads and the inner edge of the crack suppression dielectric frame. Typically, the interface dielectric layer is made of a different material than the crack suppression dielectric frame and has a bottom surface that is substantially coplanar with or located at a level below the bottom side of the crack suppression dielectric frame. In order to effectively absorb stress and reduce structural warping during coating of the interface dielectric layer, the interface dielectric layer may have an elastic modulus lower than that of the crack suppression dielectric frame. In one or more preferred embodiments, the interface dielectric layer is composed of an organic material doped with an electrically insulating filler with a low coefficient of thermal expansion (CTE) to reduce internal expansion and contraction of the interface dielectric layer during thermal cycling. For example, the electrically insulating filler may have a CTE of less than 20 ppm.

[0090] The conductive pillars can provide vertical conduction and are separated from each other by the interfacial dielectric layer. Typically, the top side of the conductive pillars is substantially coplanar with the top surface of the interfacial dielectric layer. In addition, the conductive pillars can further extend laterally below the bottom surface of the interfacial dielectric layer.

[0091] The optional thermal pad can provide heat conduction with the semiconductor element and be separated from the conductive column by the interface dielectric layer. The top side and bottom side of the thermal pad can be substantially coplanar with the top side and bottom side of the conductive column, respectively. Alternatively, in an example of forming a recess aligned with the thermal pad, the top side of the thermal pad is lower than the top side of the conductive column and is preferably located between the top surface and the bottom surface of the interface dielectric layer, and the recess is defined by the inner sidewall of the interface dielectric layer and the top side of the thermal pad, wherein the top side of the thermal pad serves as the bottom of the recess. In addition, the thermal pad may further extend below the bottom surface of the interface dielectric layer. In one or more preferred embodiments, the thermal pad has a seat and fins protruding from the seat and separated from each other by spacing. Each fin has a proximal end adjacent to the seat and a distal end opposite to the proximal end and substantially coplanar with the top side of each conductive column. The interface dielectric layer can fill the gap between the fins so that each fin sidewall is laterally covered and surrounded by the interface dielectric layer. The distal end of each fin may be substantially coplanar with the top surface of the interfacial dielectric layer. The distal end of each fin and the top side of each conductive pillar preferably have the same exposed surface area. In this way, the semiconductor element can be attached to the base, and the solder balls attached to the distal ends of the fins and the top side of the conductive pillars (for the next level of interconnection) can have the same height, thereby avoiding false soldering.

[0092] The optional patterned conductive layer may be formed adjacent to the bottom side of the conductive pillars to provide horizontal routing. In one or more preferred embodiments, the patterned conductive layer may be first deposited on a sacrificial carrier, followed by the deposition of the conductive pillars, the optional thermal pads, the crack suppression dielectric frame, and the interface dielectric layer, and then the sacrificial carrier is removed. Thus, the patterned conductive layer may be embedded in the interface dielectric layer, and the bottom surface of the patterned conductive layer is substantially coplanar with the bottom surface of the interface dielectric layer. For a semiconductor package substrate having a stacked configuration, the patterned conductive layer of the upper interconnect component extends laterally over the interface dielectric layer of the lower interconnect component and onto the conductive pillars and the optional thermal pads of the lower interconnect component.

[0093] The present invention also provides a semiconductor assembly that electrically connects a semiconductor element to the above-mentioned semiconductor package substrate and optionally covers the semiconductor element with a packaging material. In one or more preferred embodiments, each semiconductor element overlaps above a corresponding thermal pad and is thermally conductive with the corresponding thermal pad through a thermally conductive adhesive, and is electrically connected to a conductive column of the semiconductor package substrate via a wire. For a semiconductor package substrate having a recess above the thermal pad, the semiconductor element is disposed in the recess and is laterally surrounded by a surrounding portion of the interface dielectric layer. The semiconductor element may be a packaged chip or an unpackaged chip. In addition, the semiconductor element may be a bare chip, or a wafer-level packaged die, etc.

[0094] The term "covering" means incomplete as well as complete covering in the vertical and / or lateral directions. For example, in a preferred embodiment, the interfacial dielectric layer partially covers the sidewalls of the conductive pillar, wherein the upper sidewall of the conductive pillar is completely covered by the interfacial dielectric layer, while the lower sidewall is not covered.

[0095] The term "surrounding" refers to the relative position of components, whether the components are spaced apart or adjacent to each other. For example, in a preferred embodiment, the crack suppression dielectric frame has a plurality of inner edges, each of which laterally surrounds a corresponding interconnect unit.

[0096] The meanings of "disposed on" and "attached to / attached on" include contact and non-contact with a single or multiple components. For example, in a preferred embodiment, the semiconductor component can be attached to the thermal pad and separated from the thermal pad by thermal conductive glue.

[0097] The words "electrically connected" and "electrically coupled" refer to direct or indirect electrical connection. For example, in a preferred embodiment, the semiconductor element is electrically connected to the conductive pillar through a wire, but does not contact the conductive pillar.

[0098] For ease of description, spatially relative terms such as "top", "bottom", "below", "above", "lower", "upper" may be used herein to describe the relationship between an element or feature and another element or feature as shown in the figure. In addition to the orientations depicted in the figure, spatially relative terms are intended to cover substrates or assemblies in different orientations during use or operation. For example, if the substrate or assembly in the figure is flipped, the element described as "below" other elements or features will be oriented to be "above" other elements or features, and the "bottom" surface will become the "top" surface. Therefore, the exemplary term "below" can cover both the above and below directions. The substrate or assembly can be oriented in other ways (rotated 90 degrees or in other directions), and the spatially relative descriptions used herein are also interpreted accordingly.

[0099] The manufacturing method of the present invention is highly applicable and combines various mature electrical and mechanical connection technologies in a unique and progressive way. In addition, the manufacturing method of the present invention can be implemented without expensive tools. Therefore, compared with traditional technologies, this manufacturing method can greatly improve production, yield, performance and cost-effectiveness.

[0100] The embodiments described herein are for illustration purposes only, and these embodiments may simplify or omit elements or steps known in the art to avoid blurring the features of the present invention. Similarly, for clarity of the drawings, the drawings may omit repeated or unnecessary elements and element symbols.

Claims

1. A semiconductor package substrate using a dielectric frame to separate interconnection units, characterized in that: The invention comprises a crack suppression dielectric frame and a plurality of interconnection units, each of the interconnection units being disposed in a corresponding one of the separation compartments defined by the crack suppression dielectric frame and comprising a conductive column and an interface dielectric layer, wherein: The crack suppression dielectric rack has a plurality of inner edges each side surrounding a corresponding one of the interconnecting unit; The conductive columns are arranged in the compartment and are separated from each other by the interface dielectric layer; and The interface dielectric layer laterally covers and surrounds the side walls of the conductive posts and covers the inner edge of the crack-resisting dielectric frame.

2. The semiconductor package substrate according to claim 1, wherein: The crack suppression dielectric frame has an elastic modulus of less than 50 Gpa.

3. The semiconductor package substrate according to claim 1, wherein: The crack suppression dielectric rack is an organic material having reinforcement configured to suppress crack propagation.

4. The semiconductor package substrate according to claim 1, wherein: The interface dielectric layer has an elastic modulus lower than the crack suppression dielectric frame.

5. The semiconductor package substrate according to claim 1, wherein: The interface dielectric layer is an organic material with an electrically insulating filler.

6. The semiconductor package substrate according to claim 5, wherein: The electrically insulating filler has a thermal expansion coefficient of less than 20 ppm.

7. The semiconductor package substrate according to claim 1, wherein: The conductive column also extends laterally below the bottom surface of the interface dielectric layer.

8. The semiconductor package substrate according to claim 1, wherein: Each of the interconnecting units further comprises a patterned conductive layer adjacent the conductive post.

9. The semiconductor package substrate according to claim 8, wherein: The patterned guide layer is embedded in the interface dielectric layer, and the bottom surface of the patterned guide layer is substantially coplanar with the bottom surface of the interface dielectric layer.

10. The semiconductor package substrate according to claim 1, wherein: Each of the interconnecting units further comprises a thermal pad, and the interface dielectric layer laterally covers and surrounds the side wall of the thermal pad.

11. The semiconductor package substrate according to claim 10, wherein: The top side of the thermal pad serves as the bottom of a concave hole, and the interface dielectric layer surrounds the concave hole sideways.

12. The semiconductor package substrate of claim 10, wherein The conductive column and the thermal pad also extend laterally below the bottom surface of the interface dielectric layer.

13. The semiconductor package substrate of claim 10, wherein Each of the interconnecting units further comprises a patterned conductive layer adjacent to the conductive post and the thermal pad.

14. The semiconductor package substrate of claim 13, wherein The patterned guide layer is embedded in the interface dielectric layer, and the bottom surface of the patterned guide layer is substantially coplanar with the bottom surface of the interface dielectric layer.

15. The semiconductor package substrate of claim 10, wherein The thermal pad has a seat portion and a fin portion, which protrude from the seat portion and are spaced from each other by a gap.

16. The semiconductor package substrate of claim 15, wherein Each of the fins has a proximal end and a distal end, the proximal end is adjacent to the seat, the distal end is substantially coplanar with the proximal end and with the exposed surface of each of the conductive pillars, and the exposed surface area of ​​each of the conductive pillars is substantially equal to the exposed surface area of ​​the distal end of each of the fins.

17. The semiconductor package substrate of claim 15, wherein The interface dielectric layer also fills the gap and laterally covers and surrounds the side walls of the fins.

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