Single-chip integrated half-bridge
By integrating the half-bridge structure on a single chip, using multi-layer doped regions and trench structures to achieve horizontal and vertical conduction of diodes, the problems of complex packaging and low power density of traditional half-bridge devices are solved, and higher power density is achieved and cost-effective.
Patent Information
- Application Number
- CN202421096591.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-20
- Publication Date
- 2024-12-31
- Estimated Expiration
- 2034-05-20
AI Technical Summary
Traditional half-bridge rectifier devices have complex packaging processes and large packaging bodies, resulting in reduced power density and increased cost, making it difficult to meet the requirements of high power density and cost-effectiveness.
Using a single-chip integrated half-bridge structure, two reverse parallel diodes are integrated on one chip. By setting a multi-layer doping region and trench structure on the epitaxial chip, horizontal and vertical conductivity is achieved, packaging process is simplified and power density is improved. .
It effectively reduces the packaging process steps and costs, reduces chip usage, and increases the device power density, making it twice that of traditional half-bridge devices.
Smart Images
Figure CN222281997U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductors, in particular to a single-chip integrated half-bridge. Background Art
[0002] In the field of power electronic device technology, AC to DC conversion has always been an important application field. The current rectification methods include diode rectification, half-bridge rectification and full-bridge rectification.
[0003] Half-bridge rectification is a commonly used rectification method and needs to be implemented using a rectification half-bridge. The traditional rectification half-bridge is to package two diode chips in reverse parallel into one device. The packaging process is complicated and the package body is large, resulting in a decrease in device power density and an increase in cost. As power semiconductors have higher and higher requirements for power density and cost-effectiveness, increasing the power density of rectification half-bridges has attracted more and more attention. Utility Model Content
[0004] In view of the above problems, the utility model provides a single-chip integrated half-bridge which can effectively improve the power density of the rectifier half-bridge.
[0005] The technical solution of the utility model is:
[0006] A single chip integrated half bridge comprises a second cathode, an epitaxial wafer and an isolation layer arranged in sequence from bottom to top;
[0007] The epitaxial wafer is provided with:
[0008] A first heavily doped P region extending downward from the top surface of the epitaxial wafer and located in the first lightly doped N region;
[0009] A first heavily doped N region extends downward from the top surface of the epitaxial wafer and is located in the first lightly doped N region; a trench is provided on the top surface of the epitaxial wafer that passes through the first heavily doped N region and extends downward into the second lightly doped N region;
[0010] a second heavily doped P region extending downward from the bottom surface of the trench;
[0011] a second anode extending upward from the bottom surface of the trench and flush with the top surface of the epitaxial wafer;
[0012] The isolation layer is provided with:
[0013] A first anode extending downward from the top surface of the isolation layer and connected to the first heavily doped P region;
[0014] The first cathode extends downward from the top surface of the isolation layer and is connected to the first heavily doped N region and the second anode.
[0015] Specifically, the epitaxial wafer includes, from bottom to top, a second heavily doped N region, a second lightly doped N region, an oxide isolation layer and a first lightly doped N region.
[0016] Specifically, the doping concentration of the second lightly doped N region is 1e 13 .cm -3 To 1e 17 .cm -3 ;
[0017] The doping concentration of the second heavily doped N region is 1e 19 .cm -3 To 1e 21 .cm -3 .
[0018] The epitaxial wafer is a SOI epitaxial wafer with a thickness of 121-2010um.
[0019] Specifically, the thickness of the second heavily doped N region 11 is 100-1000 um, and the thickness of the second lightly doped N region 12 is 10-500 um.
[0020] Beneficial effects of the utility model:
[0021] Traditional half-bridge devices require two diode chips to be packaged in reverse parallel. The packaging process is complicated and the package body is large, resulting in a decrease in device power density and an increase in cost. In this case, the half-bridge rectifier chip integrates two reverse-parallel diodes on one chip. The diode from the first anode to the first cathode area conducts horizontally, and the diode from the second anode to the second cathode area conducts vertically, which effectively utilizes the chip area. Using the half-bridge rectifier chip in this case only requires one chip to be packaged, reducing the packaging process steps and costs. Using the half-bridge rectifier chip in this case can reduce the chip usage by half, and the power density is twice that of traditional half-bridge devices. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Figure 1 This is a process flow chart of the utility model.
[0023] Figure 2 is a schematic diagram of the cross-sectional structure of the device in step S100,
[0024] Figure 3 is a schematic diagram of the cross-sectional structure of the device in step S200,
[0025] Figure 4 is a schematic diagram of the cross-sectional structure of the device in step S300,
[0026] Figure 5 is a schematic diagram of the cross-sectional structure of the device in step S400,
[0027] Figure 6is a schematic diagram of the cross-sectional structure of the device in step S500,
[0028] Figure 7 is a schematic diagram of the cross-sectional structure of the device in step S600,
[0029] In the figure, 1 is the epitaxial wafer, 2 is the first heavily doped P region, 3 is the first heavily doped N region, 4 is the trench, 5 is the second heavily doped P region, 6 is the isolation layer, 7 is the first anode, 8 is the first cathode, 9 is the second anode, 10 is the second cathode, 11 is the second heavily doped N region, 12 is the second lightly doped N region, 13 is the oxide isolation layer, and 14 is the first lightly doped N region. DETAILED DESCRIPTION
[0030] The embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.
[0031] In the description of the present invention, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In the description of the present invention, unless otherwise specified, "plurality" means two or more.
[0032] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0033] The utility model is described below with reference to Figures 1-7;
[0034] A method for preparing a single-chip integrated half-bridge comprises the following steps:
[0035] Step S100, preparing a first heavily doped P region 2 on the epitaxial wafer 1, such as Figure 2 As shown;
[0036] Step S110, using a mask to protect the outer area of the first heavily doped P region 2 through a photolithography process;
[0037] Step S120: forming a first heavily doped P region 2 by diffusion or ion implantation.
[0038] Correspondingly, the epitaxial wafer is an SOI epitaxial wafer, and the epitaxial wafer 1 is composed of a second heavily doped N region 11, a second lightly doped N region 12, an oxide isolation layer 13, and a first lightly doped N region 14 from bottom to top. The thickness of the epitaxial wafer is 121-2010um, the thickness of the second heavily doped N region 11 is 100-1000um, the thickness of the second lightly doped N region 12 is 10-500um, the thickness of the oxide isolation layer is 1-10um, the thickness of the first lightly doped N region 14 is 10-500um, the first heavily doped P region 2 is located inside the first lightly doped N region 14, the upper surface is level with the upper surface of the epitaxial wafer 1, and the lower surface is higher than the upper surface of the oxide isolation layer 13. The junction depth is set to 1-100um, the width is set to 1-100um, and the doping concentration of all lightly doped regions is 1e 13 .cm -3 To 1e 17 .cm -3 , the doping concentration of the heavily doped region is 1e 19 .cm -3 To 1e 21 .cm -3 , the N-type doping element is phosphorus or arsenic, the P-type doping element is boron, and the relevant parameter settings are related to the device electrical design;
[0039] In this embodiment, the thickness of the epitaxial wafer 1 is 605 μm, the doping element of the second heavily doped N region 11 is phosphorus, and the doping concentration is 2e 19 .cm -3 , with a thickness of 400um, the doping element of the second lightly doped N region 12 is phosphorus, and the doping concentration is 1e 14. cm -3 , the thickness is 100um, the thickness of the oxide isolation layer is 5um, the doping element of the first lightly doped N region 14 is phosphorus, and the doping concentration is 1e 14. cm -3 , thickness is 100um, the doping element of the first heavily doped P region 2 is boron, and the doping concentration is 2e 19 .cm -3 The junction depth is 30um, the width is 30um, and the first heavily doped P region 2 is formed using a diffusion process.
[0040] Step S200, preparing a first heavily doped N region 3 on the epitaxial wafer 1, such as Figure 3 As shown;
[0041] Step S210, using a mask to protect the outer area of the first heavily doped N region 3 through a photolithography process;
[0042] Step S220: forming a first heavily doped N region 3 by diffusion or ion implantation.
[0043] Correspondingly, the first heavily doped N region 3 is located inside the first lightly doped N region 14, the upper surface is level with the upper surface of the epitaxial wafer 1, the lower surface is higher than the upper surface of the oxide isolation layer 13, the junction depth is set to 1-100um, the width is set to 1-100um, the first heavily doped P region 2 and the first heavily doped N region 3 are not connected, and the distance between the two is set to 10-500um. The relevant parameter settings are related to the electrical design of the device;
[0044] In this embodiment, the first heavily doped N region 3 is phosphorus, and the doping concentration is 2e 19 .cm -3 , the junction depth is 30um, the width is 30um, and the first heavily doped N region 3 is prepared by a diffusion process. The first heavily doped P region 2 and the first heavily doped N region 3 are not connected, and the distance between the two is set to 70um.
[0045] Step S300, a trench 4 extending to the second lightly doped N region 12 is formed in the first heavily doped N region 3, such as Figure 4 As shown;
[0046] Step S310, using a mask to protect a portion of the first heavily doped N region 3 and an external region through a photolithography process;
[0047] Step S320, preparing the groove 4 by etching process.
[0048] Accordingly, the notch of the trench 4 is located in the first heavily doped N region 3, the notch width is smaller than the first heavily doped N region 3, the upper surface is level with the upper surface of the epitaxial wafer 1, and the lower surface extends to the inside of the second lightly doped N region 12. The relevant parameter settings are related to the device electrical design;
[0049] In this embodiment, the groove 4 is set to 20um, located at the center of the first heavily doped N region 3, with the surface level with the upper surface of the epitaxial wafer 1, and the lower surface extending to the upper surface of the second lightly doped N region 12, with a depth of 105um.
[0050] Step S400, prepare a second heavily doped P region 5 on the bottom surface of the trench 4, and prepare a second anode 9 in the trench, such as Figure 5 As shown;
[0051] Step S410, using a mask to protect the outer area of the trench 4 through a photolithography process;
[0052] Step S420, forming a second heavily doped P region 5 at the bottom of the trench 4 by diffusion or ion implantation process;
[0053] Step S430 , depositing an ohmic contact metal in the groove 4 by a stripping process or an etching process to prepare a second anode 9 .
[0054] Correspondingly, the second heavily doped P region 5 is located inside the second lightly doped N region 12, the upper surface is level with the lower surface of the groove 4, the lower surface is higher than the lower surface of the second lightly doped N region 12, the junction depth is set to 1-100um, and the width is consistent with the groove width. The second anode 9 is located inside the groove 4, the upper surface is level with the upper surface of the epitaxial wafer 1, and the lower surface is located at the bottom of the groove, and forms a good ohmic contact with the second heavily doped P region 5. The relevant parameter settings are related to the device electrical design;
[0055] In this embodiment, the doping element of the second heavily doped P region 5 is boron, and the doping concentration is 2e 19 .cm -3 The junction depth is 5um and the width is 20um. The second heavily doped P region 5 is prepared by ion implantation process, and the second anode 9 is prepared by metal stripping process. The upper surface of the second anode 9 is level with the upper surface of the epitaxial wafer 1, and the lower surface is located at the bottom of the groove. Four layers of metal Al / Ti / Ni / Ag are used as ohmic contact metal to form a good ohmic contact with the second heavily doped P region 5.
[0056] Step S500, depositing an isolation layer 6 on the epitaxial wafer 1, and opening windows in the first heavily doped P region 2 and the first heavily doped N region 3, respectively, as shown in FIG. Figure 6 As shown;
[0057] Step S510, preparing an isolation layer 6 by chemical vapor deposition;
[0058] Step S520 , using a mask to protect the outer regions of the first heavily doped P region 2 and the first heavily doped N region 3 through a photolithography process, and using an etching process to open windows in the first heavily doped P region 2 and the first heavily doped N region 3 .
[0059] Correspondingly, the isolation layer 6 plays a protective role, and its material is SiO2 or Si3N4, and its thickness is set to 10-5000nm. ICP dry etching is used for window opening, and the relevant parameter settings are related to the electrical design of the device.
[0060] In this embodiment, Si3N4 is used as the isolation layer 6, the thickness is set to 200nm, CF4 is used for ICP dry etching, the etching rate is 10nm / min to ensure the accuracy of etching, and the etching time is set to 21min to ensure successful window opening.
[0061] Step S600, prepare a first anode 7 and a first cathode 8 at the regional window; and prepare a second cathode 10 at the bottom of the epitaxial wafer 1, such as Figure 7 As shown;
[0062] Step S610, preparing a first anode 7 and a first cathode 8 at the openings in the first heavily doped P region 2 and the first heavily doped N region 3 by a stripping process or an etching process;
[0063] Step S620, preparing a second cathode 10 at the bottom of the epitaxial wafer 1 by thinning process and back-gold process;
[0064] Correspondingly, the first anode 7 and the first cathode 8 are in contact with the first heavily doped P region 2 and the first heavily doped N region 3 below, and form a good ohmic contact. The upper surface of the first anode 7 and the first cathode 8 is level with the upper surface of the isolation layer 6. The lower surface of the first cathode 8 is level with the upper surface of the second anode 9, and the two are in contact to form an interconnection. The second cathode 10 is in contact with the second heavily doped N region 11 above, and forms a good ohmic contact.
[0065] In this case, a metal stripping process is used to prepare the first anode 7 and the first cathode 8, four layers of metal Al / Ti / Ni / Ag are used as ohmic contact metals, a thinning process is used to thin the 605um substrate to 255um, and a back gold process is used to deposit four layers of metal Al / Ti / Ni / Ag as the second cathode 10.
[0066] Step S700: the entire device is prepared.
[0067] A single chip integrated half bridge comprises a second cathode 10, an epitaxial wafer 1 and an isolation layer 6 arranged in sequence from bottom to top;
[0068] The epitaxial wafer 1 is provided with:
[0069] A first heavily doped P region 2 extending downward from the top surface of the epitaxial wafer 1 and located in the first lightly doped N region 14;
[0070] The first heavily doped N region 3 is spaced apart from the first heavily doped P region 2, extends downward from the top surface of the epitaxial wafer 1, and is located in the first lightly doped N region 14; the top surface of the epitaxial wafer 1 is provided with a trench 4 that passes through the first heavily doped N region 3 and extends downward to the second lightly doped N region 12; the width of the trench 4 is smaller than the width of the first heavily doped N region 3;
[0071] The second heavily doped P region 5 extends downward from the bottom surface of the trench 4; is located in the second lightly doped N region 12; the upper surface of the second heavily doped P region 5 is flush with the top surface of the second lightly doped N region 12; the lower surface of the second heavily doped P region 5 is higher than the bottom surface of the second lightly doped N region 12;
[0072] The second anode 9 extends upward from the bottom surface of the groove 4 and is flush with the top surface of the epitaxial wafer 1; the lower surface forms a good ohmic contact with the second heavily doped P region;
[0073] The isolation layer 6 is provided with:
[0074] A first anode 7 extending downward from the top surface of the isolation layer 6 and connected to the first heavily doped P region 2;
[0075] The first cathode 8 extends downward from the top surface of the isolation layer 6 and is connected to the first heavily doped N region 3 and the second anode 9 .
[0076] In the present case, the first anode 7 and the first cathode 8 are in contact with the first heavily doped P region 2 and the first heavily doped N region 3 below, and form good ohmic contact. The lower surface of the first cathode 8 and the upper surface of the second anode 9 are level, and the two are in contact to form an interconnection. The first cathode 10 is in contact with the second heavily doped N region 11 above, and form good ohmic contact.
[0077] It is further defined that the epitaxial wafer 1 includes, from bottom to top, a second heavily doped N region 11 , a second lightly doped N region 12 , an oxide isolation layer 13 and a first lightly doped N region 14 .
[0078] It is further defined that the doping concentration of the second lightly doped N region 12 is 1e 13 .cm -3 To 1e 17 .cm -3 ;
[0079] The doping concentration of the second heavily doped N region 11 is 1e 19 .cm -3 To 1e 21 .cm -3 The N-type doping element is phosphorus or arsenic, and the P-type doping element is boron.
[0080] The utility model has the following advantages:
[0081] Traditional half-bridge devices require two diode chips to be packaged in reverse parallel. The packaging process is complicated and the package body is also large, resulting in a decrease in the power density of the device and an increase in the cost. In this case, the half-bridge rectifier chip integrates two reverse-parallel diodes on one chip. The second anode 9 and the first cathode 8 are interconnected and connected to one end of the external AC power supply. The first anode 7 and the second cathode 10 are interconnected through the packaging frame and the jumper and connected to the other end of the power supply. When the first anode 7 and the second cathode 10 are connected to a positive voltage when power is turned on, the current flows from the first anode 7 through the first heavily doped P region 2, the first lightly doped N region 14, and the first heavily doped N region 3 to the first cathode 8, and the NP junction composed of the second lightly doped N region 12 and the second heavily doped P region 5 from the second cathode 10 to the second anode 9 is reversely cut off; when power is turned on, the second anode 9 and the first cathode 8 are connected to a positive voltage, and the current flows from the second anode 9 through the second heavily doped P region 5, the second lightly doped N region 12, and the second heavily doped N region 11 to the second cathode 10, and the path from the first cathode 8 to the first anode 7 is reversely cut off by the NP junction composed of the first lightly doped N region 14 and the first heavily doped P region 2.
[0082] When using the half-bridge rectifier chip in this case to prepare a rectifier half-bridge, only one chip needs to be packaged, and the packaging process steps and costs are reduced. Using the half-bridge rectifier chip in this case can reduce the chip usage by half, and the device power density is twice that of traditional half-bridge devices.
[0083] Regarding the contents disclosed in this case, there are a few points that need to be explained:
[0084] (1) The drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design;
[0085] (2) In the absence of conflict, the embodiments and features of the embodiments disclosed in this case may be combined with each other to obtain new embodiments;
[0086] The above are only specific implementation methods disclosed in this case, but the protection scope of the present disclosure is not limited thereto. The protection scope disclosed in this case should be based on the protection scope of the claims.
Claims
1. Single chip integrated half bridge, characterized in that, It comprises a second cathode (10), an epitaxial wafer (1) and an isolation layer (6) which are arranged in sequence from bottom to top; The epitaxial wafer (1) is provided with: A first heavily doped P region (2) extending downward from the top surface of the epitaxial wafer (1) and located within the first lightly doped N region (14); A first heavily doped N region (3) extends downward from the top surface of the epitaxial wafer (1) and is located in the first lightly doped N region (14); the top surface of the epitaxial wafer (1) is provided with a groove (4) passing through the first heavily doped N region (3) and extending downward to the second lightly doped N region (12); A second heavily doped P region (5) extending downward from the bottom surface of the trench (4); A second anode (9) extending upward from the bottom surface of the groove (4) and flush with the top surface of the epitaxial wafer (1); The isolation layer (6) is provided with: A first anode (7) extending downward from the top surface of the isolation layer (6) and connected to the first heavily doped P region (2); A first cathode (8) extends downward from the top surface of the isolation layer (6) and is connected to the first heavily doped N region (3) and the second anode (9).
2. The single-chip integrated half-bridge according to claim 1, characterized in that: The epitaxial wafer (1) comprises, from bottom to top, a second heavily doped N region (11), a second lightly doped N region (12), an oxide isolation layer (13) and a first lightly doped N region (14).
3. The single-chip integrated half-bridge according to claim 2, characterized in that: The doping concentration of the second lightly doped N region (12) is 1e 13 .cm -3 To 1e 17 .cm -3 ; The doping concentration of the second heavily doped N region (11) is 1e 19 .cm -3 To 1e 21 .cm -3 .
4. The single-chip integrated half-bridge according to claim 2, characterized in that: The epitaxial wafer is a SOI epitaxial wafer with a thickness of 121-2010um.
5. The single-chip integrated half-bridge according to claim 2, characterized in that: The thickness of the second heavily doped N region 11 is 100-1000 um, and the thickness of the second lightly doped N region 12 is 10-500 um.