Power MOSFET device

Abstract

The utility model relates to a power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device, which comprises a back metal layer, an N + type epitaxial layer, an N-type substrate, a P + type well region, an N + + type inner ring source region, an N + + type outer ring source region, an N + type inner ring source region, an N + type outer ring source region, a gate oxide layer, a polycrystalline silicon layer, a passivation layer and a front metal layer, an N + type inner ring source region is formed on the back surface of the N + + type inner ring source region, and an N + type outer ring source region is formed on the back surface of the N + + type outer ring source region. According to the utility model, the forward bias safe working area FBSOA of the device is enhanced, and the source electrode structure of the power MOSFET device is improved, so that the power MOSFET device is more suitable for being used in a linear mode, and is suitable for the application fields of electronic loads, audio power amplifiers, linear voltage regulators, ultrasonic high-frequency surgical integrated systems and the like.

Description

Technical Field

[0001] The utility model belongs to the technical field of semiconductors and specifically discloses a power MOSFET device. Background Art

[0002] Power MOSFETs are most commonly used in switch-mode applications, where they act as switches. However, in applications such as electronic loads, linear regulators, or class A amplifiers, the power MOSFET must be operated in its linear region. In this operating mode, the MOSFET is subject to high thermal stress. The chip is subject to high thermal stress due to the high drain-source voltage and drain current occurring simultaneously. When the thermoelectric stress exceeds a critical limit, hot spots appear in the silicon, leading to device failure. To prevent such failures, MOSFETs operating in the linear region require high power dissipation capabilities and an extended forward bias safe operating area (FBSOA). Summary of the invention

[0003] The purpose of the utility model is to overcome the deficiencies in the prior art and provide a power MOSFET device that is more suitable for use in a linear mode.

[0004] According to the technical solution provided by the utility model, the power MOSFET device includes an N-type substrate, an N+ type epitaxial layer is formed on the back of the N-type substrate, a back metal layer is formed on the back of the N+ type epitaxial layer, and the back metal layer is led out to form a drain D;

[0005] A ring-shaped P+ type well region is formed downwardly on the front side of the N-type substrate, an N++ type inner ring source region and an N++ type outer ring source region are formed downwardly on the front side of the P+ type well region, an N+ type inner ring source region is formed on the back side of the N++ type inner ring source region, an N+ type outer ring source region is formed on the back side of the N++ type outer ring source region, a gate oxide layer and a front metal layer are formed upwardly on the front side of the N-type substrate, the front metal layer is led out to form a source S, the front metal layer contacts part of the N++ type inner ring source region and part of the N++ type outer ring source region, the gate oxide layer contacts the remaining part of the N++ type inner ring source region and the remaining part of the N++ type outer ring source region, a polysilicon layer is formed upwardly on the front side of the gate oxide layer, the polysilicon layer is led out to form a gate G, and a passivation layer is formed between the polysilicon layer and the front metal layer;

[0006] The ion implantation concentration of the N+ type epitaxial layer is greater than the ion implantation concentration of the N- type substrate;

[0007] The ion implantation concentration of the N++ type inner ring source region is greater than that of the N+ type inner ring source region, and the ion implantation concentration of the N++ type outer ring source region is greater than that of the N+ type outer ring source region.

[0008] Preferably, the back metal layer includes a metal titanium layer, a metal nickel layer and a metal silver layer, the front side of the metal titanium layer is connected to the back side of the N+ type epitaxial layer, the back side of the metal titanium layer is connected to the front side of the metal nickel layer, and the back side of the metal nickel layer is connected to the front side of the metal silver layer.

[0009] More preferably, the thickness of the metal titanium layer is 400-600Å, the thickness of the metal nickel layer is 4500-5500Å, and the thickness of the metal silver layer is 5500-6500Å.

[0010] Preferably, the thickness of the N+ type epitaxial layer is 50-70 μm.

[0011] Preferably, the thickness of the N-type substrate is 120-140 μm.

[0012] Preferably, the gate oxide layer has a thickness of 110-130 nm.

[0013] Preferably, the thickness of the polysilicon layer is 5000-6000 Å.

[0014] Preferably, the passivation layer includes a phosphosilicate glass layer and a silicon nitride layer on the front side of the phosphosilicate glass layer, the thickness of the phosphosilicate glass layer is 3500-4500Å, and the thickness of the silicon nitride layer is 4500-4500Å.

[0015] Preferably, the material of the front metal layer is aluminum, and the thickness of the front metal layer is 4-5 μm.

[0016] The utility model enhances the forward bias safe operating area FBSOA of the device and improves the source structure of the power MOSFET device, thereby making the power MOSFET device more suitable for use in a linear mode, and is suitable for application fields such as electronic loads, audio power amplifiers, linear regulators, ultrasonic high-frequency surgical integrated systems, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a structural schematic diagram of the utility model. DETAILED DESCRIPTION

[0018] The utility model is further described below in conjunction with specific embodiments.

[0019] A power MOSFET device, such as Figure 1 As shown, it includes an N-type substrate 3, an N+ type epitaxial layer 2 is formed on the back of the N-type substrate 3, a back metal layer 1 is formed on the back of the N+ type epitaxial layer 2, and the back metal layer 1 is led out to form a drain D;

[0020] A circular P+ type well region 4 is formed downwardly on the front side of the N-type substrate 3, an N++ type inner ring source region 5-1 and an N++ type outer ring source region 5-2 are formed downwardly on the front side of the P+ type well region 4, an N+ type inner ring source region 6-1 is formed on the back side of the N++ type inner ring source region 5-1, and an N+ type outer ring source region 6-2 is formed on the back side of the N++ type outer ring source region 5-2, a gate oxide layer 7 and a front metal layer 10 are formed upwardly on the front side of the N-type substrate 3, and a positive gate oxide layer 7 is formed upwardly on the front side of the N-type substrate 3. The surface metal layer 10 is led out to form a source S, the front metal layer 10 contacts part of the N++ type inner ring source region 5-1 and part of the N++ type outer ring source region 5-2, the gate oxide layer 7 contacts the remaining part of the N++ type inner ring source region 5-1 and the remaining part of the N++ type outer ring source region 5-2, a polysilicon layer 8 is formed upward on the front of the gate oxide layer 7, the polysilicon layer 8 is led out to form a gate G, and a passivation layer 9 is formed between the polysilicon layer 8 and the front metal layer 10;

[0021] The ion implantation concentration of the N+ type epitaxial layer 2 is greater than the ion implantation concentration of the N- type substrate 3;

[0022] The ion implantation concentration of the N++ type inner ring source region 5-1 is greater than that of the N+ type inner ring source region 6-1, and the ion implantation concentration of the N++ type outer ring source region 5-2 is greater than that of the N+ type outer ring source region 6-2.

[0023] The back metal layer 1 includes a metal titanium layer, a metal nickel layer and a metal silver layer. The front side of the metal titanium layer is connected to the back side of the N+ epitaxial layer 2, the back side of the metal titanium layer is connected to the front side of the metal nickel layer, and the back side of the metal nickel layer is connected to the front side of the metal silver layer. The thickness of the metal titanium layer is 400-600Å, the thickness of the metal nickel layer is 4500-5500Å, and the thickness of the metal silver layer is 5500-6500Å.

[0024] The thickness of the N+ type epitaxial layer 2 is 50-70 μm.

[0025] The thickness of the N-type substrate 3 is 120-140 μm.

[0026] The thickness of the gate oxide layer 7 is 110-130 nm.

[0027] The thickness of the polysilicon layer 8 is 5000-6000 Å.

[0028] The passivation layer 9 includes a phosphosilicate glass layer and a silicon nitride layer on the front side of the phosphosilicate glass layer. The thickness of the phosphosilicate glass layer is 3500-4500Å, and the thickness of the silicon nitride layer is 4500-4500Å.

[0029] The material of the front metal layer 10 is aluminum, and the thickness of the front metal layer 10 is 4-5 μm.

[0030] The utility model forms an N++ type inner ring source region 5-1 and an N++ type outer ring source region 5-2 on the front of the P+ type well region 4, forms an N+ type inner ring source region 6-1 on the back of the N++ type inner ring source region 5-1, and forms an N+ type outer ring source region 6-2 on the back of the N++ type outer ring source region 5-2. The layout of the P+ type well region 4 doped with different concentrations is formed intermittently, and the current-temperature relationship of the Vgs (i.e., gate-source threshold voltage) and Id (i.e., drain DC current) of the power MOSFET device is reconstructed, thereby enhancing the device forward bias safe operating area FBSOA, improving the source structure of the power MOSFET device, so that the power MOSFET device is more suitable for use in a linear mode, and is suitable for application fields such as electronic loads, audio power amplifiers, linear regulators, and ultrasonic high-frequency surgical integrated systems.

Claims

1. A power MOSFET device, comprising an N-type substrate (3), an N+ type epitaxial layer (2) formed on the back side of the N-type substrate (3), a back side metal layer (1) formed on the back side of the N+ type epitaxial layer (2), and the back side metal layer (1) is led out to form a drain (D); A circular P+ type well region (4) is formed downwardly on the front side of the N- type substrate (3), wherein: An N++ type inner ring source region (5-1) and an N++ type outer ring source region (5-2) are formed on the front side of the P+ type well region (4) downward, an N+ type inner ring source region (6-1) is formed on the back side of the N++ type inner ring source region (5-1), an N+ type outer ring source region (6-2) is formed on the back side of the N++ type outer ring source region (5-2), a gate oxide layer (7) and a front metal layer (10) are formed on the front side of the N- type substrate (3) upward, and the front metal layer (10) is led out to form a source (S), The front metal layer (10) contacts a portion of the N++ type inner ring source region (5-1) and a portion of the N++ type outer ring source region (5-2); the gate oxide layer (7) contacts the remaining portion of the N++ type inner ring source region (5-1) and the remaining portion of the N++ type outer ring source region (5-2); a polysilicon layer (8) is formed upward on the front surface of the gate oxide layer (7); the polysilicon layer (8) is led out to form a gate (G); and a passivation layer (9) is formed between the polysilicon layer (8) and the front metal layer (10); The ion implantation concentration of the N+ type epitaxial layer (2) is greater than the ion implantation concentration of the N- type substrate (3); The ion implantation concentration of the N++ type inner ring source region (5-1) is greater than the ion implantation concentration of the N+ type inner ring source region (6-1), and the ion implantation concentration of the N++ type outer ring source region (5-2) is greater than the ion implantation concentration of the N+ type outer ring source region (6-2).

2. The power MOSFET device according to claim 1, wherein: The back metal layer (1) comprises a metal titanium layer, a metal nickel layer and a metal silver layer; the front side of the metal titanium layer is connected to the back side of the N+ type epitaxial layer (2); the back side of the metal titanium layer is connected to the front side of the metal nickel layer; and the back side of the metal nickel layer is connected to the front side of the metal silver layer.

3. The power MOSFET device according to claim 2, characterized in that: The thickness of the metal titanium layer is 400-600Å, the thickness of the metal nickel layer is 4500-5500Å, and the thickness of the metal silver layer is 5500-6500Å.

4. The power MOSFET device according to claim 1, wherein: The thickness of the N+ type epitaxial layer (2) is 50-70 μm.

5. The power MOSFET device according to claim 1, wherein: The thickness of the N-type substrate (3) is 120-140 μm.

6. The power MOSFET device according to claim 1, wherein: The thickness of the gate oxide layer (7) is 110-130 nm.

7. The power MOSFET device according to claim 1, characterized in that: The thickness of the polysilicon layer (8) is 5000-6000 Å.

8. The power MOSFET device according to claim 1, characterized in that: The passivation layer (9) comprises a phosphosilicate glass layer and a silicon nitride layer on the front side of the phosphosilicate glass layer, the thickness of the phosphosilicate glass layer is 3500-4500Å, and the thickness of the silicon nitride layer is 4500-4500Å.

9. The power MOSFET device according to claim 1, wherein: The material of the front metal layer (10) is aluminum, and the thickness of the front metal layer (10) is 4-5 μm.

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