Intelligent lock charging detection circuit

Abstract

The utility model relates to an intelligent lock charging detection circuit, which is used for charging detection of various intelligent lock batteries, and is characterized in that a battery port scanning detection circuit, a battery positive port control circuit and a battery negative port control circuit are connected in parallel between a control chip and a battery connecting end and respectively comprise four circuit channels with the same structure; the four circuit channels are respectively connected to four ports of the battery, and the control chip realizes port scanning, battery charging and battery detection functions of the four ports of the battery by respectively controlling the on-off of the four circuit channels. The intelligent lock charging detection circuit can automatically recognize the positive electrode and the negative electrode of the battery, self-adaptive recognition of a battery port is achieved, and the intelligent charging detection circuit can be applied to intelligent lock batteries of various models. After charging is completed, the battery port scanning detection circuit detects the state of the battery, and the state of the battery is displayed outwards through the battery state indicating circuit, so that people can visually know the electric quantity and the working state of the battery.

Description

Technical Field

[0001] The utility model relates to the technical field of smart lock rechargeable batteries, and in particular to a smart lock charging detection circuit. Background Art

[0002] Smart door lock is a technologically advanced composite lock that realizes the locking function by identifying the user's fingerprint, password or iris information. It is not only safe and convenient, but also more intelligent and simple to manage.

[0003] The battery of a smart door lock is usually a rechargeable battery. Due to the wide variety of smart locks on the market, the models and types of rechargeable batteries used are different, so the positive and negative terminals of the batteries are set at different locations. Therefore, the battery of a smart door lock needs to be charged with a matching charging device, which brings inconvenience to the user when the charging device fails or is lost. In addition, the existing charging device can only be used to charge the battery and cannot determine the working status of the battery. Utility Model Content

[0004] In view of this, it is necessary to provide a smart lock charging detection circuit that automatically detects the polarity of the battery port and achieves adaptive matching.

[0005] A smart lock charging detection circuit is used for charging detection of various smart lock batteries, including a control chip U7, a battery port scanning detection circuit, a battery positive port control circuit, a battery negative port control circuit and a status indication circuit, wherein the battery port scanning detection circuit, the battery positive port control circuit and the battery negative port control circuit are connected in parallel between the control chip and the battery connection end, the battery port scanning detection circuit, the battery positive port control circuit and the battery negative port control circuit respectively include four circuit channels with the same structure, and the four circuit channels are respectively connected to the four ports of the battery, and the control chip realizes port scanning, battery charging and battery detection functions for the four ports of the battery by respectively controlling the on and off of the four circuit channels; the status indication circuit includes a battery status indication circuit, and the battery status indication circuit is used to indicate the battery power and working status.

[0006] Preferably, the control chip U7 includes four battery positive control terminals, four battery negative control terminals, a battery positive port detection terminal and a battery negative port detection terminal, the four battery positive control terminals are respectively a first battery positive control pin V_ctrl1, a second battery positive control pin V_ctrl2, a third battery positive control pin V_ctrl3 and a fourth battery positive control pin V_ctrl4, the four battery negative control terminals are respectively a first battery negative control pin G_ctrl1, a second battery negative control pin G_ctrl2, a third battery negative control pin G_ctrl3 and a fourth battery negative control pin G_ctrl4, the battery positive port detection terminal includes a battery voltage sampling circuit, and the battery negative port detection terminal includes a battery negative sampling circuit.

[0007] Preferably, the battery voltage sampling circuit includes a thirty-second resistor R32 and a thirty-third resistor R33 connected in series, the midpoint of the thirty-second resistor R32 and the thirty-third resistor R33 is connected to the positive port detection pin VBAT DET of the control chip U7, the free end of the thirty-second resistor R32 is connected to the positive power supply VBAT, and the free end of the thirty-third resistor R33 is connected to the negative power supply VSS.

[0008] Preferably, the battery negative electrode sampling circuit includes a seventeenth P-channel MOS transistor Q17, a thirty-fourth resistor R34, a thirty-fifth resistor R35, a thirty-sixth resistor R36 and a thirty-seventh resistor R37, the source of the seventeenth P-channel MOS transistor Q17 is connected to the positive power supply electrode VBAT, the drain of the seventeenth P-channel MOS transistor Q17 is connected to the thirty-fourth resistor R34 and the thirty-fifth resistor R35 arranged in series, the midpoint of the thirty-fourth resistor R34 and the thirty-fifth resistor R35 is connected to the negative electrode port detection pin BGND_DET of the control chip U7, the free end of the thirty-fifth resistor R35 is connected to the negative power supply electrode VSS, the gate of the seventeenth P-channel MOS transistor Q17 is connected to the midpoint of the thirty-sixth resistor R36 and the thirty-seventh resistor R37 arranged in series, the free end of the thirty-sixth resistor R36 is connected to the source of the seventeenth P-channel MOS transistor Q17, and the free end of the thirty-seventh resistor R37 is grounded.

[0009] Preferably, the battery port scanning detection circuit includes four parallel battery port scanning detection channels, each of which is connected to one of the battery positive control terminals, one of the battery negative control terminals and a battery port, for detecting the polarity of the battery port and the battery status; the four battery port scanning detection channels include a first battery port scanning detection channel, a second battery port scanning detection channel, a third battery port scanning detection channel and a fourth battery port scanning detection channel.

[0010] Preferably, the first battery port scanning detection channel includes an eighth one-into-two-way diode B8, an eighth N-channel MOS transistor Q8, a twelfth P-channel MOS transistor Q12 and a sixteenth N-channel MOS transistor Q16, the third port of the eighth one-into-two-way diode B8 is connected to the first battery port, the second port of the eighth one-into-two-way diode B8 is connected to the source of the twelfth P-channel MOS transistor Q12, the drain of the twelfth P-channel MOS transistor Q12 is connected to the positive power supply VBAT, the gate of the twelfth P-channel MOS transistor Q12 is connected to the drain of the sixteenth N-channel MOS transistor Q16 through a twenty-fourth resistor R24, and a twentieth resistor R2 is connected between the gate and the source of the twelfth P-channel MOS transistor Q12. 0, the source of the sixteenth N-channel MOS transistor Q16 is connected to the negative power supply VSS, the gate of the sixteenth N-channel MOS transistor Q16 is connected to the first battery positive electrode control pin V_ctrl1, and the gate of the sixteenth N-channel MOS transistor Q16 is also connected to the negative power supply VSS through the twenty-eighth resistor 28; the first port of the eighth one-to-two-way diode B8 is connected to the source of the eighth N-channel MOS transistor Q8, the drain of the eighth N-channel MOS transistor Q8 is connected to the negative power supply VSS, the gate of the eighth N-channel MOS transistor Q8 is connected to the first battery negative electrode control pin G_ctrl1, and the gate of the eighth N-channel MOS transistor Q8 is also connected to the negative power supply VSS through the sixteenth resistor R16;

[0011] The second battery port scanning detection channel includes a seventh one-into-two-way diode B7, a seventh N-channel MOS transistor Q7, an eleventh P-channel MOS transistor Q11 and a fifteenth N-channel MOS transistor Q15, the third port of the seventh one-into-two-way diode B7 is connected to the second battery port, the second port of the seventh one-into-two-way diode B7 is connected to the source of the eleventh P-channel MOS transistor Q11, the drain of the eleventh P-channel MOS transistor Q11 is connected to the positive power supply VBAT, the gate of the eleventh P-channel MOS transistor Q11 is connected to the drain of the fifteenth N-channel MOS transistor Q15 through a twenty-third resistor R23, and a nineteenth resistor R19 is connected between the gate and the source of the eleventh P-channel MOS transistor Q11. The source of the fifteenth N-channel MOS transistor Q15 is connected to the negative power supply VSS, the gate of the fifteenth N-channel MOS transistor Q15 is connected to the second battery positive electrode control pin V_ctrl2, and the gate of the fifteenth N-channel MOS transistor Q15 is also connected to the negative power supply VSS through the twenty-seventh resistor R27; the first port of the seventh one-to-two-way diode B7 is connected to the source of the seventh N-channel MOS transistor Q7, the drain of the seventh N-channel MOS transistor Q7 is connected to the negative power supply VSS, the gate of the seventh N-channel MOS transistor Q7 is connected to the second battery negative electrode control pin G_ctrl2, and the gate of the seventh N-channel MOS transistor Q7 is also connected to the negative power supply VSS through the fifteenth resistor R15;

[0012] The third battery port scanning detection channel includes a sixth one-into-two-way diode B6, a sixth N-channel MOS transistor Q6, a tenth P-channel MOS transistor Q10 and a fourteenth N-channel MOS transistor Q14, the third port of the sixth one-into-two-way diode B6 is connected to the third battery port, the second port of the sixth one-into-two-way diode B6 is connected to the source of the tenth P-channel MOS transistor Q10, the drain of the tenth P-channel MOS transistor Q10 is connected to the positive power supply VBAT, the gate of the tenth P-channel MOS transistor Q10 is connected to the drain of the fourteenth N-channel MOS transistor Q14 through a twenty-second resistor R22, an eighteenth resistor R18 is connected between the gate and the source of the tenth P-channel MOS transistor Q10, and the The source of the fourteenth N-channel MOS transistor Q14 is connected to the negative power supply VSS, the gate of the fourteenth N-channel MOS transistor Q14 is connected to the third battery positive electrode control pin V_ctrl3, and the gate of the fourteenth N-channel MOS transistor Q14 is also connected to the negative power supply VSS through the twenty-sixth resistor R26; the first port of the sixth one-to-two-way diode B6 is connected to the source of the sixth N-channel MOS transistor Q6, the drain of the sixth N-channel MOS transistor Q6 is connected to the negative power supply VSS, the gate of the sixth N-channel MOS transistor Q6 is connected to the third battery negative electrode control pin G_ctrl3, and the gate of the sixth N-channel MOS transistor Q6 is also connected to the negative power supply VSS through the fourteenth resistor R14;

[0013] The fourth battery port scanning detection channel includes a fifth one-into-two-way diode B5, a fifth N-channel MOS transistor Q5, a ninth P-channel MOS transistor Q9 and a thirteenth N-channel MOS transistor Q13, the third port of the fifth one-into-two-way diode B5 is connected to the fourth battery port, the second port of the fifth one-into-two-way diode B5 is connected to the source of the ninth P-channel MOS transistor Q9, the drain of the ninth P-channel MOS transistor Q9 is connected to the positive power supply VBAT, the gate of the ninth P-channel MOS transistor Q9 is connected to the drain of the thirteenth N-channel MOS transistor Q13 through a twenty-first resistor R21, a seventeenth resistor R17 is connected between the gate and the source of the ninth P-channel MOS transistor Q9, and the thirteenth N-channel MOS transistor Q13 is connected to the drain of the ninth P-channel MOS transistor Q9 through a twenty-first resistor R21. The source of the N-channel MOS transistor Q13 is connected to the negative power supply VSS, the gate of the thirteenth N-channel MOS transistor Q13 is connected to the fourth battery positive electrode control pin V_ctrl4, and the gate of the thirteenth N-channel MOS transistor Q13 is also connected to the negative power supply VSS through the twenty-fifth resistor R25; the first port of the fifth one-to-two-way diode B5 is connected to the source of the fifth N-channel MOS transistor Q5, the drain of the fifth N-channel MOS transistor Q5 is connected to the negative power supply VSS, the gate of the fifth N-channel MOS transistor Q5 is connected to the fourth battery negative electrode control pin G_ctrl4, and the gate of the fifth N-channel MOS transistor Q5 is also connected to the negative power supply VSS through the thirteenth resistor R13.

[0014] Preferably, the battery positive port control circuit includes four parallel battery positive port control channels, namely a first battery positive port control channel, a second battery positive port control channel, a third battery positive port control channel and a fourth battery positive port control channel;

[0015] The first battery positive electrode port control channel includes an eighteenth P-channel MOS transistor Q18, a twenty-second N-channel MOS transistor Q22 and a fourth MOS internal diode D4, the source of the fourth MOS internal diode D4 is connected to the first battery port, the drain of the fourth MOS internal diode D4 is connected to the drain of the eighteenth P-channel MOS transistor Q18, the source of the eighteenth P-channel MOS transistor Q18 is connected to the positive electrode PV of the charging power supply, the gate of the eighteenth P-channel MOS transistor Q18 is connected to the drain of the twenty-second N-channel MOS transistor Q22 through a forty-third resistor R43, a forty-second resistor R42 is connected between the source and the gate of the eighteenth P-channel MOS transistor Q18, the gate of the twenty-second N-channel MOS transistor Q22 is connected to the first battery positive electrode control pin V_ctrl1, a fiftieth resistor R50 is connected between the source and the gate of the twenty-second N-channel MOS transistor Q22, and the source of the twenty-second N-channel MOS transistor Q22 is connected to the negative electrode VSS of the power supply;

[0016] The second battery positive electrode port control channel includes a nineteenth P-channel MOS transistor Q19, a twenty-third N-channel MOS transistor Q23 and a fifth MOS internal diode D5, the source of the fifth MOS internal diode D5 is connected to the second battery port, the drain of the fifth MOS internal diode D5 is connected to the drain of the nineteenth P-channel MOS transistor Q19, the source of the nineteenth P-channel MOS transistor Q19 is connected to the positive electrode PV of the charging power supply, the gate of the nineteenth P-channel MOS transistor Q19 is connected to the drain of the twenty-third N-channel MOS transistor Q23 through a forty-fifth resistor R45, a forty-fourth resistor R44 is connected between the source and the gate of the nineteenth P-channel MOS transistor Q19, the gate of the twenty-third N-channel MOS transistor Q23 is connected to the second battery positive electrode control pin V_ctrl2, a fifty-first resistor R51 is connected between the source and the gate of the twenty-third N-channel MOS transistor Q23, and the source of the twenty-third N-channel MOS transistor Q23 is connected to the negative electrode VSS of the power supply;

[0017] The third battery positive electrode port control channel includes a twentieth P-channel MOS transistor Q20, a twenty-fourth N-channel MOS transistor Q24 and a sixth MOS internal diode D6, the source of the sixth MOS internal diode D6 is connected to the third battery port, the drain of the sixth MOS internal diode D6 is connected to the drain of the twentieth P-channel MOS transistor Q20, the source of the twentieth P-channel MOS transistor Q20 is connected to the charging power supply positive electrode PV, the gate of the twentieth P-channel MOS transistor Q20 is connected to the drain of the twentieth N-channel MOS transistor Q24 through a forty-seventh resistor R47, a forty-sixth resistor R46 is connected between the source and the gate of the twentieth P-channel MOS transistor Q20, the gate of the twentieth N-channel MOS transistor Q24 is connected to the third battery positive electrode control pin V_ctrl3, a fifty-second resistor R52 is connected between the source and the gate of the twentieth N-channel MOS transistor Q24, and the source of the twentieth N-channel MOS transistor Q24 is connected to the negative power supply VSS;

[0018] The fourth battery positive electrode port control channel includes a twenty-first P-channel MOS transistor Q21, a twenty-fifth N-channel MOS transistor Q25 and a seventh MOS internal diode D7, the source of the seventh MOS internal diode D7 is connected to the fourth battery port, the drain of the seventh MOS internal diode D7 is connected to the drain of the twenty-first P-channel MOS transistor Q21, the source of the twenty-first P-channel MOS transistor Q21 is connected to the charging power supply positive electrode PV, the gate of the twenty-first P-channel MOS transistor Q21 is connected to the drain of the twenty-fifth N-channel MOS transistor Q25 through a forty-ninth resistor R49, a forty-eighth resistor R48 is connected between the source and the gate of the twenty-first P-channel MOS transistor Q21, the gate of the twenty-fifth N-channel MOS transistor Q25 is connected to the fourth battery positive electrode control pin V_ctrl4, a fifty-third resistor R53 is connected between the source and the gate of the twenty-fifth N-channel MOS transistor Q25, and the source of the twenty-fifth N-channel MOS transistor Q25 is connected to the negative power supply VSS.

[0019] Preferably, the battery negative electrode port control circuit includes four parallel battery negative electrode port control channels, namely a first battery negative electrode port control channel, a second battery negative electrode port control channel, a third battery negative electrode port control channel and a fourth battery negative electrode port control channel;

[0020] The first battery negative electrode port control channel includes a first N-channel MOS transistor U3, a source of the first N-channel MOS transistor U3 is connected to the first battery port, a gate of the first N-channel MOS transistor U3 is connected to the first battery negative electrode control pin G_ctrl1, and a gate of the first N-channel MOS transistor U3 is also connected to the negative power supply VSS through a thirty-eighth resistor R38;

[0021] The second battery negative electrode port control channel includes a second N-channel MOS transistor U4, the source of the second N-channel MOS transistor U4 is connected to the second battery port, the gate of the second N-channel MOS transistor U4 is connected to the second battery negative electrode control pin G_ctrl2, and the gate of the second N-channel MOS transistor U4 is also connected to the negative power supply VSS through a thirty-ninth resistor R39;

[0022] The third battery negative electrode port control channel includes a third N-channel MOS transistor U5, the source of which is connected to the third battery port, the gate of which is connected to the third battery negative electrode control pin G_ctrl3, and the gate of which is also connected to the negative power supply VSS through a fortieth resistor R40;

[0023] The fourth battery negative electrode port control channel includes a fourth N-channel MOS tube U6, a source of the fourth N-channel MOS tube U6 is connected to the fourth battery port, a gate of the fourth N-channel MOS tube U6 is connected to the fourth battery negative electrode control pin G_ctrl4, and a gate of the fourth N-channel MOS tube U6 is also connected to the negative power supply VSS through a thirty-eighth resistor R38.

[0024] Preferably, it also includes a charging control circuit, which includes a charging control boost chip and a charging voltage sampling circuit. The charging control boost chip is connected to each port of the battery to be charged through the battery positive port control circuit and the battery negative port control circuit, and the control chip U7 controls the on and off of each battery port to realize battery charging; the input end of the charging voltage sampling circuit is connected to the charging control boost chip, and the output end of the charging voltage sampling circuit is connected to the control chip U7. The charging voltage sampling circuit is used for the control chip U7 to monitor the charging voltage.

[0025] Preferably, the battery status indication circuit includes an SMD patch lamp bead D2, the first pin of the SMD patch lamp bead D2 is connected to the BLED pin of the control chip through a twenty-ninth resistor R29, the third pin of the SMD patch lamp bead D2 is connected to the RLED pin of the control chip through a thirtieth resistor R30, the fifth pin of the SMD patch lamp bead D2 is connected to the GLED pin of the control chip through a thirty-first resistor R31, and the second, fourth and sixth pins of the SMD patch lamp bead D2 are connected to the positive electrode of the power supply VBAT; the battery power is detected after charging is completed, and the SMD patch lamp bead D2 uses indicator lights of different colors to indicate different battery power values ​​and battery working status.

[0026] In the above-mentioned smart lock charging detection circuit, the battery port scanning detection circuit is arranged between the control chip U7 and the battery. The control chip U7 has four battery positive control terminals and four battery negative control terminals. The battery port scanning detection circuit scans and detects the four ports of the battery, and the identified battery positive pole is connected to the battery positive control terminal, and the identified battery negative pole is connected to the battery negative control terminal; the battery positive port control circuit and the battery negative port control circuit are also arranged between the four battery positive control terminals and the four battery negative control terminals and the four ports of the battery. When charging, the control chip U7 only connects the corresponding battery positive control terminal and the battery negative control terminal to realize battery charging. The smart lock charging detection circuit can automatically identify the positive and negative poles of the battery, realize adaptive identification of the battery port, and enable the smart charging detection circuit to be applied to various models of smart lock batteries. After charging is completed, the battery port scanning detection circuit detects the battery status and displays it to the outside through the battery status indication circuit, so that people can intuitively understand the battery power and working status. The utility model has a simple circuit structure, is easy to produce, has a low cost and is convenient for promotion. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a principle block diagram of the smart lock charging detection circuit of the embodiment of the utility model.

[0028] Figure 2 It is a circuit structure diagram of the control chip U7 of the smart lock charging detection circuit of the embodiment of the utility model.

[0029] Figure 3 It is a circuit structure diagram of a battery port scanning detection circuit of a smart lock charging detection circuit according to an embodiment of the utility model.

[0030] Figure 4 It is a circuit structure diagram of a battery positive port control circuit of a smart lock charging detection circuit according to an embodiment of the utility model.

[0031] Figure 5 It is a circuit structure diagram of a battery negative terminal port control circuit of a smart lock charging detection circuit according to an embodiment of the utility model.

[0032] Figure 6 It is a circuit structure diagram of a battery status indication circuit of a smart lock charging detection circuit according to an embodiment of the utility model. DETAILED DESCRIPTION

[0033] The present invention will be described in detail below with reference to specific embodiments and accompanying drawings.

[0034] See also Figure 1, showing a smart lock charging detection circuit provided by an embodiment of the utility model, which is used for charging detection of various smart lock batteries, including a control chip U7, a battery port scanning detection circuit, a battery positive port control circuit, a battery negative port control circuit and a status indication circuit, wherein the battery port scanning detection circuit, the battery positive port control circuit and the battery negative port control circuit are connected in parallel between the control chip and the battery connection end, the battery port scanning detection circuit, the battery positive port control circuit and the battery negative port control circuit respectively include four circuit channels with the same structure, and the four circuit channels are respectively connected to the four ports of the battery, and the control chip realizes the port scanning, battery charging and battery detection functions of the four ports of the battery by respectively controlling the on and off of the four circuit channels; the status indication circuit includes a battery status indication circuit, and the battery status indication circuit is used to indicate the battery power and working status.

[0035] Preferably, see Figure 2 The control chip U7 includes four battery positive control terminals, four battery negative control terminals, a battery positive port detection terminal and a battery negative port detection terminal. The four battery positive control terminals are respectively a first battery positive control pin V_ctrl1, a second battery positive control pin V_ctrl2, a third battery positive control pin V_ctrl3 and a fourth battery positive control pin V_ctrl4. The four battery negative control terminals are respectively a first battery negative control pin G_ctrl1, a second battery negative control pin G_ctrl2, a third battery negative control pin G_ctrl3 and a fourth battery negative control pin G_ctrl4. The battery positive port detection terminal includes a battery voltage sampling circuit, and the battery negative port detection terminal includes a battery negative sampling circuit.

[0036] Preferably, the battery voltage sampling circuit includes a thirty-second resistor R32 and a thirty-third resistor R33 connected in series, the midpoint of the thirty-second resistor R32 and the thirty-third resistor R33 is connected to the positive port detection pin VBAT DET of the control chip U7, the free end of the thirty-second resistor R32 is connected to the positive power supply VBAT, and the free end of the thirty-third resistor R33 is connected to the negative power supply VSS.

[0037] Preferably, the battery negative electrode sampling circuit includes a seventeenth P-channel MOS transistor Q17, a thirty-fourth resistor R34, a thirty-fifth resistor R35, a thirty-sixth resistor R36 and a thirty-seventh resistor R37, the source of the seventeenth P-channel MOS transistor Q17 is connected to the positive power supply electrode VBAT, the drain of the seventeenth P-channel MOS transistor Q17 is connected to the thirty-fourth resistor R34 and the thirty-fifth resistor R35 arranged in series, the midpoint of the thirty-fourth resistor R34 and the thirty-fifth resistor R35 is connected to the negative electrode port detection pin BGND_DET of the control chip U7, the free end of the thirty-fifth resistor R35 is connected to the negative power supply electrode VSS, the gate of the seventeenth P-channel MOS transistor Q17 is connected to the midpoint of the thirty-sixth resistor R36 and the thirty-seventh resistor R37 arranged in series, the free end of the thirty-sixth resistor R36 is connected to the source of the seventeenth P-channel MOS transistor Q17, and the free end of the thirty-seventh resistor R37 is grounded.

[0038] Specifically, the thirty-second resistor R32, the thirty-third resistor R33, the thirty-fourth resistor R34, and the thirty-fifth resistor R35 are signal configuration sampling resistors, and U7 is a control chip for allocating control signals and detection signals, thereby controlling the on and off of each circuit channel.

[0039] Preferably, see Figure 3 The battery port scanning detection circuit includes four parallel battery port scanning detection channels, each of which is connected to one of the battery positive control terminals, one of the battery negative control terminals and a battery port, and is used to detect the polarity of the battery port and the battery status; the four battery port scanning detection channels include a first battery port scanning detection channel, a second battery port scanning detection channel, a third battery port scanning detection channel and a fourth battery port scanning detection channel.

[0040] Preferably, the first battery port scanning detection channel includes an eighth one-into-two-way diode B8, an eighth N-channel MOS transistor Q8, a twelfth P-channel MOS transistor Q12 and a sixteenth N-channel MOS transistor Q16, the third port of the eighth one-into-two-way diode B8 is connected to the first battery port, the second port of the eighth one-into-two-way diode B8 is connected to the source of the twelfth P-channel MOS transistor Q12, the drain of the twelfth P-channel MOS transistor Q12 is connected to the positive power supply VBAT, the gate of the twelfth P-channel MOS transistor Q12 is connected to the drain of the sixteenth N-channel MOS transistor Q16 through a twenty-fourth resistor R24, and a twentieth resistor R2 is connected between the gate and the source of the twelfth P-channel MOS transistor Q12. 0, the source of the sixteenth N-channel MOS transistor Q16 is connected to the negative power supply VSS, the gate of the sixteenth N-channel MOS transistor Q16 is connected to the first battery positive electrode control pin V_ctrl1, and the gate of the sixteenth N-channel MOS transistor Q16 is also connected to the negative power supply VSS through the twenty-eighth resistor 28; the first port of the eighth one-to-two-way diode B8 is connected to the source of the eighth N-channel MOS transistor Q8, the drain of the eighth N-channel MOS transistor Q8 is connected to the negative power supply VSS, the gate of the eighth N-channel MOS transistor Q8 is connected to the first battery negative electrode control pin G_ctrl1, and the gate of the eighth N-channel MOS transistor Q8 is also connected to the negative power supply VSS through the sixteenth resistor R16;

[0041] The second battery port scanning detection channel includes a seventh one-into-two-way diode B7, a seventh N-channel MOS transistor Q7, an eleventh P-channel MOS transistor Q11 and a fifteenth N-channel MOS transistor Q15, the third port of the seventh one-into-two-way diode B7 is connected to the second battery port, the second port of the seventh one-into-two-way diode B7 is connected to the source of the eleventh P-channel MOS transistor Q11, the drain of the eleventh P-channel MOS transistor Q11 is connected to the positive power supply VBAT, the gate of the eleventh P-channel MOS transistor Q11 is connected to the drain of the fifteenth N-channel MOS transistor Q15 through a twenty-third resistor R23, and a nineteenth resistor R19 is connected between the gate and the source of the eleventh P-channel MOS transistor Q11. The source of the fifteenth N-channel MOS transistor Q15 is connected to the negative power supply VSS, the gate of the fifteenth N-channel MOS transistor Q15 is connected to the second battery positive electrode control pin V_ctrl2, and the gate of the fifteenth N-channel MOS transistor Q15 is also connected to the negative power supply VSS through the twenty-seventh resistor R27; the first port of the seventh one-to-two-way diode B7 is connected to the source of the seventh N-channel MOS transistor Q7, the drain of the seventh N-channel MOS transistor Q7 is connected to the negative power supply VSS, the gate of the seventh N-channel MOS transistor Q7 is connected to the second battery negative electrode control pin G_ctrl2, and the gate of the seventh N-channel MOS transistor Q7 is also connected to the negative power supply VSS through the fifteenth resistor R15;

[0042] The third battery port scanning detection channel includes a sixth one-into-two-way diode B6, a sixth N-channel MOS transistor Q6, a tenth P-channel MOS transistor Q10 and a fourteenth N-channel MOS transistor Q14, the third port of the sixth one-into-two-way diode B6 is connected to the third battery port, the second port of the sixth one-into-two-way diode B6 is connected to the source of the tenth P-channel MOS transistor Q10, the drain of the tenth P-channel MOS transistor Q10 is connected to the positive power supply VBAT, the gate of the tenth P-channel MOS transistor Q10 is connected to the drain of the fourteenth N-channel MOS transistor Q14 through a twenty-second resistor R22, an eighteenth resistor R18 is connected between the gate and the source of the tenth P-channel MOS transistor Q10, and the The source of the fourteenth N-channel MOS transistor Q14 is connected to the negative power supply VSS, the gate of the fourteenth N-channel MOS transistor Q14 is connected to the third battery positive electrode control pin V_ctrl3, and the gate of the fourteenth N-channel MOS transistor Q14 is also connected to the negative power supply VSS through the twenty-sixth resistor R26; the first port of the sixth one-to-two-way diode B6 is connected to the source of the sixth N-channel MOS transistor Q6, the drain of the sixth N-channel MOS transistor Q6 is connected to the negative power supply VSS, the gate of the sixth N-channel MOS transistor Q6 is connected to the third battery negative electrode control pin G_ctrl3, and the gate of the sixth N-channel MOS transistor Q6 is also connected to the negative power supply VSS through the fourteenth resistor R14;

[0043] The fourth battery port scanning detection channel includes a fifth one-into-two-way diode B5, a fifth N-channel MOS transistor Q5, a ninth P-channel MOS transistor Q9 and a thirteenth N-channel MOS transistor Q13, the third port of the fifth one-into-two-way diode B5 is connected to the fourth battery port, the second port of the fifth one-into-two-way diode B5 is connected to the source of the ninth P-channel MOS transistor Q9, the drain of the ninth P-channel MOS transistor Q9 is connected to the positive power supply VBAT, the gate of the ninth P-channel MOS transistor Q9 is connected to the drain of the thirteenth N-channel MOS transistor Q13 through a twenty-first resistor R21, a seventeenth resistor R17 is connected between the gate and the source of the ninth P-channel MOS transistor Q9, and the thirteenth N-channel MOS transistor Q13 is connected to the drain of the ninth P-channel MOS transistor Q9 through a twenty-first resistor R21. The source of the N-channel MOS transistor Q13 is connected to the negative power supply VSS, the gate of the thirteenth N-channel MOS transistor Q13 is connected to the fourth battery positive electrode control pin V_ctrl4, and the gate of the thirteenth N-channel MOS transistor Q13 is also connected to the negative power supply VSS through the twenty-fifth resistor R25; the first port of the fifth one-to-two-way diode B5 is connected to the source of the fifth N-channel MOS transistor Q5, the drain of the fifth N-channel MOS transistor Q5 is connected to the negative power supply VSS, the gate of the fifth N-channel MOS transistor Q5 is connected to the fourth battery negative electrode control pin G_ctrl4, and the gate of the fifth N-channel MOS transistor Q5 is also connected to the negative power supply VSS through the thirteenth resistor R13.

[0044] Specifically, B5, B6, B7, and B8 are diodes that serve to block reverse current. B5 is a one-to-two-way diode at port 4, B6 is a one-to-two-way diode at port 3, B7 is a one-to-two-way diode at port 2, and B8 is a one-to-two-way diode at port 1.

[0045] Q5, Q6, Q7, and Q8 are N-channel MOS tubes, which act as switch channels. The signals G_crtl1, G_crtl2, G_crtl3, and G_crtl4 are used to control the switches of Q8, Q7, Q6, and Q5, and provide the negative electrode signal of the battery to the main control. The resistors R13, R14, R15, and R16 act as stabilizing signals.

[0046] Q9, Q10, Q11, and Q12 are P-channel MOS tubes, which act as switch channels. Q13, Q14, Q15, and Q16 are N-channel MOS tubes, which control the opening of Q9, Q10, Q11, and Q12 respectively. Resistors R17 and R21 are voltage-dividing resistors at the input end of Q9, which cooperate with Q13 to control Q9, and control the switch of Q9 through signal V_crtl4 to provide the control chip U7 with the positive battery signal. The control of other channels is the same. Resistors R25, R26, R27, and R28 act as signal stabilization.

[0047] Specifically, COM1, COM2, COM3, and COM4 are four interfaces of the battery, and their positive and negative polarities are unknown before scanning and detection. V_ctrl1, V_ctrl2, V_ctrl3, and V_ctr4 are positive signal control terminals, and G_crtl1, G_crtl2, G_crtl3, and G_crtl4 are negative signal control terminals.

[0048] Specifically, when port COM4 is the positive electrode of the battery, the scanning detection signal V_ctr4 outputs a high level, Q13 works, Q9 is turned on, port COM4 is connected, the positive electrode signal VBAT is turned on, and the resistors R32 and R33 in the battery voltage sampling circuit supply power to the positive electrode port detection pin VBAT DET of the control chip U7, see the attached Figure 2 When the main control U7 detects that the signal VBAT_DET is at a high level, it determines that COM4 is the positive pole of the battery. When the main control U7 detects that the signal VBAT_DET is at a low level, it will not determine that it is the positive pole of the battery. The detection of other ports is similar.

[0049] For example, when port COM3 is the negative electrode of the battery, and the scanning detection signal G_crtl3 is at a high level, Q6 is turned on, connected to port COM3, connected to the negative electrode signal VSS, and connected to Q17 through resistor R37. Figure 2 , power the resistors R34 and R35. When the main control U7 detects that the negative port detection pin BGND_DET is at a high level, it determines that COM3 is the negative electrode of the battery. When the main control U7 detects that the signal BGND_DET is at a low level, it will not determine that it is the negative electrode of the battery. The detection of other ports is similar.

[0050] Preferably, see Figure 4 , the battery positive port control circuit includes four parallel battery positive port control channels, namely a first battery positive port control channel, a second battery positive port control channel, a third battery positive port control channel and a fourth battery positive port control channel;

[0051] The first battery positive electrode port control channel includes an eighteenth P-channel MOS transistor Q18, a twenty-second N-channel MOS transistor Q22 and a fourth MOS internal diode D4, the source of the fourth MOS internal diode D4 is connected to the first battery port, the drain of the fourth MOS internal diode D4 is connected to the drain of the eighteenth P-channel MOS transistor Q18, the source of the eighteenth P-channel MOS transistor Q18 is connected to the positive electrode PV of the charging power supply, the gate of the eighteenth P-channel MOS transistor Q18 is connected to the drain of the twenty-second N-channel MOS transistor Q22 through a forty-third resistor R43, a forty-second resistor R42 is connected between the source and the gate of the eighteenth P-channel MOS transistor Q18, the gate of the twenty-second N-channel MOS transistor Q22 is connected to the first battery positive electrode control pin V_ctrl1, a fiftieth resistor R50 is connected between the source and the gate of the twenty-second N-channel MOS transistor Q22, and the source of the twenty-second N-channel MOS transistor Q22 is connected to the negative electrode VSS of the power supply;

[0052] The second battery positive electrode port control channel includes a nineteenth P-channel MOS transistor Q19, a twenty-third N-channel MOS transistor Q23 and a fifth MOS internal diode D5, the source of the fifth MOS internal diode D5 is connected to the second battery port, the drain of the fifth MOS internal diode D5 is connected to the drain of the nineteenth P-channel MOS transistor Q19, the source of the nineteenth P-channel MOS transistor Q19 is connected to the positive electrode PV of the charging power supply, the gate of the nineteenth P-channel MOS transistor Q19 is connected to the drain of the twenty-third N-channel MOS transistor Q23 through a forty-fifth resistor R45, a forty-fourth resistor R44 is connected between the source and the gate of the nineteenth P-channel MOS transistor Q19, the gate of the twenty-third N-channel MOS transistor Q23 is connected to the second battery positive electrode control pin V_ctrl2, a fifty-first resistor R51 is connected between the source and the gate of the twenty-third N-channel MOS transistor Q23, and the source of the twenty-third N-channel MOS transistor Q23 is connected to the negative electrode VSS of the power supply;

[0053] The third battery positive electrode port control channel includes a twentieth P-channel MOS transistor Q20, a twenty-fourth N-channel MOS transistor Q24 and a sixth MOS internal diode D6, the source of the sixth MOS internal diode D6 is connected to the third battery port, the drain of the sixth MOS internal diode D6 is connected to the drain of the twentieth P-channel MOS transistor Q20, the source of the twentieth P-channel MOS transistor Q20 is connected to the charging power supply positive electrode PV, the gate of the twentieth P-channel MOS transistor Q20 is connected to the drain of the twentieth N-channel MOS transistor Q24 through a forty-seventh resistor R47, a forty-sixth resistor R46 is connected between the source and the gate of the twentieth P-channel MOS transistor Q20, the gate of the twentieth N-channel MOS transistor Q24 is connected to the third battery positive electrode control pin V_ctrl3, a fifty-second resistor R52 is connected between the source and the gate of the twentieth N-channel MOS transistor Q24, and the source of the twentieth N-channel MOS transistor Q24 is connected to the negative power supply VSS;

[0054] The fourth battery positive electrode port control channel includes a twenty-first P-channel MOS transistor Q21, a twenty-fifth N-channel MOS transistor Q25 and a seventh MOS internal diode D7, the source of the seventh MOS internal diode D7 is connected to the fourth battery port, the drain of the seventh MOS internal diode D7 is connected to the drain of the twenty-first P-channel MOS transistor Q21, the source of the twenty-first P-channel MOS transistor Q21 is connected to the charging power supply positive electrode PV, the gate of the twenty-first P-channel MOS transistor Q21 is connected to the drain of the twenty-fifth N-channel MOS transistor Q25 through a forty-ninth resistor R49, a forty-eighth resistor R48 is connected between the source and the gate of the twenty-first P-channel MOS transistor Q21, the gate of the twenty-fifth N-channel MOS transistor Q25 is connected to the fourth battery positive electrode control pin V_ctrl4, a fifty-third resistor R53 is connected between the source and the gate of the twenty-fifth N-channel MOS transistor Q25, and the source of the twenty-fifth N-channel MOS transistor Q25 is connected to the negative power supply VSS.

[0055] Specifically, Q18, Q19, Q20, and Q21 are P-channel MOS tubes, which act as switch channels. Q22, Q23, Q24, and Q25 are N-channel MOS tubes, which control the conduction of Q18, Q19, Q20, and Q21 respectively. Resistors R42 and R43 are voltage-dividing resistors at the input end of Q18, which cooperate with Q22 to control Q18, and control the Q18 switch through the signal V_crtl1 to turn on or off the positive electrode of the battery. The control of other channels is the same. Resistors R50, R51, R52, and R53 act as signal stabilization. D4, D5, D6, and D7 use P-channel MOS tubes, which use the internal diodes of the MOS tubes to act as diodes to prevent current reverse flow.

[0056] Preferably, see Figure 5 , the battery negative electrode port control circuit includes four parallel battery negative electrode port control channels, namely a first battery negative electrode port control channel, a second battery negative electrode port control channel, a third battery negative electrode port control channel and a fourth battery negative electrode port control channel;

[0057] The first battery negative electrode port control channel includes a first N-channel MOS transistor U3, a source of the first N-channel MOS transistor U3 is connected to the first battery port, a gate of the first N-channel MOS transistor U3 is connected to the first battery negative electrode control pin G_ctrl1, and a gate of the first N-channel MOS transistor U3 is also connected to the negative power supply VSS through a thirty-eighth resistor R38;

[0058] The second battery negative electrode port control channel includes a second N-channel MOS transistor U4, the source of the second N-channel MOS transistor U4 is connected to the second battery port, the gate of the second N-channel MOS transistor U4 is connected to the second battery negative electrode control pin G_ctrl2, and the gate of the second N-channel MOS transistor U4 is also connected to the negative power supply VSS through a thirty-ninth resistor R39;

[0059] The third battery negative electrode port control channel includes a third N-channel MOS transistor U5, the source of which is connected to the third battery port, the gate of which is connected to the third battery negative electrode control pin G_ctrl3, and the gate of which is also connected to the negative power supply VSS through a fortieth resistor R40;

[0060] The fourth battery negative electrode port control channel includes a fourth N-channel MOS tube U6, a source of the fourth N-channel MOS tube U6 is connected to the fourth battery port, a gate of the fourth N-channel MOS tube U6 is connected to the fourth battery negative electrode control pin G_ctrl4, and a gate of the fourth N-channel MOS tube U6 is also connected to the negative power supply VSS through a thirty-eighth resistor R38.

[0061] Specifically, U3, U4, U5, and U6 are N-channel dual MOS tubes, which are controlled by signals G_crtl1, G_crtl2, G_crtl3, and G_crtl4, respectively, and are connected to the negative terminal of the battery and the negative terminal of the charging power supply.

[0062] Specifically, when it is determined that port COM4 is the positive electrode of the battery, the positive electrode scanning detection stops, the fourth battery positive electrode control pin V_ctrl4 outputs a stable high level, Q25 works, Q21 is turned on, and the charging power supply positive electrode PV is connected to the battery positive electrode COM4.

[0063] When it is determined that port COM3 is the negative electrode of the battery, the negative electrode scanning detection stops, the third battery negative electrode control pin G_crtl3 outputs a stable high level, and U5 works. Figure 5 , connect the negative pole of the charging power supply to the negative pole of the battery COM3, and prepare for charging. Connect the charging adapter to charge the battery.

[0064] When the battery is charging, the battery positive control terminal and the battery negative control terminal of the control chip U7 connected to the positive port and the negative port of the detected battery output a high level, and the other ports output a low level.

[0065] When the other ports are positive or negative, the operation is similar.

[0066] Preferably, it also includes a charging control circuit, which includes a charging control boost chip and a charging voltage sampling circuit. The charging control boost chip is connected to each port of the battery to be charged through the battery positive port control circuit and the battery negative port control circuit, and the control chip U7 controls the on and off of each battery port to realize battery charging; the input end of the charging voltage sampling circuit is connected to the charging control boost chip, and the output end of the charging voltage sampling circuit is connected to the control chip U7. The charging voltage sampling circuit is used for the control chip U7 to monitor the charging voltage.

[0067] Preferably, see Figure 6 The battery status indication circuit includes an SMD patch lamp bead D2, the first pin of the SMD patch lamp bead D2 is connected to the BLED pin of the control chip through a twenty-ninth resistor R29, the third pin of the SMD patch lamp bead D2 is connected to the RLED pin of the control chip through a thirtieth resistor R30, the fifth pin of the SMD patch lamp bead D2 is connected to the GLED pin of the control chip through a thirty-first resistor R31, and the second pin, the fourth pin and the sixth pin of the SMD patch lamp bead D2 are connected to the positive electrode VBAT of the power supply; after charging is completed, the battery power is detected, and the SMD patch lamp bead D2 uses indicator lights of different colors to indicate different battery power values ​​and battery working status.

[0068] Specifically, the SMD chip lamp bead D2 is preferably an RGB5050 chip.

[0069] Preferably, the working status indication circuit also includes a charging status indication circuit, and the charging status indication circuit is used to detect the working status of the charging control circuit when the battery is charging, and indicate the working status of the charging circuit through lights of different colors.

[0070] Specifically, after the charging module is connected to the battery, the module intelligently matches the positive and negative interfaces of the battery interface. Batteries of different brands have different arrangements of positive and negative interfaces. The smart lock charging detection circuit can automatically adapt to various interfaces. The color light displays the battery power status. The green light indicates that the battery is fully charged and does not need to be charged. The yellow and red lights indicate that charging is required.

[0071] Connect the charging adapter, the smart lock charging detection circuit intelligently matches the positive and negative poles of the battery interface to charge the battery, the red indicator light indicates that charging is in progress, and the green light indicates that charging is finished.

[0072] After charging is completed, remove the charging adapter, and the smart lock charging detection circuit will detect the battery status: if the power indicator light is green, the battery is fully charged, the power is above 90%, the power indicator light is yellow, the power is 50%~80%, the battery is not fully charged, the power light is red and the power is less than 50%, the battery is abnormal and the battery needs to be replaced.

[0073] In the above-mentioned smart lock charging detection circuit, the battery port scanning detection circuit is arranged between the control chip U7 and the battery. The control chip U7 has four battery positive control terminals and four battery negative control terminals. The battery port scanning detection circuit scans and detects the four ports of the battery, and the identified battery positive pole is connected to the battery positive control terminal, and the identified battery negative pole is connected to the battery negative control terminal; the battery positive port control circuit and the battery negative port control circuit are also arranged between the four battery positive control terminals and the four battery negative control terminals and the four ports of the battery. When charging, the control chip U7 only connects the corresponding battery positive control terminal and the battery negative control terminal to realize battery charging. The smart lock charging detection circuit can automatically identify the positive and negative poles of the battery, realize adaptive identification of the battery port, and enable the smart charging detection circuit to be applied to various models of smart lock batteries. After charging is completed, the battery port scanning detection circuit detects the battery status and displays it to the outside through the battery status indication circuit, so that people can intuitively understand the battery power and working status. The utility model has a simple circuit structure, is easy to produce, has a low cost and is convenient for promotion.

[0074] It should be noted that the present invention is not limited to the above-mentioned embodiments. According to the creative spirit of the present invention, those skilled in the art may also make other changes. These changes made according to the creative spirit of the present invention should be included in the scope of protection required by the present invention.

Claims

1. A smart lock charging detection circuit, used for charging detection of various smart lock batteries, characterized in that: It includes a control chip U7, a battery port scanning detection circuit, a battery positive port control circuit, a battery negative port control circuit and a status indication circuit. The battery port scanning detection circuit, the battery positive port control circuit and the battery negative port control circuit are connected in parallel between the control chip and the battery connection end. The battery port scanning detection circuit, the battery positive port control circuit and the battery negative port control circuit respectively include four circuit channels with the same structure. The four circuit channels are respectively connected to the four ports of the battery. The control chip realizes the port scanning, battery charging and battery detection functions of the four ports of the battery by respectively controlling the on and off of the four circuit channels; the status indication circuit includes a battery status indication circuit, and the battery status indication circuit is used to indicate the battery power and working status.

2. A smart lock charging detection circuit as claimed in claim 1, characterized in that: The control chip U7 includes four battery positive control terminals, four battery negative control terminals, a battery positive port detection terminal and a battery negative port detection terminal. The four battery positive control terminals are respectively a first battery positive control pin V_ctrl1, a second battery positive control pin V_ctrl2, a third battery positive control pin V_ctrl3 and a fourth battery positive control pin V_ctrl4. The four battery negative control terminals are respectively a first battery negative control pin G_ctrl1, a second battery negative control pin G_ctrl2, a third battery negative control pin G_ctrl3 and a fourth battery negative control pin G_ctrl4. The battery positive port detection terminal includes a battery voltage sampling circuit, and the battery negative port detection terminal includes a battery negative sampling circuit.

3. A smart lock charging detection circuit as claimed in claim 2, characterized in that: The battery voltage sampling circuit includes a thirty-second resistor R32 and a thirty-third resistor R33 connected in series, the midpoint of the thirty-second resistor R32 and the thirty-third resistor R33 is connected to the positive port detection pin VBAT DET of the control chip U7, the free end of the thirty-second resistor R32 is connected to the positive power supply VBAT, and the free end of the thirty-third resistor R33 is connected to the negative power supply VSS.

4. A smart lock charging detection circuit as claimed in claim 2, characterized in that: The battery negative electrode sampling circuit includes a seventeenth P-channel MOS transistor Q17, a thirty-fourth resistor R34, a thirty-fifth resistor R35, a thirty-sixth resistor R36 and a thirty-seventh resistor R37, the source of the seventeenth P-channel MOS transistor Q17 is connected to the positive power supply electrode VBAT, the drain of the seventeenth P-channel MOS transistor Q17 is connected to the thirty-fourth resistor R34 and the thirty-fifth resistor R35 arranged in series, the midpoint of the thirty-fourth resistor R34 and the thirty-fifth resistor R35 is connected to the negative electrode port detection pin BGND_DET of the control chip U7, the free end of the thirty-fifth resistor R35 is connected to the negative power supply electrode VSS, the gate of the seventeenth P-channel MOS transistor Q17 is connected to the midpoint of the thirty-sixth resistor R36 and the thirty-seventh resistor R37 arranged in series, the free end of the thirty-sixth resistor R36 is connected to the source of the seventeenth P-channel MOS transistor Q17, and the free end of the thirty-seventh resistor R37 is grounded.

5. A smart lock charging detection circuit as claimed in claim 2, characterized in that: The battery port scanning detection circuit includes four parallel battery port scanning detection channels, each of which is connected to a battery positive control terminal, a battery negative control terminal and a battery port, and is used to detect the polarity of the battery port and the battery status; the four battery port scanning detection channels include a first battery port scanning detection channel, a second battery port scanning detection channel, a third battery port scanning detection channel and a fourth battery port scanning detection channel.

6. A smart lock charging detection circuit as claimed in claim 2, characterized in that: The first battery port scanning detection channel includes an eighth one-into-two-way diode B8, an eighth N-channel MOS transistor Q8, a twelfth P-channel MOS transistor Q12 and a sixteenth N-channel MOS transistor Q16, the third port of the eighth one-into-two-way diode B8 is connected to the first battery port, the second port of the eighth one-into-two-way diode B8 is connected to the source of the twelfth P-channel MOS transistor Q12, the drain of the twelfth P-channel MOS transistor Q12 is connected to the positive power supply VBAT, the gate of the twelfth P-channel MOS transistor Q12 is connected to the drain of the sixteenth N-channel MOS transistor Q16 through a twenty-fourth resistor R24, and a twentieth resistor R20 is connected between the gate and the source of the twelfth P-channel MOS transistor Q12. The source of the sixteenth N-channel MOS transistor Q16 is connected to the negative power supply VSS, the gate of the sixteenth N-channel MOS transistor Q16 is connected to the first battery positive electrode control pin V_ctrl1, and the gate of the sixteenth N-channel MOS transistor Q16 is also connected to the negative power supply VSS through the twenty-eighth resistor 28; the first port of the eighth one-to-two-way diode B8 is connected to the source of the eighth N-channel MOS transistor Q8, the drain of the eighth N-channel MOS transistor Q8 is connected to the negative power supply VSS, the gate of the eighth N-channel MOS transistor Q8 is connected to the first battery negative electrode control pin G_ctrl1, and the gate of the eighth N-channel MOS transistor Q8 is also connected to the negative power supply VSS through the sixteenth resistor R16; The second battery port scanning detection channel includes a seventh one-into-two-way diode B7, a seventh N-channel MOS transistor Q7, an eleventh P-channel MOS transistor Q11 and a fifteenth N-channel MOS transistor Q15, the third port of the seventh one-into-two-way diode B7 is connected to the second battery port, the second port of the seventh one-into-two-way diode B7 is connected to the source of the eleventh P-channel MOS transistor Q11, the drain of the eleventh P-channel MOS transistor Q11 is connected to the positive power supply VBAT, the gate of the eleventh P-channel MOS transistor Q11 is connected to the drain of the fifteenth N-channel MOS transistor Q15 through a twenty-third resistor R23, and a nineteenth resistor R19 is connected between the gate and the source of the eleventh P-channel MOS transistor Q11. The source of the fifteenth N-channel MOS transistor Q15 is connected to the negative power supply VSS, the gate of the fifteenth N-channel MOS transistor Q15 is connected to the second battery positive electrode control pin V_ctrl2, and the gate of the fifteenth N-channel MOS transistor Q15 is also connected to the negative power supply VSS through the twenty-seventh resistor R27; the first port of the seventh one-to-two-way diode B7 is connected to the source of the seventh N-channel MOS transistor Q7, the drain of the seventh N-channel MOS transistor Q7 is connected to the negative power supply VSS, the gate of the seventh N-channel MOS transistor Q7 is connected to the second battery negative electrode control pin G_ctrl2, and the gate of the seventh N-channel MOS transistor Q7 is also connected to the negative power supply VSS through the fifteenth resistor R15; The third battery port scanning detection channel includes a sixth one-into-two-way diode B6, a sixth N-channel MOS transistor Q6, a tenth P-channel MOS transistor Q10 and a fourteenth N-channel MOS transistor Q14, the third port of the sixth one-into-two-way diode B6 is connected to the third battery port, the second port of the sixth one-into-two-way diode B6 is connected to the source of the tenth P-channel MOS transistor Q10, the drain of the tenth P-channel MOS transistor Q10 is connected to the positive power supply VBAT, the gate of the tenth P-channel MOS transistor Q10 is connected to the drain of the fourteenth N-channel MOS transistor Q14 through a twenty-second resistor R22, an eighteenth resistor R18 is connected between the gate and the source of the tenth P-channel MOS transistor Q10, and the The source of the fourteenth N-channel MOS transistor Q14 is connected to the negative power supply VSS, the gate of the fourteenth N-channel MOS transistor Q14 is connected to the third battery positive electrode control pin V_ctrl3, and the gate of the fourteenth N-channel MOS transistor Q14 is also connected to the negative power supply VSS through the twenty-sixth resistor R26; the first port of the sixth one-to-two-way diode B6 is connected to the source of the sixth N-channel MOS transistor Q6, the drain of the sixth N-channel MOS transistor Q6 is connected to the negative power supply VSS, the gate of the sixth N-channel MOS transistor Q6 is connected to the third battery negative electrode control pin G_ctrl3, and the gate of the sixth N-channel MOS transistor Q6 is also connected to the negative power supply VSS through the fourteenth resistor R14; The fourth battery port scanning detection channel includes a fifth one-into-two-way diode B5, a fifth N-channel MOS transistor Q5, a ninth P-channel MOS transistor Q9 and a thirteenth N-channel MOS transistor Q13, the third port of the fifth one-into-two-way diode B5 is connected to the fourth battery port, the second port of the fifth one-into-two-way diode B5 is connected to the source of the ninth P-channel MOS transistor Q9, the drain of the ninth P-channel MOS transistor Q9 is connected to the positive power supply VBAT, the gate of the ninth P-channel MOS transistor Q9 is connected to the drain of the thirteenth N-channel MOS transistor Q13 through a twenty-first resistor R21, a seventeenth resistor R17 is connected between the gate and the source of the ninth P-channel MOS transistor Q9, and the thirteenth N-channel MOS transistor Q13 is connected to the drain of the ninth P-channel MOS transistor Q9 through a twenty-first resistor R21. The source of the N-channel MOS transistor Q13 is connected to the negative power supply VSS, the gate of the thirteenth N-channel MOS transistor Q13 is connected to the fourth battery positive electrode control pin V_ctrl4, and the gate of the thirteenth N-channel MOS transistor Q13 is also connected to the negative power supply VSS through the twenty-fifth resistor R25; the first port of the fifth one-to-two-way diode B5 is connected to the source of the fifth N-channel MOS transistor Q5, the drain of the fifth N-channel MOS transistor Q5 is connected to the negative power supply VSS, the gate of the fifth N-channel MOS transistor Q5 is connected to the fourth battery negative electrode control pin G_ctrl4, and the gate of the fifth N-channel MOS transistor Q5 is also connected to the negative power supply VSS through the thirteenth resistor R13.

7. A smart lock charging detection circuit as claimed in claim 2, characterized in that: The battery positive terminal control circuit includes four parallel battery positive terminal control channels, namely a first battery positive terminal control channel, a second battery positive terminal control channel, a third battery positive terminal control channel and a fourth battery positive terminal control channel; The first battery positive electrode port control channel includes an eighteenth P-channel MOS transistor Q18, a twenty-second N-channel MOS transistor Q22 and a fourth MOS internal diode D4, the source of the fourth MOS internal diode D4 is connected to the first battery port, the drain of the fourth MOS internal diode D4 is connected to the drain of the eighteenth P-channel MOS transistor Q18, the source of the eighteenth P-channel MOS transistor Q18 is connected to the positive electrode PV of the charging power supply, the gate of the eighteenth P-channel MOS transistor Q18 is connected to the drain of the twenty-second N-channel MOS transistor Q22 through a forty-third resistor R43, a forty-second resistor R42 is connected between the source and the gate of the eighteenth P-channel MOS transistor Q18, the gate of the twenty-second N-channel MOS transistor Q22 is connected to the first battery positive electrode control pin V_ctrl1, a fiftieth resistor R50 is connected between the source and the gate of the twenty-second N-channel MOS transistor Q22, and the source of the twenty-second N-channel MOS transistor Q22 is connected to the negative electrode VSS of the power supply; The second battery positive electrode port control channel includes a nineteenth P-channel MOS transistor Q19, a twenty-third N-channel MOS transistor Q23 and a fifth MOS internal diode D5, the source of the fifth MOS internal diode D5 is connected to the second battery port, the drain of the fifth MOS internal diode D5 is connected to the drain of the nineteenth P-channel MOS transistor Q19, the source of the nineteenth P-channel MOS transistor Q19 is connected to the positive electrode PV of the charging power supply, the gate of the nineteenth P-channel MOS transistor Q19 is connected to the drain of the twenty-third N-channel MOS transistor Q23 through a forty-fifth resistor R45, a forty-fourth resistor R44 is connected between the source and the gate of the nineteenth P-channel MOS transistor Q19, the gate of the twenty-third N-channel MOS transistor Q23 is connected to the second battery positive electrode control pin V_ctrl2, a fifty-first resistor R51 is connected between the source and the gate of the twenty-third N-channel MOS transistor Q23, and the source of the twenty-third N-channel MOS transistor Q23 is connected to the negative electrode VSS of the power supply; The third battery positive electrode port control channel includes a twentieth P-channel MOS transistor Q20, a twenty-fourth N-channel MOS transistor Q24 and a sixth MOS internal diode D6, the source of the sixth MOS internal diode D6 is connected to the third battery port, the drain of the sixth MOS internal diode D6 is connected to the drain of the twentieth P-channel MOS transistor Q20, the source of the twentieth P-channel MOS transistor Q20 is connected to the charging power supply positive electrode PV, the gate of the twentieth P-channel MOS transistor Q20 is connected to the drain of the twentieth N-channel MOS transistor Q24 through a forty-seventh resistor R47, a forty-sixth resistor R46 is connected between the source and the gate of the twentieth P-channel MOS transistor Q20, the gate of the twentieth N-channel MOS transistor Q24 is connected to the third battery positive electrode control pin V_ctrl3, a fifty-second resistor R52 is connected between the source and the gate of the twentieth N-channel MOS transistor Q24, and the source of the twentieth N-channel MOS transistor Q24 is connected to the negative power supply VSS; The fourth battery positive electrode port control channel includes a twenty-first P-channel MOS transistor Q21, a twenty-fifth N-channel MOS transistor Q25 and a seventh MOS internal diode D7, the source of the seventh MOS internal diode D7 is connected to the fourth battery port, the drain of the seventh MOS internal diode D7 is connected to the drain of the twenty-first P-channel MOS transistor Q21, the source of the twenty-first P-channel MOS transistor Q21 is connected to the charging power supply positive electrode PV, the gate of the twenty-first P-channel MOS transistor Q21 is connected to the drain of the twenty-fifth N-channel MOS transistor Q25 through a forty-ninth resistor R49, a forty-eighth resistor R48 is connected between the source and the gate of the twenty-first P-channel MOS transistor Q21, the gate of the twenty-fifth N-channel MOS transistor Q25 is connected to the fourth battery positive electrode control pin V_ctrl4, a fifty-third resistor R53 is connected between the source and the gate of the twenty-fifth N-channel MOS transistor Q25, and the source of the twenty-fifth N-channel MOS transistor Q25 is connected to the negative power supply VSS.

8. A smart lock charging detection circuit as claimed in claim 2, characterized in that: The battery negative electrode port control circuit includes four parallel battery negative electrode port control channels, namely a first battery negative electrode port control channel, a second battery negative electrode port control channel, a third battery negative electrode port control channel and a fourth battery negative electrode port control channel; The first battery negative electrode port control channel includes a first N-channel MOS transistor U3, a source of the first N-channel MOS transistor U3 is connected to the first battery port, a gate of the first N-channel MOS transistor U3 is connected to the first battery negative electrode control pin G_ctrl1, and a gate of the first N-channel MOS transistor U3 is also connected to the negative power supply VSS through a thirty-eighth resistor R38; The second battery negative electrode port control channel includes a second N-channel MOS transistor U4, the source of the second N-channel MOS transistor U4 is connected to the second battery port, the gate of the second N-channel MOS transistor U4 is connected to the second battery negative electrode control pin G_ctrl2, and the gate of the second N-channel MOS transistor U4 is also connected to the negative power supply VSS through a thirty-ninth resistor R39; The third battery negative electrode port control channel includes a third N-channel MOS transistor U5, the source of which is connected to the third battery port, the gate of which is connected to the third battery negative electrode control pin G_ctrl3, and the gate of which is also connected to the negative power supply VSS through a fortieth resistor R40; The fourth battery negative electrode port control channel includes a fourth N-channel MOS tube U6, a source of the fourth N-channel MOS tube U6 is connected to the fourth battery port, a gate of the fourth N-channel MOS tube U6 is connected to the fourth battery negative electrode control pin G_ctrl4, and a gate of the fourth N-channel MOS tube U6 is also connected to the negative power supply VSS through a thirty-eighth resistor R38.

9. A smart lock charging detection circuit as claimed in claim 1, characterized in that: It also includes a charging control circuit, which includes a charging control boost chip and a charging voltage sampling circuit. The charging control boost chip is connected to each port of the battery to be charged through the battery positive port control circuit and the battery negative port control circuit, and the control chip U7 controls the on and off of each battery port to realize battery charging; the input end of the charging voltage sampling circuit is connected to the charging control boost chip, and the output end of the charging voltage sampling circuit is connected to the control chip U7. The charging voltage sampling circuit is used for the control chip U7 to monitor the charging voltage.

10. A smart lock charging detection circuit as claimed in claim 1, characterized in that: The battery status indication circuit includes an SMD patch lamp bead D2, the first pin of the SMD patch lamp bead D2 is connected to the BLED pin of the control chip through a twenty-ninth resistor R29, the third pin of the SMD patch lamp bead D2 is connected to the RLED pin of the control chip through a thirtieth resistor R30, the fifth pin of the SMD patch lamp bead D2 is connected to the GLED pin of the control chip through a thirty-first resistor R31, and the second pin, the fourth pin and the sixth pin of the SMD patch lamp bead D2 are connected to the positive electrode VBAT of the power supply; after charging is completed, the battery power is detected, and the SMD patch lamp bead D2 uses indicator lights of different colors to indicate different battery power values ​​and battery working status.

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