Switched mode power supply (SMPS) and integrated circuit (IC) device

Abstract

The utility model relates to a switch mode power supply (SMPS) and integrated circuit (IC) equipment, and aims to realize soft start of a buck converter. The integrated circuit device includes: a buck converter; a control circuit of a buck converter includes: a comparator comparing a feedback voltage of the buck converter with a reference voltage increased from a first voltage to a second voltage; a pulse width modulator generating a pulse width modulated (PWM) signal having a time-varying pulse width proportional to the reference voltage; an AND gate which generates a first control signal by performing logic AND operation on the output of the comparator and the PWM signal; a pulse generator generating a second control signal by generating a pulse in response to a rising edge in an output of the comparator; and a selection circuit selecting the first control signal or the second control signal as a control signal of the buck converter based on an output voltage of the buck converter. The utility model is used in a switch mode power supply (SMPS) and integrated circuit (IC) equipment.

Description

Technical Field

[0001] The present invention generally relates to a switch mode power supply (SMPS), and in a specific embodiment, to a buck converter with a soft start function. Background Art

[0002] Power converters are widely used in many electronic applications from computers to automobiles. In some embodiments, the voltage within the power converter is generated by operating a switch loaded with an inductor or transformer to perform DC-DC, DC-AC and / or AC-DC conversion. Examples of power converters include switch mode power supplies (SMPS) and linear regulators. SMPS are generally more efficient than other types of power conversion systems because power conversion is performed by controlled charging and discharging of an inductor or transformer, and energy losses caused by power dissipation on a resistive voltage drop are reduced.

[0003] An SMPS typically includes at least one switch (also called a power switch) and an inductor or transformer. Some specific topologies include buck converters, boost converters, and flyback converters, among others. A control circuit is typically used to turn the switch on and off to charge and discharge the inductor. In some applications, the current supplied to the load and / or the voltage supplied to the load is controlled via a feedback loop. In some topologies, the switches used in an SMPS are implemented using cascode switches. A linear regulator is another type of power converter in which a pass transistor is controlled (e.g., turned on and off) by a controller to provide a stable voltage to an external load.

[0004] Buck converters are a popular choice for SMPS and are often used to provide power to downstream devices such as sensors or processors. In order to avoid or mitigate performance issues of buck converters, such as inrush current or output voltage overshoot at startup, soft start of the buck converter is desired. There is a need in the art for a buck converter with good soft start performance. Utility Model Content

[0005] The utility model aims to provide an improved switch mode power supply SMPS and integrated circuit IC equipment.

[0006] According to an embodiment, a switch mode power supply (SMPS) includes a buck converter and a control circuit for the buck converter. The control circuit includes: a comparator configured to compare a feedback voltage of the buck converter with a reference voltage increased from a first voltage to a second voltage; a pulse width modulator configured to generate a pulse width modulated (PWM) signal, wherein the pulse width of the PWM signal varies with time and is proportional to the value of the reference voltage; an AND gate, wherein a first input terminal of the AND gate and a second input terminal of the AND gate are respectively coupled to an output terminal of the comparator and an output terminal of the pulse width modulator; a pulse generator coupled to the output terminal of the comparator and configured to generate a pulse in response to a rising edge in an output signal of the comparator; and a selection circuit coupled to the AND gate and the pulse generator, wherein the selection circuit is configured to select an output of the AND gate or an output of the pulse generator as an output of the selection circuit based on the output voltage of the buck converter, wherein the buck converter is configured to be controlled by the output of the selection circuit.

[0007] Preferably, the selection circuit is configured to: when the output voltage of the buck converter is lower than a predetermined threshold, select the output of the AND gate as the output of the selection circuit; and when the output voltage of the buck converter is higher than the predetermined threshold, select the output of the pulse generator as the output of the selection circuit.

[0008] Preferably, the feedback voltage is applied to a first input terminal of the comparator and the reference voltage is applied to a second input terminal of the comparator.

[0009] Preferably, the first input terminal is a negative terminal of the comparator and the second input terminal is a positive terminal of the comparator.

[0010] Preferably, the SMPS further comprises a voltage divider coupled to the output terminal of the buck converter, the voltage divider being configured to generate a scaled version of the output voltage of the buck converter.

[0011] Preferably, the SMPS further comprises: a ripple reconstructor coupled to the input / output I / O terminal of the buck converter and configured to generate a ripple voltage; and an adder circuit, wherein the adder circuit is configured to add the ripple voltage to a scaled version of the output voltage of the buck converter to generate a feedback voltage.

[0012] Preferably, the SMPS further comprises a voltage checking circuit configured to compare the output voltage of the buck converter with a predetermined threshold.

[0013] Preferably, the duration of the pulses generated by the pulse generator is proportional to the ratio between the output voltage of the buck converter and the supply voltage of the pulse generator.

[0014] Preferably, the buck converter comprises a gate driver circuit configured to drive one or more switches of the buck converter, wherein the output of the selection circuit is coupled to the gate driver circuit.

[0015] Preferably, the SMPS further comprises a reference signal generator configured to generate a reference voltage, wherein an output terminal of the reference signal generator is coupled to an input terminal of the pulse width modulator and an input terminal of the comparator.

[0016] Preferably, the first voltage is zero.

[0017] Preferably, the reference voltage increases linearly from the first voltage to the second voltage.

[0018] According to an embodiment, an integrated circuit (IC) device includes: a buck converter and a control circuit for the buck converter. The control circuit includes: a comparator configured to compare a feedback voltage of the buck converter with a reference voltage increased from a first voltage to a second voltage; a pulse width modulator configured to generate a pulse width modulation (PWM) signal having a time-varying pulse width proportional to the value of the reference voltage; an AND gate configured to generate a first control signal by performing a logical AND operation on an output signal of the comparator and the PWM signal; a pulse generator configured to generate a second control signal by generating a pulse in response to a rising edge in the output signal of the comparator; and a selection circuit configured to select the first control signal or the second control signal as the control signal of the buck converter based on the output voltage of the buck converter.

[0019] Preferably, the selection circuit is configured to: select the first control signal as the control signal of the buck converter when the output voltage of the buck converter is lower than a predetermined threshold; and select the second control signal as the control signal of the buck converter when the output voltage of the buck converter is higher than the predetermined threshold.

[0020] Preferably, the buck converter has one or more switches which are alternately switched on and off during normal operation of the buck converter, wherein the control signal of the buck converter controls the operation of the one or more switches during normal operation of the buck converter.

[0021] Preferably, the control circuit further includes a reference voltage generator configured to generate a reference voltage.

[0022] Preferably, the control circuit further comprises a voltage checking circuit configured to compare the output voltage of the buck converter with a predetermined threshold value.

[0023] The technical effect of one aspect of the utility model is to achieve soft start of the buck converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more fully understand the present invention and its advantages, reference is now made to the following description in conjunction with the accompanying drawings, in which:

[0025] Figure 1 illustrates a block diagram of a switch mode power supply (SMPS) in an embodiment;

[0026] Figure 2 A block diagram of a pulse generator in an embodiment is shown;

[0027] Figure 3 The embodiment is shown in the figure Figure 2 Timing diagram of the pulse generator;

[0028] Figure 4 The embodiment is shown in the figure Figure 1 Timing diagram of SMPS;

[0029] Figure 5 illustrates a block diagram of a system including a power management integrated circuit (PMIC) device and a processor in an embodiment; and

[0030] Figure 6 A flow chart of a method of starting a buck converter in some embodiments is illustrated. DETAILED DESCRIPTION

[0031] The making and use of the currently disclosed examples are discussed in detail below. However, it should be appreciated that the present invention provides many applicable utility concepts that can be implemented in a variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the present invention and do not limit the scope of the present invention. Throughout the discussion herein, unless otherwise specified, the same or similar reference numerals or labels in different figures refer to the same or similar components or signals.

[0032] The present disclosure will be described with reference to examples in a specific context, namely a buck converter with a control circuit that performs a soft start of the buck converter. The soft start of the buck converter is also referred to as a soft start process of the buck converter.

[0033] Figure 1 A block diagram of a switch mode power supply (SMPS) 100 in an embodiment is illustrated. Figure 1 The SMPS 100 in FIG. 1 is a buck converter, and its control circuit implements a soft start of the buck converter. As will be discussed in more detail below, during the soft start process, the voltage V is increased from a first value (e.g., zero voltage) to a second value (e.g., voltage V REF ) is supplied to the control circuit of the buck converter. The control circuit generates a control signal (e.g., PWM) based on the reference voltage and the output voltage of the buck converter. BUCKsignal) to drive the buck converter, so that the output voltage of the buck converter increases from zero to the steady-state output voltage during this period of time.

[0034] exist Figure 1 , the components within the dashed box 150 illustrate a buck converter. The components outside the dashed box 150 form a control circuit for the buck converter. In some embodiments, Figure 1 The SMPS 100 (or a portion of the SMPS 100 ) is formed as an integrated circuit (IC) device or a portion of an IC device. An example of an IC device is a power management integrated circuit (PMIC) device.

[0035] refer to Figure 1 , the buck converter includes switches 101 and 103, a gate driver circuit 105, an inductor 107, and a capacitor 109. Figure 1 In the example of , switch 101 is a P-type transistor and switch 103 is an N-type transistor. Switch 101 is coupled between an input / output (I / O) pin 111 (also referred to as an I / O terminal or I / O port) of SMPS 100 and an I / O pin 113 of SMPS 100, and switch 103 is coupled between I / O pin 113 and a reference voltage (e.g., electrical ground). Gate driver circuit 105 receives a control signal 128 (e.g., a pulse width modulation (PWM) signal) for the buck converter, and generates control signals (e.g., gate control signals) for switches 101 and 103, for example, by amplifying and / or voltage shifting control signal 128. Note that since switches 101 and 103 are transistors of different types (e.g., N-type or P-type), control signal 128 sets switches 101 and 103 to opposite states (e.g., an ON state or an OFF state) during operation. In other words, during operation of the buck converter, switch 101 is closed when switch 103 is open, and switch 101 is open when switch 103 is closed.

[0036] exist Figure 1 In the example of FIG. 1 , inductor 107 is coupled between I / O pin 113 and I / O pin 115 of SMPS 100, and capacitor 109 is coupled between I / O pin 115 and a reference voltage (e.g., electrical ground). In the illustrated embodiment, I / O pin 111 is configured to receive a supply voltage V of a buck converter. IN , and I / O pin 115 is configured to output the buck converter output voltage V OUT .

[0037] In some embodiments, when Figure 1When the SMPS 100 is integrated into an IC device, the inductor 107 and the capacitor 109 are not integrated into the IC device, but are implemented as external components connected to the IC device. This may be due to the difficulty in integrating inductors and capacitors of large nominal values ​​(e.g., large inductance or large capacitance) into the IC device. However, it is contemplated within the scope of the present disclosure to integrate the inductor 107 and the capacitor 109 into the IC device including the SMPS 100.

[0038] Figure 1 The buck converter shown in is only a non-limiting example. Variations are possible and are fully intended to be included within the scope of this disclosure. For example, Figure 1 The switch 103 in may be replaced by a diode with its cathode connected to the I / O pin 113 and its anode connected to a reference voltage (eg, electrical ground).

[0039] The control circuit of the buck converter and the operation of the buck converter are discussed below.

[0040] Still reference Figure 1 , the output voltage of the buck converter V OUT is sent to a voltage divider formed by resistors R1 and R2, which are coupled between I / O pin 115 and reference node 121. In an embodiment, reference node 121 is coupled to electrical ground. The output of the voltage divider at node 120 is combined with the ripple voltage V by an adder circuit 119. RIPPLE Added together to form the feedback voltage V FB , the feedback voltage V FB The ripple voltage V is sent to an input terminal (eg, a negative input terminal) of the comparator 123. The ripple voltage V is generated by filtering the voltage at the I / O pin 113 using the ripple reconstructor 117. RIPPLE The ripple reconstructor 117 may be a filter (eg, a low-pass filter) or other suitable circuit to reshape the voltage at the I / O pin 113 to form a ripple voltage V RIPPLE The ripple reconstructor 117 is known and used in the art, so the details are not discussed here.

[0041] exist Figure 1 , the reference voltage 132, also referred to as the soft start reference voltage 132, or the reference voltage V REF_SOFT , which is generated by the reference voltage generator 131 and sent to the other input terminal (eg, the positive input terminal) of the comparator 123. Figure 1 In the example of FIG. 1 , the output signal 124 (also referred to as the Comp_Out signal) of the comparator 123 is at the reference voltage V REF_SOFT Higher than the feedback voltage V FB , has a logic high value (eg, digital value 1), and at the reference voltage V REF_SOFTLower than the feedback voltage V FB , has a logical low value (e.g., a digital value of 0).

[0042] In an embodiment, the reference voltage generator 131 is configured to generate a reference voltage V REF_SOFT The circuit, the reference voltage V REF_SOFT During a period of time, the voltage increases from a first value (e.g., zero voltage) to a second value (e.g., a predetermined voltage V REF ). Figure 4 shows the reference voltage V REF_SOFT For example, the reference voltage V REF_SOFT During the soft start process of the buck converter, the voltage linearly increases from a first value (eg, zero) to a final value (eg, V REF ). Note that, unlike an electrically grounded reference voltage having a static or fixed voltage value (eg, zero voltage), during the soft-start process of the buck converter, the reference voltage V REF_SOFT Increase continuously (eg, linearly) from a first value to a second value.

[0043] Return to reference Figure 1 , the reference voltage generator 131 receives a predetermined voltage V REF , the predetermined voltage V REF can be internally (e.g., via a voltage divider, not shown) from the supply voltage V IN may be derived from, or may be received from, another I / O pin as an external signal (eg, external to SMPS 100 ).

[0044] Figure 1 Further diagram shows that according to the reference voltage V REF_SOFT The pulse width modulator 133 modulates the pulse width of the clock signal CLK to generate an output signal 134 (eg, a pulse width modulated (PWM) signal). In an embodiment, the pulse width of the modulated clock signal CLK (which is the output signal 134) is the same as the reference voltage V REF_SOFT The value of is proportional to the frequency of the modulated clock signal CLK, while the frequency of the modulated clock signal CLK is the same as the clock signal CLK. Note that during the soft start process of the buck converter, the reference voltage V REF_SOFT The value of increases from the first value to the second value. Therefore, the output signal 134 (also referred to as the Pulse_PWM signal) includes a signal that follows the reference voltage V during the soft start process of the buck converter. REF_SOFT A plurality of pulses having increasing (eg, monotonically increasing) time varying pulse widths. Figure 4 An example of the Pulse_PWM signal between time T0 and time T3 is illustrated. Figure 1 The clock signal CLK in may be provided as an external signal to an I / O pin of the SMPS 100 , or may be generated internally.

[0045] The output signal 124 of the comparator 123 and the output signal 134 of the pulse width modulator 133 are sent to the input terminal of the AND gate 125, and the AND gate 125 performs a logical AND operation on the output signal 124 and the output signal 134 to generate an output signal 126. Therefore, the output signal 126 (also referred to as the first control signal P1) is a gated PWM signal. As described in more detail below, during the soft start process of the buck converter, the first control signal P1 is used as the control signal 128 of the buck converter to initially start the buck converter, and once the output voltage V OUT Rising above a predetermined threshold, the second control signal P2 generated by the pulse generator 135 is used as the control signal 128 for the buck converter.

[0046] Figure 1 Also shown is a pulse generator 135 that generates an output signal 136 (also referred to as a second control signal P2). In some embodiments, in response to a rising edge in the Comp_Out signal, a pulse having a pulse width T is generated in the output signal 136. ON pulse. Figure 2 An embodiment of the pulse generator 135 is shown in FIG.

[0047] Figure 2 FIG. 1 is a block diagram of a pulse generator 135 in an embodiment. Figure 2 , the pulse generator 135 includes a comparator 201. A first input terminal (e.g., a negative input terminal) of the comparator 201 is coupled to the output of a voltage divider formed by resistors 213 and 215. The resistors 213 and 215 are coupled between the I / O pin 115 and a reference voltage (e.g., electrical ground). The voltage divider provides the output voltage V of the buck converter to the first input terminal of the comparator 201. OUT The scaled version of OUT , where K is a constant scaling factor.

[0048] A second input terminal (eg, a positive input terminal) of the comparator 201 is coupled to a node between the current source 217 and the capacitor 219. Figure 2 In the example of FIG. 1 , the current source 217 is coupled to the I / O pin 111 , and the current provided by the current source 217 is expressed as I=α×V IN , where α is a constant and V IN is the power supply voltage of SMPS 100. The capacitance of capacitor 219 is represented by C RAMP The second input terminal of the comparator 201 is also coupled to a switch 211 (eg, a transistor, a transmission gate, etc.). The switch 211 is controlled by a control signal 210 at the output of the inverter 209. The input terminal of the inverter 209 is coupled to the output terminal of the flip-flop 207.

[0049] Still reference Figure 2 , the output signal 202 of the comparator 201 is sent to the edge detector 203. The edge detector 203 is configured to detect the rising edge in the output signal 202 and generate a short pulse (referred to as END) starting at the rising edge of the output signal 202. TON pulse).

[0050] Figure 2 Another edge detector 205 is also shown. The edge detector 205 is configured to Figure 1 The comparator 123 receives the Comp_Out signal, detects the rising edge in the Comp_Out signal, and generates a short pulse (referred to as START) starting at the rising edge of the Comp_Out signal. TON pulse). Each START TON Pulse and corresponding END TON Pulse is used to generate a pulse signal, refer to Figure 2 and Figure 3 Discuss in detail.

[0051] exist Figure 2 In the example of FIG. 1 , the output signal 206 (eg, START TON The pulse) is sent to the SET (S) terminal of the flip-flop 207, and the output signal 204 (eg, END) of the edge detector 203 is TON The output signal 136 of the flip-flop 207 is a SET (R) latch formed by a pair of cross-coupled NOR gates. In some embodiments, when the SET terminal and the RESET terminal are in a logic low state (e.g., the signals at the SET terminal and the RESET terminal have a logic low value), the output signal 136 of the flip-flop 207 maintains its current value. If the SET terminal is pulsed high and the RESET terminal remains low, the output signal 136 is forced high and remains high when the SET terminal returns to low; similarly, if the RESET terminal is pulsed high and the SET terminal remains low, the output signal 136 is forced low and remains low when the RESET terminal returns to low.

[0052] Figure 3 In the embodiment shown Figure 2 How does the pulse generator of the output signal 136 (also referred to as the second control signal P2) generate a pulse in response to a rising edge in the Comp_Out signal, wherein the pulse has a pulse with V OUT / V IN Proportional pulse width T ON . Figure 3The process shown in is repeated during operation of the buck converter to generate multiple pulses during at least the second phase of the soft start process discussed below.

[0053] exist Figure 3 In the example of , the output signal 136 (eg, the second control signal P2) of the flip-flop 207 initially (eg, after power-up) has a logic low value. Therefore, Figure 2 The control signal 210 in (which is the inversion of the output signal 136) initially has a logic high value, which closes the switch 211 to pull the voltage at the second input terminal (e.g., the positive input terminal) of the comparator 201 down to electrical ground. Therefore, the output signal 202 initially has a logic low value.

[0054] refer to Figure 2 and Figure 3 At time TA, the Comp_Out signal changes from logic low to logic high, thereby forming a rising edge. In response to the rising edge in the Comp_Out signal, the edge detector 205 generates a START TON Pulse. Note that the output signal 204 of the edge detector 203 is still at logic low at time TA. Therefore, START TON The pulse at time TA turns the output signal 136 of the flip-flop 207 (at Figure 3 2 , the second control signal P2 is set to logic high. Therefore, the control signal 210 , which is the inversion of the output signal 136 , becomes logic low, thereby opening the switch 211 .

[0055] When the switch 211 switches from the closed position to the open position, the current source 217 starts to charge the capacitor 219, and the voltage across the capacitor 219 (eg Figure 3 V RAMP As the charging process continues, the voltage across capacitor 219 rises to a value higher than K×V at time TB. OUT , so the output signal 202 of the comparator 201 changes from logic low to logic high, thereby generating a rising edge. In response, the edge detector 203 generates an END at time TB. TON Pulse. Note that the output signal 206 of the edge detector 205 has a logic low value at time TB, so END TON The pulse resets the flip-flop 207, causing the second control signal P2 to become a logic low value.

[0056] As discussed above, Figure 2 The pulse width of the second control signal P2 (expressed as T ON ) is determined by the duration between time TA and time TB. Those skilled in the art will readily appreciate that, since the voltage VRAMP The linear increase of pulse width T ON Given by:

[0057]

[0058] in, In other words, the pulse width T ON With V OUT / V IN is proportional to the ratio.

[0059] At the beginning of the soft start process of the buck converter, the output voltage V OUT According to equation (1), at the beginning of the soft start process, the pulse width T of the second control signal P2 is ON Theoretically, it should be zero. In practical circuits, due to propagation delays, for example, the pulse width T ON The first control signal P1 may have a short duration of, for example, several nanoseconds at the beginning of the soft start process, which is still too short to be used as the control signal 128 of the buck converter. Therefore, it is problematic to use the second control signal P2 to start the buck converter from the beginning. The present disclosure starts the buck converter by initially using the first control signal P1 (e.g., driving the buck converter with the first control signal P1), and then when the output voltage V OUT Switching to the second control signal P2 after rising above the threshold solves this problem, which will be discussed in detail below.

[0060] Return to reference Figure 1 , the SMPS 100 includes a voltage check circuit 137, which is configured to convert the output voltage V OUT With the predetermined threshold V THRESH The predetermined threshold V THRESH is high enough to allow the pulse generator 135 to generate a pulse width T ON (Its V OUT / V IN The predetermined threshold V THRESH The target output voltage V OUT_STEADY (Also called steady-state output voltage V OUT_STEADY ) between about 85% and about 95%, such as 90%. The voltage check circuit 137 may be or include a circuit that checks the output voltage V OUT With the predetermined threshold V THRESH The output signal 138 of the voltage detection circuit 137 is also called V OUT_OK signal, the output voltage of the buck converter V OUT Above the predetermined threshold V THRESHhas a logic high value, and the output voltage V OUT Below the predetermined threshold V THRESH has a logic low value.

[0061] Figure 1 Also shown is a selection circuit 127, which is Figure 1 127 is illustrated as a multiplexer (MUX), but any suitable selection circuit may be used. The selection circuit 127 is also referred to as MUX 127 in the discussion herein, and it should be understood that any selection circuit 127 capable of selecting one of two input signals as an output signal may be used.

[0062] like Figure 1 As shown in FIG. 1 , the input terminal of MUX 127 is coupled to a first control signal P1 (e.g., a gated PWM signal) and a second control signal P2 (e.g., a PWM signal). The output of MUX 127 is selected by the control signal of MUX 127, which is V from the voltage check circuit 137. OUT_OK signal. In the embodiment, when V OUT_OK When the signal is logic low, the first control signal P1 is selected as the output of MUX 127; when V OUT_OK When the signal is logic high, the second control signal P2 is selected as the output of MUX 127. The output of MUX 127, also known as PWM Buck Signal , is a control signal 128 sent to the gate driver circuit 105 and used to drive the buck converter (eg, control the operation of the switch(es) of the buck converter).

[0063] V OUT_OK The signal may optionally be used as an enable signal for the pulse width modulator 133 and the pulse generator 135, such as Figure 1 For example, when V OUT_OK When the signal has a logic low value, the pulse width modulator 133 is enabled and the pulse generator 135 is disabled. Conversely, when V OUT_OK When the signal has a logic high value, the pulse width modulator 133 is disabled and the pulse generator 135 is enabled.

[0064] Reference now Figure 1 and Figure 4 The operation of SMPS 100 is described. Figure 4 The embodiment is shown in the figure Figure 1 Timing diagram of the different signals of the SMPS100.

[0065] refer to Figure 1 and Figure 4 At time T0, SMPS100 starts the soft start process. The reference voltage V generated by the reference voltage generator 131REF_SFT The voltage at the first voltage (eg, 0V) is increased (eg, linearly) from a first value (eg, 0V) to a second value (eg, V REF ). Since the output voltage V OUT is still zero, so the Comp_Out signal generated by the comparator 123 becomes a logic high value at time T0. The pulse width modulator 133 starts to generate the Pulse_PWM signal at time T0. Figure 4 As shown in the figure, the pulse width of the Pulse_PWM signal is related to the reference voltage V REF_SFT Proportional, therefore, it is time varying and increases with time.

[0066] In the first stage of the soft start process (eg, between time T0 and time T4), since the output voltage V OUT Below the predetermined threshold V THRESH , so the V generated by the voltage check circuit 137 OUT_OK The signal has a logic low value. Therefore, MUX 127 selects the first control signal P1 as the PWM signal that controls the operation of the buck converter. Buck Signal. Figure 4 As shown in FIG. 1 , the PWM during the first phase of the soft start process (eg, between time T0 and time T4) is Buck The signal is the first control signal P1 formed by gate-controlling the Pulse_PWM signal by the Comp_Out signal. The buck converter is PWM-controlled from time T0. Buck signal drive, and its output voltage V OUT Follow the reference voltage V REF_SOFT And it also began to increase. Figure 4 As shown in Figure 1, during the first stage of the soft start process, when the feedback voltage V FB rises above the reference voltage V REF_SOFT , the Comp_Out signal can go to a logic low value.

[0067] At time T4, the output voltage V OUT rises above a predetermined threshold V THRESH Therefore, the V generated by the voltage check circuit 137 OUT_OK The signal changes to a logic high value at time T4. In response, MUX 127 now selects the second control signal P2 generated by pulse generator 135 as the PWM signal that controls the operation of the buck converter. Buck The soft start process enters the second stage after time T4.

[0068] like Figure 4 As shown in Figure 2, in the second stage of the soft start process, the PWM BuckThe signal includes a pulse width of T ON The pulse, where T ON For example, it is determined by equation (1). Figure 4 The duration T is shown ON How does each pulse consist of a pair of START TON Pulse and END TON Pulse generation.

[0069] From time T4 to time T5, the output voltage V OUT Continue to rise. At time T5, the reference voltage V REF_SOEF Reach value V REF , and the output voltage of the buck converter V OUT reaches its steady-state output voltage V OUT_STEADY . Figure 4 The PWM between time T4 and time T5 is not shown. Buck If a pulse is generated between time T4 and time T5, then the pulse width T ON will increase between time T4 and time T5. At time T5, the pulse width T ON Reached by V OUT_STEADY / V IN The final fixed nominal value determined. Those skilled in the art will readily recognize that when operating in the second phase of the soft start process (e.g., driven by the control signal P2), the SMPS 100 is said to operate with adaptive constant on-time (ACOT) control. Thus, during the first phase of the soft start process, the ACOT control is disabled and the buck converter is controlled (e.g., driven) by the first control signal P1.

[0070] Note that in Figure 4 For simplicity, the Pulse_PWM signal after about time T4 is not plotted, and the STAT_PWM signal before time T4 is not plotted. TON Pulse and END TON Pulse. At V OUT_OK In the embodiment where the signal is used to enable / disable the pulse width modulator 133 and the pulse generator 135, the Plus_PWM signal is not generated after time T4, and the START signal is not generated before time T4. TON Pulse and END TON pulse.

[0071] Figure 5 The block diagram of a system 500 including a power management integrated circuit (PMIC) device 300 and a processor 400 in an embodiment is shown. The PMIC 300 includes a plurality of power circuits 303, 305, and 307. Each power circuit 303 may be Figure 1The power supply circuit 307 may be a low dropout (LDO) power supply. The power supply circuit 305 may be other types of power supplies, such as a boost converter, a flyback converter, etc.

[0072] exist Figure 5 In the example, the power supply circuit 303 receives the power supply voltage V IN , and generates an output voltage V OUT1 And V OUT2 For use by processor 400. Power supply circuit 307 (eg, LDO power supply) can receive output voltage V OUT1 and V OUT2 , and generates a well-regulated output voltage for use by processor 400. In some embodiments, the output voltage V OUT1 and V OUT2 A higher drive capability (eg, with a higher current) may be provided, but with more voltage ripple, whereas the output of the power supply circuit 307 may have less voltage ripple, but may provide a lower drive capability.

[0073] The PMIC 300 has an I / O interface 301 (e.g., an I2C interface) for communicating with the processor 400 through an I / O interface 401 (e.g., an I2C interface) of the processor 400. The processor 400 may be or include a central processing unit (CPU), a microcontroller (MCU), a digital signal processor (DSP), etc. The processor 400 may include a memory module (e.g., a random access memory (RAM) and / or a read-only memory (ROM)), and may include peripheral circuits such as an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), etc.

[0074] Figure 6 1 is a flow chart of a method 1000 for starting a buck converter in some embodiments. It should be understood that Figure 6 The example methods shown in are merely examples of many possible example methods. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, the following may be added, removed, replaced, rearranged, or repeated. Figure 6 The steps shown in .

[0075] refer to Figure 6, at block 1010, a reference voltage is supplied to a control circuit for a buck converter, wherein the reference voltage is increased from a first voltage to a second voltage. At block 1020, an output voltage of the buck converter is compared to a predetermined threshold. At block 1030, in response to detecting that the output voltage of the buck converter is below the predetermined threshold, the buck converter is driven using a first control signal, wherein the first control signal includes a first plurality of pulses having a time-varying pulse width proportional to the reference voltage. At block 1040, in response to detecting that the output voltage of the buck converter is above the predetermined threshold, the buck converter is driven using a second control signal, wherein the second control signal includes a second plurality of pulses having a pulse width proportional to a ratio between the output voltage of the buck converter and a supply voltage of the buck converter.

[0076] Embodiments can achieve the advantages described below. For example, by using the first control signal P1 and the second control signal P2 to drive the buck converter during the first stage and the second stage of the soft start process, respectively, the disclosed SMPS 100 can achieve a smooth soft start process, which avoids or alleviates performance issues such as inrush current or output voltage overshoot at startup.

[0077] To further understand the advantages of the disclosed SMPS and its soft-start process, consider a reference design in which, at the beginning of the soft-start process, a pulse of the Comp_Out signal is used as a control signal 128 to drive a buck converter such that the buck converter outputs a voltage V OUT Increases to a certain level. The pulse counter is used to count the number of pulses in the Comp_Out signal. In some embodiments, after the pulse counter counts a pulse in the Comp_Out signal, the output signal 136 of the pulse generator 135 (e.g., the second control signal P2) is used as the control signal 128 to drive the buck converter. The above reference design can solve the problems associated with starting the buck converter with a zero or near-zero PWM pulse width. However, since the pulses of the Comp_Out signal have a long and uncontrolled duration, it may cause the output voltage V OUT , i.e., where there is a maximum voltage across the inductor 107 (e.g., V IN -V OUT ). In some embodiments, during the long, uncontrolled duration of the pulse of the Comp_Out signal, a high current flows, suddenly charging capacitor 109 and causing the output voltage V of the buck converter to OUT Unexpected step in the PMIC. Unexpected step can be hundreds of millivolts. Figure 5 300) using a buck converter for a processor peripheral or memory module (e.g., see Figure 5In applications where the supply voltage is 400V, the target output voltage provided by the buck converter may be less than 1V, so a base of hundreds of millivolts is unacceptable. The utility model achieves a smooth output voltage V by switching between the first control signal P1 and the second control signal P2 during the first and second stages of the soft start process. OUT , and avoids the output voltage V OUT Unexpected step in the

[0078] Examples of the present invention are summarized here. Other examples can also be understood from the entire specification and text submitted herein.

[0079] Example 1. According to an embodiment, a switch mode power supply (SMPS) includes: a buck converter; a control circuit for the buck converter, comprising: a comparator configured to compare a feedback voltage of the buck converter with a reference voltage increased from a first voltage to a second voltage; a pulse width modulator configured to generate a pulse width modulated (PWM) signal, wherein a pulse width of the PWM signal varies with time and is proportional to a value of the reference voltage; an AND gate, wherein a first input terminal of the AND gate and a second input terminal of the AND gate are coupled to an output terminal of the comparator and an output terminal of the pulse width modulator, respectively; a pulse generator coupled to the output terminal of the comparator and configured to generate a pulse in response to a rising edge of an output signal of the comparator; and a selection circuit coupled to the AND gate and the pulse generator, wherein the selection circuit is configured to select an output of the AND gate or an output of the pulse generator as an output of the selection circuit based on the output voltage of the buck converter, wherein the buck converter is configured to be controlled by the output of the selection circuit.

[0080] Example 2. The SMPS of Example 1, wherein the selection circuit is configured to: select the output of the AND gate as the output of the selection circuit when the output voltage of the buck converter is lower than a predetermined threshold; and select the output of the pulse generator as the output of the selection circuit when the output voltage of the buck converter is higher than the predetermined threshold.

[0081] Example 3. The SMPS of Example 2, wherein the feedback voltage is applied to the first input terminal of the comparator and the reference voltage is applied to the second input terminal of the comparator.

[0082] Example 4. The SMPS of Example 3, wherein the first input terminal is a negative terminal of the comparator and the second input terminal is a positive terminal of the comparator.

[0083] Example 5. The SMPS of Example 3, further comprising a voltage divider coupled to the output terminal of the buck converter, the voltage divider configured to generate a scaled version of the output voltage of the buck converter.

[0084] Example 6. The SMPS of Example 5, further comprising: a ripple reconstructor coupled to an input / output (I / O) terminal of the buck converter and configured to generate a ripple voltage; and an adder circuit, wherein the adder circuit is configured to add the ripple voltage to a scaled version of the output voltage of the buck converter to generate a feedback voltage.

[0085] Example 7. The SMPS of Example 2, further comprising a voltage check circuit configured to compare the output voltage of the buck converter with a predetermined threshold.

[0086] Example 8. The SMPS of Example 2, wherein the duration of the pulse generated by the pulse generator is proportional to the ratio between the output voltage of the buck converter and the supply voltage of the pulse generator.

[0087] Example 9. The SMPS of Example 2, wherein the buck converter includes a gate driver circuit configured to drive one or more switches of the buck converter, wherein the output of the selection circuit is coupled to the gate driver circuit.

[0088] Example 10. The SMPS of Example 2, further comprising a reference signal generator configured to generate a reference voltage, wherein an output terminal of the reference signal generator is coupled to an input terminal of the pulse width modulator and an input terminal of the comparator.

[0089] Example 11. The SMPS of Example 10, wherein the first voltage is zero.

[0090] Example 12. The SMPS of Example 11, wherein the reference voltage increases linearly from the first voltage to the second voltage.

[0091] Example 13. According to an embodiment, an integrated circuit (IC) device includes: a buck converter; and a control circuit for the buck converter, comprising: a comparator configured to compare a feedback voltage of the buck converter with a reference voltage that increases from a first voltage to a second voltage; a pulse width modulator configured to generate a pulse width modulated (PWM) signal having a time-varying pulse width that is proportional to the value of the reference voltage; an AND gate configured to generate a first control signal by performing a logical AND operation of an output signal of the comparator and the PWM signal; a pulse generator configured to generate a second control signal by generating a pulse in response to a rising edge in the output signal of the comparator; and a selection circuit configured to select the first control signal or the second control signal as the control signal of the buck converter based on the output voltage of the buck converter.

[0092] Example 14. An IC device of Example 13, wherein the selection circuit is configured to: select a first control signal as the control signal of the buck converter when the output voltage of the buck converter is lower than a predetermined threshold; and select a second control signal as the control signal of the buck converter when the output voltage of the buck converter is higher than a predetermined threshold.

[0093] Example 15. The IC device of Example 14, wherein the buck converter has one or more switches that are alternately turned on and off during normal operation of the buck converter, wherein a control signal of the buck converter controls operation of the one or more switches during normal operation of the buck converter.

[0094] Example 16. The IC device of Example 14, wherein the control circuit further comprises a reference voltage generator configured to generate a reference voltage.

[0095] Example 17. The IC device of Example 14, wherein the control circuit further comprises a voltage check circuit configured to compare the output voltage of the buck converter with a predetermined threshold.

[0096] Example 18. According to an embodiment, a method for starting a buck converter includes: supplying a reference voltage to a control circuit for the buck converter, wherein the reference voltage increases from a first voltage to a second voltage; comparing the output voltage of the buck converter with a predetermined threshold; in response to detecting that the output voltage of the buck converter is lower than the predetermined threshold, driving the buck converter using a first control signal, wherein the first control signal includes a first plurality of pulses, wherein the first plurality of pulses have a pulse width that varies over time and is proportional to the reference voltage; and in response to detecting that the output voltage of the buck converter is higher than the predetermined threshold, driving the buck converter using a second control signal, wherein the second control signal includes a second plurality of pulses, wherein the second plurality of pulses have a pulse width that is proportional to the ratio between the output voltage of the buck converter and the power supply voltage of the buck converter.

[0097] Example 19. The method as described in Example 18 also includes: generating a first control signal by: using a first comparator to compare the feedback voltage of the buck converter with a reference voltage; using the reference voltage to modulate the pulse width of the clock signal so that the pulse width of the modulated clock signal increases with the reference voltage; and performing a logical AND operation on the output signal of the first comparator and the modulated clock signal to generate the first control signal.

[0098] Example 20. The method as described in Example 19 also includes generating a second control signal by: detecting a rising edge in the output signal of the first comparator; in response to detecting the rising edge in the output signal of the first comparator: setting the output of a set-reset (SR) latch to a logic high value; and starting to charge a capacitor using a current source, wherein the capacitor is coupled between a second input terminal of the second comparator and electrical ground, wherein the first input terminal of the second comparator is supplied with a scaled version of the output voltage of the buck converter; detecting a rising edge in the output signal of the second comparator; and in response to detecting the rising edge in the output signal of the second comparator: resetting the output of the SR latch to a logic low value, wherein the output of the SR latch is a second control signal; and forcing the voltage at the second input terminal of the second comparator to electrical ground.

[0099] Although the utility model has been described with reference to illustrative examples, this description is not intended to be interpreted as limiting. When referring to the specification, those skilled in the art will understand various modifications and combinations of illustrative examples and other examples of the utility model. Therefore, the attached claims are intended to cover any such modifications or examples.

Claims

1. A switch mode power supply (SMPS), characterized in that: The switch mode power supply SMPS comprises: Buck converter; and A control circuit for a buck converter comprising: a comparator configured to compare a feedback voltage of the buck converter with a reference voltage increased from a first voltage to a second voltage; A pulse width modulator is configured to generate a pulse width modulated PWM signal, wherein The pulse width of the PWM signal varies with time and is proportional to the value of the reference voltage; an AND gate, wherein a first input terminal of the AND gate and a second input terminal of the AND gate are coupled to an output terminal of the comparator and an output terminal of the pulse width modulator, respectively; a pulse generator coupled to the output terminal of the comparator and configured to generate a pulse in response to a rising edge of an output signal of the comparator; and A selection circuit is coupled to the AND gate and the pulse generator, wherein the selection circuit is configured to select an output of the AND gate or an output of the pulse generator as an output of the selection circuit based on an output voltage of the buck converter, wherein the buck converter is configured to be controlled by the output of the selection circuit.

2. The SMPS according to claim 1, characterized in that The selection circuit is configured as: When the output voltage of the buck converter is lower than a predetermined threshold, selecting the output of the AND gate as the output of the selection circuit; and When the output voltage of the buck converter is higher than a predetermined threshold, the output of the pulse generator is selected as the output of the selection circuit.

3. The SMPS according to claim 2, characterized in that A feedback voltage is applied to a first input terminal of the comparator, and a reference voltage is applied to a second input terminal of the comparator.

4. The SMPS according to claim 3, characterized in that The first input terminal is a negative terminal of the comparator, and the second input terminal is a positive terminal of the comparator.

5. The SMPS according to claim 3, characterized in that The SMPS also includes a voltage divider coupled to the output terminal of the buck converter, the voltage divider configured to generate a scaled version of the output voltage of the buck converter.

6. The SMPS according to claim 5, characterized in that The SMPS further comprises: a ripple reconstructor coupled to the input / output I / O terminal of the buck converter and configured to generate a ripple voltage; and An adder circuit, wherein the adder circuit is configured to add the ripple voltage to a scaled version of the output voltage of the buck converter to generate a feedback voltage.

7. The SMPS according to claim 2, characterized in that The SMPS also includes a voltage checking circuit configured to compare an output voltage of the buck converter with a predetermined threshold.

8. The SMPS according to claim 2, characterized in that The duration of the pulse generated by the pulse generator is proportional to the ratio between the output voltage of the buck converter and the supply voltage of the pulse generator.

9. The SMPS according to claim 2, characterized in that The buck converter includes a gate driver circuit configured to drive one or more switches of the buck converter, wherein an output of the selection circuit is coupled to the gate driver circuit.

10. The SMPS according to claim 2, characterized in that The SMPS further includes a reference signal generator configured to generate a reference voltage, wherein an output terminal of the reference signal generator is coupled to an input terminal of the pulse width modulator and an input terminal of the comparator.

11. The SMPS according to claim 10, characterized in that The first voltage is zero.

12. The SMPS according to claim 11, characterized in that The reference voltage increases linearly from the first voltage to the second voltage.

13. An integrated circuit IC device, characterized in that: The integrated circuit IC device comprises: Buck converter; and A control circuit for a buck converter comprising: a comparator configured to compare a feedback voltage of the buck converter with a reference voltage increased from a first voltage to a second voltage; a pulse width modulator configured to generate a pulse width modulated (PWM) signal having a time-varying pulse width proportional to a value of a reference voltage; an AND gate configured to generate a first control signal by performing a logic AND operation on an output signal of the comparator and a PWM signal; a pulse generator configured to generate a second control signal by generating a pulse in response to a rising edge in an output signal of the comparator; and The selection circuit is configured to select the first control signal or the second control signal as the control signal of the buck converter based on the output voltage of the buck converter.

14. The IC device according to claim 13, wherein: The selection circuit is configured as: When the output voltage of the buck converter is lower than a predetermined threshold, selecting the first control signal as the control signal of the buck converter; and When the output voltage of the buck converter is higher than a predetermined threshold, the second control signal is selected as the control signal of the buck converter.

15. The IC device according to claim 14, wherein: The buck converter has one or more switches that are alternately turned on and off during normal operation of the buck converter, wherein a control signal of the buck converter controls the operation of the one or more switches during normal operation of the buck converter.

16. The IC device according to claim 14, wherein: The control circuit also includes a reference voltage generator configured to generate a reference voltage.

17. The IC device according to claim 14, wherein: The control circuit also includes a voltage check circuit configured to compare the output voltage of the buck converter with a predetermined threshold.

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