Semiconductor module and power module

Abstract

The utility model provides a semiconductor module and a power module. The semiconductor module comprises a substrate, a diverter and a Z-phase inverter circuit are arranged on the substrate, the inverter circuit is electrically connected with the diverter, and Z is a positive integer; each phase of inverter circuit comprises an upper bridge arm circuit and a lower bridge arm circuit, M conductive paths are formed between the upper bridge arm circuit and the lower bridge arm circuit, the upper bridge arm circuit is used for being connected with a positive electrode of a power supply, the lower bridge arm circuit is used for being connected with a negative electrode of the power supply, and M is a positive integer; wherein the projection of the at least one conductive path on the at least one plane has an intersection point so as to weaken the electromagnetic interference of the magnetic field formed by the conductive path on the diverter. According to the utility model, the stability that the power module executes sampling work through the internal shunt is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of power module design, in particular to a semiconductor module and a power module. Background Art

[0002] Power modules are widely used in rail transportation, aerospace, new energy vehicles, wind power generation and other industries. There are various types of power module packages, and the power inside different power modules is also different. In order to meet different product performance and reduce the complexity of peripheral circuit design, a shunt is built into the power module package.

[0003] Taking the IGBT power module as an example, the maximum current that can pass through the IGBT can reach thousands of amperes. When the power module is working, the power switching device in the power module will produce a large current change rate during the switching process, which will bring about EMC (electromagnetic compatibility) problems. The smaller the size of the power module, the greater the sampling impact on the shunt in the power module. Utility Model Content

[0004] To achieve the above objectives, the present application proposes a semiconductor module, aiming to improve the sampling stability and accuracy of a shunt built into the semiconductor module.

[0005] The present application proposes a semiconductor module, comprising:

[0006] A substrate, on which a shunt and a Z-phase inverter circuit are arranged, the inverter circuit is electrically connected to the shunt, and Z is a positive integer;

[0007] Each phase of the inverter circuit includes an upper bridge arm circuit and a lower bridge arm circuit, wherein M conductive paths are formed between the upper bridge arm circuit and the lower bridge arm circuit, the upper bridge arm circuit is used to connect to the positive pole of the power supply, and the lower bridge arm circuit is used to connect to the negative pole of the power supply, and M is a positive integer;

[0008] The projection of at least one conductive path on at least one plane has an intersection point, so as to weaken the electromagnetic interference of the magnetic field formed by the conductive path itself on the shunt.

[0009] Optionally, a projection of the conductive path on the plane where the substrate is located has an intersection point.

[0010] Optionally, a position on the conductive path corresponding to the intersection point has a first enclosed end and a second enclosed end, and an area enclosed by the conductive path between the first enclosed end and the second enclosed end forms a target area;

[0011] The first enclosed end and the second enclosed end of the conductive path are in contact with each other or are spaced apart from each other.

[0012] Optionally, the number of the target areas formed by the conductive path is multiple;

[0013] The distance between the shunt electrically connected to the inverter circuit corresponding to the conductive path and the smallest one of the target regions is smaller than the distance between the shunt and any other target regions.

[0014] Optionally, the first end of the upper bridge arm circuit, at least one power device chip in the upper bridge arm circuit, at least one power device chip in the lower bridge arm circuit and the second end of the lower bridge arm circuit are electrically connected in sequence through a plurality of connectors to form the conductive path.

[0015] Optionally, M is 2, and the two conductive paths are respectively a first conductive path and a second conductive path;

[0016] The first end of the upper bridge arm circuit, the IGBT power device chip in the upper bridge arm circuit, the diode chip in the lower bridge arm circuit and the second end of the lower bridge arm circuit are electrically connected in sequence through a plurality of connectors to form the first conductive path;

[0017] The first end of the upper bridge arm circuit, the diode chip in the upper bridge arm circuit, the IGBT power device chip in the lower bridge arm circuit and the second end of the lower bridge arm circuit form the second conductive path through a plurality of the connecting members.

[0018] Optionally, the types of the plurality of connectors include at least one of bonding wires, signal wires on at least one wiring layer of the substrate, a flexible printed circuit board, and a copper busbar.

[0019] Optionally, a first enclosed end of the conductive path is on a signal line disposed on the substrate; and a second enclosed end of the conductive path is on a binding line.

[0020] Optionally, the area enclosed by at least one of the plurality of connectors is the target area.

[0021] Optionally, the types of the plurality of connectors include at least one of bonding wires, signal wires on at least one wiring layer of the substrate, a flexible printed circuit board, and a copper busbar.

[0022] The present application also proposes a power module, comprising a plurality of pins and a semiconductor module as described above; the plurality of pins are electrically connected to a substrate of the semiconductor module, and the pins are used to electrically connect to at least one of a shunt and an inverter circuit in the semiconductor module.

[0023] Optionally, the plurality of pins include a positive power pin and at least one negative power pin;

[0024] The positive pin of the power supply is respectively connected to the first end of the upper bridge arm circuit in the inverter circuit of the Z phase;

[0025] At least one of the negative power supply pins is connected to the second end of the lower bridge arm circuit in the Z-phase inverter circuit in a one-to-one correspondence.

[0026] Optionally, at least one of the at least one negative power pin and the positive power pin are arranged on the same side of the substrate.

[0027] Optionally, when there are multiple negative power pins, negative power pins are respectively provided on both sides of the positive power pin on one side of the substrate.

[0028] Optionally, the substrate has a first side and a second side arranged opposite to each other; the plurality of pins further include at least one output pin; at least one output pin is electrically connected to an output end of the inverter circuit of the Z phase in a one-to-one correspondence;

[0029] In the Z-phase inverter circuit, the positive power pin and the negative power pin connected to at least one phase of the inverter circuit are arranged on the first side of the substrate, and the connected output pin is arranged on the second side of the substrate;

[0030] The shunt is arranged close to the output pin.

[0031] Optionally, the power module further comprises a braking circuit disposed on the substrate;

[0032] The plurality of pins also include a brake signal pin; the brake signal pin is electrically connected to the brake circuit;

[0033] The brake signal pin and the positive power pin are located on the same side of the substrate.

[0034] Optionally, the first end of the pin is arranged on the substrate, and the second end of the pin is arranged to extend out of the substrate; the second ends of the plurality of pins are arranged in a staggered manner in the direction in which the pins extend.

[0035] An embodiment of the present application proposes a semiconductor module, which includes a substrate, on which a shunt and a Z-phase inverter circuit are arranged, the inverter circuit is electrically connected to the shunt, and Z is a positive integer; each phase of the inverter circuit includes an upper bridge arm circuit and a lower bridge arm circuit, and M conductive paths are formed between the upper bridge arm circuit and the lower bridge arm circuit, the upper bridge arm circuit is used to connect to the positive pole of the power supply, and the lower bridge arm circuit is used to connect to the negative pole of the power supply, and M is a positive integer; wherein the projection of at least one conductive path on at least one plane has an intersection to weaken the electromagnetic interference of the magnetic field formed by the conductive path itself on the shunt.

[0036] Since the projections of the conductive paths on at least one plane have an intersection, the conductive paths themselves must have overlapping portions on at least one plane. During the use of the semiconductor module, when current flows through the conductive paths in the inverter circuit, the overlapping portions on at least one plane will cause different current directions on the conductive paths, causing the magnetic fields generated by the currents on the conductive paths to partially cancel each other out, thereby weakening the strength of the magnetic field generated by the entire conductive path when current flows through it, thereby reducing the interference and influence of the magnetic field caused by the current on the shunt sampling work, improving the electromagnetic compatibility problem, and effectively improving the sampling stability and sampling accuracy of the shunt built into the semiconductor module.

[0037] Through the above-mentioned settings in the semiconductor module provided in the present application, the influence of the magnetic field generated by the current flowing through the inverter circuit in the power module on the shunt can be reduced. Therefore, when designing a power module with a built-in shunt, the size of the power module can be reduced and the power density can be improved, which is conducive to expanding the application of power modules with built-in shunts to products with high power density requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0039] Figure 1 is a schematic diagram of a power topology within a power module provided in an embodiment of the present application;

[0040] Figure 2 is a schematic structural diagram of a semiconductor module provided in an embodiment of the present application;

[0041] Figure 3 is a schematic structural diagram of an intersection of a semiconductor module corresponding to a target area provided in an embodiment of the present application;

[0042] Figure 4 is a schematic diagram of the structure at the intersection of the semiconductor module corresponding to the target area provided in an embodiment of the present application;

[0043] Figure 5 is a schematic diagram of a local structure of a semiconductor module provided in an embodiment of the present application;

[0044] Figure 6 is a schematic diagram of another power topology within a power module provided in an embodiment of the present application;

[0045] Figure 7 It is a schematic diagram of the position of the signal pins of a shunt in a power module provided in an embodiment of the present application;

[0046] Figure 8 This is a schematic diagram of the position of the shunt signal pin arrangement in another power module provided in an embodiment of the present application;

[0047] Fig. 9 is a schematic diagram of a conductive path provided in an embodiment of the present application having an intersection projected on a plane;

[0048] Fig.10 It is a schematic diagram of a conductive path provided in an embodiment of the present application projected onto another plane with an intersection.

[0049] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0050] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0051] It should be noted that if the embodiments of the present application involve directional indications (such as up, down, left, right, front, back...), the directional indications are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0052] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present application, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or suggesting their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0053] The present application embodiment provides a semiconductor module, such as Figure 2 As shown, including:

[0054] A substrate 10, on which a shunt and a Z-phase inverter circuit are arranged, the inverter circuit is electrically connected to the shunt, and Z is a positive integer;

[0055] Each phase inverter circuit includes an upper bridge arm circuit and a lower bridge arm circuit, wherein M conductive paths are formed between the upper bridge arm circuit and the lower bridge arm circuit, the upper bridge arm circuit is used to connect to the positive pole of the power supply, and the lower bridge arm circuit is used to connect to the negative pole of the power supply, and M is a positive integer;

[0056] The projection of at least one conductive path on at least one plane has an intersection 20 to weaken the electromagnetic interference of the magnetic field formed by the conductive path itself on the shunt.

[0057] In this embodiment, the substrate 10 can be implemented by a ceramic substrate, a silicon substrate, an aluminum substrate, etc., and the substrate 10 can be provided with multiple mounting areas, current-carrying areas, wafer carrier areas, etc. for placing devices in the Z-phase inverter circuit and shunts electrically connected to the inverter circuit.

[0058] The conductive path formed includes any one of the power switch device in the upper arm circuit or the power switch device in the lower arm circuit. Figure 1 , Figure 1 shows a power topology within a semiconductor module, Figure 1 The inverter circuit includes three phases, namely, a U phase inverter circuit, a V phase inverter circuit, and a W phase inverter circuit. Figure 1 Two conductive paths are formed between the upper bridge arm circuit and the lower bridge arm circuit of each phase inverter circuit.

[0059] by Figure 1 Taking the U-phase inverter circuit in as an example, there are two conductive paths, that is, two commutation paths in the U-phase inverter circuit, which are as follows: starting from the positive pole P of the power supply, passing through the upper bridge arm power switch Q1 and the lower bridge arm diode chip D2 and finally to the negative pole N1 of the power supply; and, starting from the positive pole P of the power supply, passing through the upper bridge arm diode chip D1 and the lower bridge arm power switch Q2 and finally to the negative pole N1 of the power supply.

[0060] In addition, Figure 1 On the basis of the U-phase inverter circuit shown, in order to improve the overcurrent capacity of the U-phase inverter circuit, multiple parallel IGBT power device chips are set in any bridge arm circuit of the U-phase inverter circuit, and the corresponding multiple parallel IGBT power device chips will correspondingly form multiple conductive paths.

[0061] When current flows or changes on the conductive path in the inverter circuit, a magnetic field of a certain intensity will be generated. This magnetic field is formed by the conductive path itself and will affect the shunt connected to the inverter circuit where the conductive path itself is located and / or the shunt connected to other inverter circuits.

[0062] In order to reduce the electromagnetic interference to the shunt, the projection of at least one conductive path on at least one plane has an intersection 20 to weaken the electromagnetic interference of the magnetic field formed by the conductive path itself on the shunt. When designing the conductive path in the semiconductor module, the devices included in the conductive path and / or the connectors between the devices can be arranged on the substrate 10 so that the projection of the entire conductive path on at least one plane has an intersection 20.

[0063] In one example, reference Fig. 9 , Fig. 9 The A end and the B end shown in the figure are two ends of a conductive path, and current flows from the A end to the B end. The projection of the conductive path on the substrate has an intersection point 20.

[0064] In another example, refer to Fig.10 , Fig.10 The A end and the B end shown in the figure are two ends of another conductive path, and the current flows from the A end to the B end. The projection of the conductive path on a surface perpendicular to the substrate has an intersection 20.

[0065] Since the projections of the conductive paths on at least one plane have an intersection, the conductive paths themselves must have overlapping portions on at least one plane. Therefore, during the use of the semiconductor module, when current flows through the conductive paths in the inverter circuit, the overlapping portions on at least one plane will cause different current directions on the conductive paths, causing the magnetic fields generated by the currents on the conductive paths to partially cancel each other out, thereby weakening the strength of the magnetic field generated by the entire conductive path when current flows through it, thereby reducing the interference and influence of the magnetic field caused by the current on the shunt sampling work, improving the electromagnetic compatibility problem, and effectively improving the sampling stability and sampling accuracy of the shunt built into the semiconductor module.

[0066] Through the above-mentioned settings in the semiconductor module provided in the present application, the influence of the magnetic field generated by the current flowing through the inverter circuit in the power module on the shunt can be reduced. Therefore, when designing a power module with a built-in shunt, the size of the power module can be reduced and the power density can be improved, which is conducive to expanding the application of power modules with built-in shunts to products with high power density requirements.

[0067] Optionally, in an optional embodiment based on the above embodiment, the position of the corresponding intersection on the conductive path has a first enclosed end and a second enclosed end, and the area enclosed by the conductive path between the first enclosed end and the second enclosed end forms a target area 20 .

[0068] Optionally, the first enclosed end and the second enclosed end can be arranged in contact with each other. For example, the parts on the conductive path corresponding to the first enclosed end and the second enclosed end are both connectors wrapped with insulating material, such as enameled wire, so that the first enclosed end and the second enclosed end can contact each other, thereby effectively reducing the height of the entire semiconductor module, and then reducing the height of the entire power module.

[0069] Optionally, the first enclosed end and the second enclosed end may also be spaced apart, that is, the first enclosed end and the second enclosed end do not contact each other in space. For example, the portion corresponding to the first enclosed end on the conductive path is the binding wire, and the portion corresponding to the second enclosed end on the conductive path is the metal copper foil on the substrate 10. With such a configuration, there is no need to perform insulation treatment between the first enclosed end and the second enclosed end, which can effectively reduce the complexity of the conductive path design.

[0070] Optionally, the number of target areas 30 may be one or more. Setting multiple target areas 30 can enhance the ability to weaken the magnetic field generated by the current on the conductive path, but may increase the difficulty of device layout in the semiconductor module and increase the size of the semiconductor module; setting a single target area 30 makes it easier for semiconductor module designers to arrange the inverter circuit on the substrate 10, which can effectively reduce the design complexity.

[0071] Optionally, the target area 30 may be in the shape of a circle, an ellipse, a regular polygon, an irregular polygon, etc. Preferably, the target area 30 may be as close to a circle and a regular polygon as possible, and the distance in the vertical space between the paths corresponding to the first enclosed end and the second enclosed end on the conductive path may be as close as possible, so as to achieve the best magnetic field weakening effect.

[0072] When current flows on the conductive path, especially when current flows on the path corresponding to the target area 30 formed on the conductive path, since the projection of the target area 30 on a plane is a closed area, the magnetic fields formed by the currents in different directions flowing on the path corresponding to the target area 30 will cancel each other out, thereby weakening the strength of the magnetic field generated by the current flowing on the entire conductive path, thereby effectively reducing the impact on the shunt set in the semiconductor module, and effectively improving the stability and accuracy of the shunt in performing sampling work.

[0073] Optionally, a Z-phase inverter circuit, such as a one-phase, two-phase or three-phase inverter circuit, may be provided on the substrate 10; wherein, at least one phase of the inverter circuit in the multi-phase inverter circuit may be connected to a shunt, and the number of shunts in the inverter circuit connected to the shunt may be one or more. Figure 1 The circuit shown in Figure 1The circuit shown is a three-phase inverter circuit. Each phase inverter circuit is connected to a shunt. The U-phase inverter circuit is connected to the shunt RES1, the V-phase inverter circuit is connected to the shunt RES2, and the W-phase inverter circuit is connected to the shunt RES3.

[0074] Optionally, when the inverter circuit is multi-phase, a target area 30 is set on the conductive path of at least one phase of the inverter circuit. For example, in a three-phase inverter circuit, the target area can be set in a one-phase inverter circuit, a two-phase inverter circuit or a three-phase inverter circuit, respectively.

[0075] Optionally, in an inverter circuit in which a target region is set for any phase, a target region may be set for at least one conductive path. Figure 1 Take the three-phase inverter circuit in as an example. In the three-phase inverter circuit, each phase inverter circuit has two conductive paths, and at least one target area is arranged on each conductive path.

[0076] Optionally, within the semiconductor module, the target area for reducing electromagnetic interference to a certain shunt A can be formed on a conductive path of an inverter circuit connected to the shunt A, or can be formed on a conductive path of an inverter circuit not connected to the shunt A; in this way, the complexity of setting the inverter circuit layout on the substrate for designers can be reduced.

[0077] In one embodiment of the present application, the first end of the upper bridge arm circuit, at least one power device chip in the upper bridge arm circuit, at least one power device chip in the lower bridge arm circuit and the second end of the lower bridge arm circuit are electrically connected in sequence through multiple connectors to form a conductive path.

[0078] In an optional embodiment of the present application, the conductive path can be formed by multiple power device chips in the upper bridge arm and the lower bridge arm, such as a switch power chip, a diode chip, etc., and connectors connecting the power device chips. The connectors can be at least one of a bonding wire, a signal line on at least one wiring layer on a substrate, a flexible circuit board, and a copper bus.

[0079] In an optional embodiment, M is 2, that is, two conductive paths are formed between the upper bridge arm circuit and the lower bridge arm circuit. Figure 1 The power topology shown in Figure 2 In the structural schematic diagram of the semiconductor module shown, the first end of the upper bridge arm circuit, the IGBT power device chip in the upper bridge arm circuit, the diode chip in the lower bridge arm circuit and the second end of the lower bridge arm circuit are electrically connected in sequence through multiple connectors to form a first conductive path; the first end of the upper bridge arm circuit, the diode chip in the upper bridge arm circuit, the IGBT power device chip in the lower bridge arm circuit and the second end of the lower bridge arm circuit are electrically connected in sequence through multiple connectors to form a second conductive path.

[0080] Optionally, the first enclosed end and the second enclosed end on the conductive path used to form the intersection may be of different types, for example, the portion of the conductive path corresponding to the first enclosed end is a power device chip, and the portion corresponding to the second enclosed end is a connector.

[0081] In an example, Figure 3 As shown, the power device chip on the substrate 10 and the space directly above the power device chip, which spans the power device chip, such as the binding wire or the copper busbar, the projection on the plane where the substrate 10 is located forms an intersection 20; or, the substrate 10 is provided with a plurality of wiring layers, including a top wiring layer, a bottom wiring layer and at least one middle wiring layer arranged between the top wiring layer and the bottom wiring layer, the power device chip is arranged on the top wiring layer of the substrate 10, and the copper foil signal line is arranged at the position corresponding to the power device chip in the middle wiring layer, and the power device chip on the top wiring layer and the copper foil signal line arranged on the middle wiring layer corresponding to the power device chip form the above-mentioned intersection 20 on the projection on the plane where the substrate 10 is located.

[0082] Optionally, the first enclosed end and the second enclosed end on the conductive path used to form the intersection may be of the same type, for example, the portion of the conductive path corresponding to the first enclosed end is a connector, and the portion of the conductive path corresponding to the second enclosed end is also another connector.

[0083] For example, a first enclosed end of the conductive path is on a signal line disposed on the substrate, and a second enclosed end of the conductive path is on a binding line.

[0084] In one example, refer to Figure 2 The portion corresponding to the first enclosed end used to form the intersection 20 is a binding wire used to establish a connection between the negative power pin and the IGBT power device chip, and the portion corresponding to the second enclosed end used to form the intersection 20 is a copper foil on the substrate 10 serving as a signal line.

[0085] In another example, Figure 4 As shown, the projections of connectors 1 and 2 belonging to the same conductive path on the plane where substrate 10 is located form an intersection 20, wherein connector 1 is a copper foil arranged on the top wiring layer, and connector 2 is a copper foil arranged on the middle wiring layer.

[0086] Optionally, at least one of the first end of the upper bridge arm circuit and the second end of the lower bridge arm circuit is a current-carrying region corresponding to a positive power pin or a negative power pin on the substrate.

[0087] Optionally, at least one of the first end of the upper bridge arm circuit and the second end of the lower bridge arm circuit is an end of a power device chip on the conductive path. For example, the first end of the upper bridge arm circuit is the collector of the IGBT power chip in the upper bridge arm circuit, and the second end of the lower bridge arm circuit is the emitter of the IGBT power chip in the lower bridge arm circuit.

[0088] In one example, refer to Figure 2 , taking the conductive path formed on a one-phase (W-phase) inverter circuit as an example for explanation, the two conductive paths are two commutation loops of the W-phase inverter circuit, the upper bridge arm circuit includes a W-phase upper bridge arm IGBT power device chip Q5 and a W-phase upper bridge arm diode chip D5 electrically connected to each other, the lower bridge arm circuit includes a second IGBT power device chip and a W-phase lower bridge arm diode chip D6 electrically connected to each other, and an upper bridge arm current-carrying area, a lower bridge arm current-carrying area 50 and a negative current-carrying area for carrying a negative power supply pin N are provided on the substrate 10; wherein the lower bridge arm current-carrying area 50 carries the W-phase lower bridge arm IGBT power device chip Q6 and the W-phase lower bridge arm diode chip D6, and the negative current-carrying area The current carrying area is electrically connected to the W-phase lower bridge arm IGBT power device chip Q6 through the first connecting member L1, and the W-phase lower bridge arm diode chip D6 is electrically connected to the upper bridge arm current carrying area through the second connecting member; the upper bridge arm current carrying area has a first part 41 and a second part 42, the first part 41 carries the W-phase upper bridge arm IGBT power device chip Q5 and the W-phase upper bridge arm diode chip D5, the first part 41 and the lower bridge arm current carrying area 50 are arranged in sequence along the width direction of the substrate 10, one end of the second part 42 is connected to the positive power supply pin P, and the other end of the second part 42 is electrically connected to the first part 41, and the second part 42 is arranged through the gap between the first connecting member L1 and the substrate 10.

[0089] In conductive path 1, after the current flows in from the positive pin of the power supply, it passes through the W-phase upper bridge arm IGBT power device chip Q5 of the upper bridge arm circuit and the W-phase lower bridge arm diode chip D6 of the lower bridge arm circuit, and finally flows out from the negative pin of the power supply N3; in conductive path 2, after the current flows in from the positive pin of the power supply, it passes through the W-phase upper bridge arm diode chip D5 of the upper bridge arm circuit and the W-phase lower bridge arm IGBT power device chip Q6 of the lower bridge arm circuit, and finally flows out from the negative pin of the power supply N3. Since the two conductive paths each form an intersection 20 on the projection of the plane where the substrate 10 is located, that is, a target area 30 having the effect of reducing the magnetic field generated by the current is set corresponding to each conductive path, the electromagnetic interference to the shunt connected to the W-phase inverter circuit can be reduced. At the same time, the target area 30 is also formed by the positional arrangement between the devices and connectors in the semiconductor module. Compared with the design in the prior art, the wiring area for placing the inverter circuit on the substrate 10 will not increase too much or even will not increase at all, thereby minimizing the wiring space of the inverter circuit with the target area 30 and effectively improving the integration of the entire semiconductor module.

[0090] In an optional embodiment of the present application, the area enclosed by at least one of the plurality of connectors is the target area 30 .

[0091] In the embodiment of the present application, when laying out the devices and wirings in the semiconductor module, the target area 30 can be formed by using only the connectors. Figure 5 An upper bridge arm circuit current-carrying area 60 and a lower bridge arm circuit current-carrying area 70 are provided on the substrate 10. A current-carrying area for connecting to the positive power supply pin P is provided near the upper bridge arm circuit current-carrying area 60, and a current-carrying area for connecting to the negative power supply pin N is provided near the lower bridge arm circuit current-carrying area 70. The connector between the upper bridge arm circuit and the lower bridge arm circuit is realized by copper foil and a binding wire L2. The copper foil includes a first part B1, a second part B2 and a third part B3. The first part B1 is provided on the top wiring layer of the substrate 10 and is electrically connected to the upper bridge arm circuit current-carrying area 60. The second part B2 is provided on the middle wiring layer of the substrate 10 and is electrically connected to the first part B1 through a through hole. The third part B3 is provided on the top wiring layer and is electrically connected to the second part B2 through a through hole, and the third part B3 is electrically connected to the binding wire. The projections of the first part B1 and the second part B2 of the copper foil on the plane where the substrate 10 is located have an intersection 20, thereby forming a target area 30. By independently arranging the connectors to form the target area 30, there is no need to deliberately place the power device chips in the upper and lower bridge arm circuits, thereby reducing the design complexity of the semiconductor module.

[0092] Optionally, in an optional embodiment based on the above embodiment, the number of target areas 30 formed by the conductive path is multiple; the distance between the shunt electrically connected to the inverter circuit corresponding to the conductive path and the smallest one of the multiple target areas 30 is smaller than the distance between the shunt and any other target area 30.

[0093] In this embodiment, when multiple target areas 30 are formed on a conductive path, the shunt connected to the inverter circuit where the conductive path is located is closest to the smallest one of the multiple target areas 30 formed on the conductive path. It can be understood that the target area 30 partially weakens the magnetic field generated by the current flowing through the conductive path, so the smaller the target area 30 closest to the shunt is, the smaller the impact on the shunt is. For example, there is a conductive path 1 in the U-phase inverter circuit, and target areas 1 and 2 are formed on the conductive path 1. The area of ​​target area 1 is larger than that of target area 2. Then, when the designer sets the position of the shunt connected to the U-phase inverter circuit, the shunt connected to the U-phase inverter circuit needs to be set close to the target area 2 and away from the target area 1. Through the above settings, not only can the magnetic field generated when the current flows through the conductive path be more effectively weakened, but the impact of the magnetic field generated by the current on the shunt can also be further reduced.

[0094] In an optional embodiment based on the above embodiment, in a multi-phase inverter circuit, if the conductive path in each phase inverter circuit forms multiple target areas 30. Then when arranging and setting the shunts connected to the inverter circuits of different phases, for any shunt, at least one target area 30 close to the shunt is a close target area 30, and each close target area 30 is the smallest one among the multiple target areas 30 in the inverter circuit corresponding to itself. For example, there are three target areas close to the shunt electrically connected to the U-phase inverter circuit, namely, the target area 11 in the U-phase inverter circuit, the target area 12 in the V-phase inverter circuit, and the target area 13 in the W-phase inverter circuit. The target area 11 is the smallest one among the multiple target areas in the U-phase inverter circuit, the target area 12 is the smallest one among the multiple target areas in the V-phase inverter circuit, and the target area 13 is the smallest one among the multiple target areas in the W-phase inverter circuit. In this way, for any shunt, the impact of the magnetic field generated by the conductive path corresponding to the shunt itself and the magnetic field generated by the conductive paths in other inverter circuits is minimized, which is conducive to further improving the accuracy and stability of the sampling work of multiple shunts built into the power module.

[0095] Optionally, in an optional embodiment based on the above embodiment, the shunt and the inverter circuit electrically connected to the shunt are arranged at intervals on the substrate 10 .

[0096] In this embodiment, when the designer sets the position of the shunt, the shunt can be placed as far away from the inverter circuit electrically connected to the shunt itself as possible, thereby minimizing the influence of the magnetic field generated by the current flowing through the inverter circuit on the operation of the shunt. Furthermore, the shunt can also be set at a distance from any inverter circuit, that is, when the designer sets the position of the shunt, the shunt is designed as far away from each inverter circuit as possible, thereby further improving the accuracy and stability of the sampling work of multiple shunts built into the power module.

[0097] refer to Figure 2 The embodiment of the present application also proposes a power module, including multiple pins and a semiconductor module as shown in any of the above embodiments; the multiple pins are electrically connected to the substrate 10 of the semiconductor module, and the pins are used to electrically connect to at least one of the shunt and the inverter circuit in the semiconductor module.

[0098] It is worth noting that since the power module provided in the embodiment of the present application includes all technical solutions of all embodiments of the above-mentioned multiple semiconductor modules, it at least has all the beneficial effects brought by the technical solutions of the above-mentioned semiconductor modules, which will not be described one by one here.

[0099] In the embodiment of the present application, the plurality of pins include a positive power pin, a negative power pin, an output pin, a shunt signal pin, etc., and the number of each type of pin is at least one. One end of the pin is used to connect to a current-carrying area on the substrate 10, or to be electrically connected to a phase inverter circuit through a connector, and the other end of the pin extends to the outside of the housing of the power module, thereby realizing electrical connection between the peripheral circuit and the internal circuit of the power module through the pin.

[0100] refer to Figure 2 and Figure 1 In an optional embodiment of the present application, the multiple pins include a positive power pin and at least one negative power pin; the positive power pin is respectively connected to the first end of the upper bridge arm circuit in the Z-phase inverter circuit; and at least one negative power pin is connected to the second end of the lower bridge arm circuit in the Z-phase inverter circuit in a one-to-one correspondence.

[0101] In the present embodiment of the application, reference Figure 1 It can be seen from the power topology that in the power module, the positive power supply connected to the first end of the upper bridge arm circuit in each inverter circuit can be the same positive power supply. Therefore, when the number of Z is greater than 1, that is, when the number of phases of the inverter circuit in the power module is multiple, the positive power supply pins connected to the first end of the upper bridge arm circuit in each inverter circuit are integrated together, which can reduce the total number of pins of the power module, effectively save the space required for setting the pins of the power module, and improve the integration of the power module.

[0102] Optionally, the number of negative power supply pins is Z, and the second end of the lower bridge arm circuit of each phase inverter circuit is connected to a negative power supply pin.

[0103] In an optional embodiment, at least one of the at least one negative power pin and the positive power pin are disposed on the same side of the substrate 10 .

[0104] The conductive path in the inverter circuit is from the first end of the upper bridge arm circuit to the second end of the lower bridge arm circuit, that is, from the positive power pin connected to the inverter circuit to the negative power pin connected to the inverter circuit. When the positive power pin and the negative power pin of a certain inverter circuit are arranged on the same side, the area enclosed by the conductive path on the substrate 10 can be minimized, which is conducive to further reducing the influence of the magnetic field generated by the current on the inverter circuit on the shunt. For example, when there is only one-phase inverter circuit in the power module, that is, the number of negative power pins is only one, the positive power pin and the negative power pin can be arranged on the same side; when there are multi-phase inverter circuits in the power module, that is, the number of negative power pins is multiple, at least one of the multiple negative power pins can be arranged on the same side as the positive power pin.

[0105] refer to Figure 2 In one embodiment, when the number of the negative power supply pins is plural, negative power supply pins are respectively provided on both sides of the positive power supply pin on one side of the substrate 10 .

[0106] Part of the negative power pins may be arranged on the same side as the positive power pins, or all the negative power pins may be arranged on the same side as the positive power pins. When a plurality of negative power pins and a positive power pin are arranged on the same side of the substrate 10, the positive power pin may be arranged between the plurality of negative power pins, that is, at least one negative power pin is arranged on each side of the positive power pin. For example, Figure 2 , a negative power pin N1 is provided on the left side of the positive power pin P, and negative power pins N2 and N3 are provided on the right side of the positive power pin P. Compared with the solution that no negative power pin is provided on one side of the positive power pin and a negative power pin is provided on the other side, such a configuration can further reduce the area enclosed by the conductive paths between the positive power pin and each negative power pin on the substrate 10, thereby further reducing the influence of the magnetic field generated by the current on all the inverter circuits on any shunt.

[0107] Based on any of the above embodiments, in an optional embodiment of the present application, the substrate 10 has a first side and a second side arranged opposite to each other; the plurality of pins further include at least one output pin; the at least one output pin is electrically connected to an output end of the Z-phase inverter circuit in a one-to-one correspondence;

[0108] In the Z-phase inverter circuit, the positive power pin and the negative power pin connected to at least one phase inverter circuit are arranged on the first side of the substrate 10 and the connected output pin is arranged on the second side of the substrate 10;

[0109] The shunt is placed close to the output pins.

[0110] In an embodiment of the present application, when the shunt in each phase inverter circuit is spaced apart from the positive power pin and the negative power pin, the distance between the shunt and the inverter circuit can be effectively reduced, that is, the distance from the conductive path in the inverter circuit can be reduced, thereby further reducing the influence of the magnetic field generated by the current flowing through the inverter circuit on the shunt.

[0111] The shunt in the power module is mainly used to detect the current output by the output pin. The shunt can be set in series in the path between the output pin and the connection point of the upper and lower bridge arm circuits in the inverter circuit. When the shunt is set close to the output pin and the output pin and the positive and negative pins of the power supply are not on the same side, it can not only make the shunt away from the inverter circuit body and the positive and negative pins of the power supply to reduce the influence of the magnetic field generated by the current in the inverter circuit on itself, but also simplify the device layout inside the power module.

[0112] The output pin is arranged at the edge of the substrate 10, and the shunt is also arranged close to the edge of the substrate 10, which in turn reduces the distance between the two ends of the shunt and the two shunt signal pins arranged at the edge of the substrate 10, thereby improving the accuracy of current sampling by the peripheral circuit using the shunt inside the power module.

[0113] For example, refer to Figure 2 ,by Figure 2 Take the U-phase inverter circuit as an example to explain. Figure 2 The negative power pin N1 and the positive power pin P of the U-phase inverter circuit are on the first side of the substrate 10 , the U-phase output pin U is on the second side of the substrate 10 , and the shunt in the U-phase inverter circuit is arranged close to the output pin U.

[0114] In addition, power circuits with different functions may be provided in the power module. In addition to the inverter circuit, the power module also includes a braking circuit.

[0115] In an alternative embodiment based on the above embodiment, reference is made to Figure 6 When the power module is provided with a braking circuit and an inverter circuit at the same time, as shown in the power topology Figure 2 As shown, the plurality of pins also include a brake signal pin BR; the brake signal pin BR is electrically connected to the brake circuit; and the brake signal pin BR and the power positive pin P are located on the same side of the substrate 10 .

[0116] In the embodiment of the present application, Figure 6 The power topology shown shows that the brake circuit is connected to the power pin P. Figure 2 In order to reduce the complexity of the pin layout in the entire power module and the circuit layout on the substrate 10, the brake signal pin BR and the positive power pin N of the brake circuit can be directly set on the same side of the substrate 10, reducing the wiring area of ​​the brake circuit.

[0117] Optionally, the brake signal pin BR of the brake circuit is disposed adjacent to the positive power pin N on the same side of the substrate 10 .

[0118] A shunt is provided inside the power module. In order for the peripheral circuit to obtain the sampling result of the shunt, for example, the voltage at both ends of the shunt, two shunt signal pins are provided on the power module corresponding to each shunt for leading the voltage signal at both ends of the shunt to the peripheral circuit. If there is a three-phase inverter circuit in the power module and each inverter circuit is provided with a shunt, then six shunt signal pins need to be provided, and the added shunt signal pins need to be kept at a safe distance, which will inevitably lead to an increase in the volume of the power module, which is not conducive to the miniaturization design of the power module.

[0119] To this end, in an optional embodiment based on any of the above embodiments, the first end of the pin is arranged on the substrate 10, and the second end of the pin is arranged extending out of the substrate 10; the second ends of the plurality of pins are staggered in the direction in which the pins extend.

[0120] In an embodiment of the present application, for each phase inverter circuit connected to a shunt, a first shunt signal pin and a second shunt signal pin are respectively set, the first shunt signal pin and the second shunt signal pin are adjacent to each other, and the second end of the first shunt signal pin and the second end of the second shunt signal pin are staggered in the pin extension direction.

[0121] refer to Figure 6 , take the two signal pins of the U-phase shunt, namely the first shunt signal pin U1 and the second shunt signal pin U2 as an example for explanation, refer to Figure 7 , the distances of the second ends of the first shunt signal pin U1 and the second shunt signal pin U2 extending out of the power module in the pin extension direction are different, but the positions of the first ends on the substrate 10 are aligned; or, refer to Figure 8 The first shunt signal pin U1 and the second shunt signal pin U2 have the same length, but are staggered at the first end on the substrate 10 so that the second end of the first shunt signal pin U1 and the second end of the second shunt signal pin U2 are staggered in the pin extension direction.

[0122] Through the above arrangement, when two signal pins corresponding to a shunt are arranged in the power module, since the second ends of the two shunt signal pins are staggered in the direction of the pin extension, the isolation gap between the two shunt signal pins is increased, and while the two adjacent shunt signal pins meet the power electrode electrical gap requirements, the spacing between the two adjacent pins is reduced, thereby reducing the volume of the power module, improving the power density of the power module, and reducing the module cost. At the same time, the staggered arrangement of the pins also facilitates the internal wiring of the power module and improves the space utilization of the power module.

[0123] Optionally, based on the above optional embodiment, the pin further includes an emitter pin of an upper bridge arm switch tube connected to one end of the shunt. Figure 1 or Figure 6 As shown, the emitter pin Ue1 of the upper bridge arm switch tube of the U-phase inverter circuit is provided.

[0124] When designing a power module, the positions and the misalignment relationships between the positive power pin, negative power pin, output pin, brake signal pin, shunt signal pin and other pins of the power module are set according to the actual performance requirements and size requirements of the power module.

[0125] The above contents are only optional embodiments of the present application and are not intended to limit the patent scope of the present application. All equivalent structural changes made using the contents of the present application specification and drawings under the application concept of the present application, or direct / indirect application in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A semiconductor module, characterized in that: include: A substrate, on which a shunt and a Z-phase inverter circuit are arranged, the inverter circuit is electrically connected to the shunt, and Z is a positive integer; Each phase of the inverter circuit includes an upper bridge arm circuit and a lower bridge arm circuit, wherein M conductive paths are formed between the upper bridge arm circuit and the lower bridge arm circuit, the upper bridge arm circuit is used to connect to the positive pole of the power supply, and the lower bridge arm circuit is used to connect to the negative pole of the power supply, and M is a positive integer; The projection of at least one conductive path on at least one plane has an intersection point, so as to weaken the electromagnetic interference of the magnetic field formed by the conductive path itself on the shunt.

2. The semiconductor module according to claim 1, wherein: The projections of the conductive paths on the plane where the substrate is located have an intersection point.

3. The semiconductor module according to claim 1, wherein: The position on the conductive path corresponding to the intersection point has a first enclosed end and a second enclosed end, and the area enclosed by the conductive path between the first enclosed end and the second enclosed end forms a target area; The first enclosed end and the second enclosed end of the conductive path are in contact with each other or are spaced apart from each other.

4. The semiconductor module according to claim 3, characterized in that The number of the target areas formed by the conductive paths is multiple; The distance between the shunt electrically connected to the inverter circuit corresponding to the conductive path and the smallest one of the target regions is smaller than the distance between the shunt and any other target regions.

5. The semiconductor module according to any one of claims 1 to 4, characterized in that: The first end of the upper bridge arm circuit, at least one power device chip in the upper bridge arm circuit, at least one power device chip in the lower bridge arm circuit and the second end of the lower bridge arm circuit are electrically connected in sequence through a plurality of connectors to form the conductive path.

6. The semiconductor module according to claim 5, characterized in that M is 2, and the two conductive paths are respectively a first conductive path and a second conductive path; The first end of the upper bridge arm circuit, the IGBT power device chip in the upper bridge arm circuit, the diode chip in the lower bridge arm circuit and the second end of the lower bridge arm circuit are electrically connected in sequence through a plurality of connectors to form the first conductive path; The first end of the upper bridge arm circuit, the diode chip in the upper bridge arm circuit, the IGBT power device chip in the lower bridge arm circuit and the second end of the lower bridge arm circuit form the second conductive path through a plurality of the connecting members.

7. The semiconductor module according to claim 5, characterized in that Types of the plurality of connectors include at least one of bonding wires, signal lines on at least one wiring layer of the substrate, a flexible printed circuit board, and a copper busbar.

8. The semiconductor module according to claim 3, characterized in that The first enclosed end of the conductive path is on a signal line arranged on the substrate; the second enclosed end of the conductive path is on a binding line.

9. A power module, characterized in that: It comprises a plurality of pins and a semiconductor module as claimed in any one of claims 1 to 8; the plurality of pins are electrically connected to a substrate of the semiconductor module, and the pins are used to be electrically connected to at least one of a shunt and an inverter circuit in the semiconductor module.

10. The power module according to claim 9, characterized in that: The plurality of pins include a positive power pin and at least one negative power pin; At least one of the at least one negative power pin is disposed on the same side of the substrate as the positive power pin; When the number of the negative power supply pins is plural, the negative power supply pins are respectively arranged on both sides of the positive power supply pin on one side of the substrate.

11. The power module according to claim 9 or 10, characterized in that: The first end of the pin is arranged on the substrate, and the second end of the pin is arranged to extend out of the substrate; the second ends of the plurality of pins are arranged to be staggered in the direction in which the pins extend.

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