Photonic device

Abstract

The utility model provides a photonic device. The edge coupler has a wide end, a narrow end, and a gradually changing thickness. The narrow end is coupled to a waveguide in a photonic integrated circuit (PIC). The wide end is coupled to an optical transmitter or an optical receiver. The edge coupler is thickened into the buried oxide layer of the box substrate by gradually changing the thickness down. The upper surface of the edge coupler may be planar. A susceptor may be formed in the oxide layer such that a laser diode mounted on the susceptor will be aligned with the edge coupler in a vertical direction. Alternatively, a susceptor may be formed in the substrate below the oxide layer such that the core of the optical fiber mounted on the susceptor will be aligned with the edge coupler in the vertical direction. The base may be in the cavity, facilitating horizontal alignment between the laser diode, fiber, or other such device and the edge coupler.

Description

Technical Field

[0001] The utility model relates to a photon device. Background Art

[0002] Photonic integrated circuits (PICs) are widely used in the field of communications and are increasingly used in sensing and computing. Photonic integrated circuits can operate at higher speeds than electrical integrated circuits (ICs) and can be used in conjunction with ICs to enhance functionality. A photonic integrated circuit includes two or more photonic devices coupled to form a circuit. Examples of photonic devices include waveguides, splitters, multiplexers, filters, modulators, sensors, and switches. A photonic integrated circuit can be connected to an optical transmitter or optical receiver (such as a laser or optical fiber) via a grating coupler, edge coupler, or the like. Utility Model Content

[0003] The utility model provides a photonic device, comprising: a photonic integrated circuit, comprising a waveguide; and an edge coupler, which has a narrow end, a wide end, a narrow end thickness and a wide end thickness; wherein the edge coupler is coupled to the waveguide at the narrow end; the edge coupler has a width that narrows between the wide end and the narrow end; and the edge coupler has a thickness that gradually changes from the wide end thickness to the narrow end thickness in a first region between the wide end and the narrow end.

[0004] The utility model provides a photonic device, comprising: an oxide layer; a photonic integrated circuit, comprising a waveguide arranged on the oxide layer; an optical transmitter or an optical receiver mounted on a base, wherein the top of the base is lower than the bottom of the waveguide; and an edge coupler, which is arranged on the oxide layer and couples the optical transmitter or the optical receiver to the waveguide, wherein the edge coupler gradually changes its thickness downward and reaches the oxide layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0006] Figure 1A A cross-sectional view of a photonic device according to some embodiments is shown.

[0007] Figure 1B Shows Figure 1A A plan view of the photonic device in area B.

[0008] Figure 2A A cross-sectional view of a photonic device according to some embodiments is shown.

[0009] Figure 2B Shows Figure 2A Plan view of the photonic device in area B.

[0010] Figures 3 to 14B Cross-sectional and plan views of a photonic device fabricated according to some embodiments are shown.

[0011] FIG. 15A to FIG. 15B Shows Figures 3 to 14B Cross-sectional and plan views of process variants.

[0012] Fig.16 A flow chart is provided illustrating a method of forming a photonic device according to some embodiments. DETAILED DESCRIPTION

[0013] The present disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, the following description in which a first feature is formed on a second feature or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than representing the relationship between the various embodiments and / or configurations discussed.

[0014] Additionally, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and the like may be used herein to describe the relationship of one device or feature illustrated in the figures to another (other) device or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0015] Edge couplers can be used to couple a waveguide of a photonic integrated circuit to an optical transmitter or optical receiver, such as an optical fiber or laser that has a larger mode size than the waveguide. To reduce coupling losses, the width of the edge coupler can be narrowed from the mode size of the optical transmitter or optical receiver to the mode size of the waveguide. However, due to the thickness difference between the waveguide and the optical transmitter or optical receiver and the misalignment between the edge coupler and the optical transmitter or optical receiver, the coupling losses may still be significant.

[0016] Certain aspects of the present disclosure relate to an edge coupler having a gradually changing thickness from a narrow end to a wide end. The narrow end is coupled to a waveguide in a photonic integrated circuit. The wide end is coupled to an optical transmitter or an optical receiver. The upper surface of the edge coupler can be planar. In some embodiments, the top of the edge coupler is coplanar with the top of the waveguide. In some embodiments, the waveguide is disposed on an oxide layer and the edge coupler enters the oxide layer by gradually thickening downward. In some embodiments, the oxide layer is a buried oxide layer of a box substrate (BOX substrate) in which the photonic integrated circuit is formed.

[0017] In some embodiments, a pedestal is provided that solves the problem of aligning an optical transmitter or optical receiver with an edge coupler. In some embodiments, the pedestal is formed in the oxide layer, and the pedestal is approximately at the same height as the bottom of the edge coupler, so that an optical transmitter or optical receiver (such as a laser diode) mounted on the pedestal will be vertically aligned with the edge coupler. In some embodiments, the pedestal is formed in the substrate below the oxide layer, so that the core of the optical fiber mounted on the pedestal will be vertically aligned with the edge coupler. In some embodiments, the pedestal is in a cavity to facilitate horizontal alignment between the optical transmitter or optical receiver and the edge coupler.

[0018] Some aspects of the present disclosure relate to a process for forming an edge coupler having a thickness that gradually changes from a narrow end to a wide end. The process can be applied to a box substrate. The box substrate includes an oxide layer between a carrier substrate and a top layer of optical material. The process includes etching a trench in the top layer and the oxide layer. The trench has a narrow end and a wide end. At the narrow end, the trench is shallower and has a depth approximately equal to the thickness of the top layer. At the wide end, the trench is deeper. In a first region between the narrow end and the wide end, the depth of the trench gradually changes from a depth at the narrow end to a depth at the wide end. The edge coupler is formed by backfilling the trench with optical material. In some embodiments, the trench is filled with the same material as the top layer. A photonic circuit can be formed in the top layer including a waveguide coupled to the narrow end of the edge coupler.

[0019] In some embodiments, the trench filled to form the edge coupler extends into a second region where the base is subsequently formed. The trench may have a constant depth in the second region. The optical material filling the trench extends into the second region. Etching to form the top of the base is done by etching through the optical material in the second region. The transition from the optical material to the oxide layer below the optical material can be used to determine the endpoint of the etching process. If the etching stops at the transition point, the top of the base will align with the bottom of the edge coupler. In some embodiments, further etching is used to lower the base to the correct height. When the optical transmitter or optical receiver is subsequently mounted on the base, it will automatically align vertically with the edge coupler.

[0020] Figure 1A A cross-sectional view of a photonic device 100 is shown in accordance with some embodiments. Figure 1B Shows Figure 1A 1. A plan view of a photonic device 100 in region B of FIG. The photonic device 100 includes an edge coupler 129 having a narrow end 127 and a wide end 137. The narrow end 127 is coupled to a waveguide 125 in a photonic integrated circuit (PIC) 123. The wide end 137 is aligned with a laser diode 139 mounted on a base 145.

[0021] In addition to the waveguide 125, the photonic integrated circuit 123 may also include other photonic circuit components such as a light detector 113, a modulator 121, etc., all of which are disposed on the oxide layer 107. The edge coupler 129 is in and on the oxide layer 107, and a portion of the oxide layer 107 provides a base 145. The metal plug 143 may bond the laser diode to the base 145. In some embodiments, the metal plug 143 extends into the processing substrate 109 to provide an electrical terminal for the laser diode 139. A second electrical terminal (not shown) may be attached to the top of the laser diode 139.

[0022] In the region 128 between the narrow end 127 and the wide end 137, the width of the edge coupler 129 gradually changes from a first width W1 to a second width W2. In some embodiments, the first width W1 is in a range of about 100 nm to about 2000 nm. In some embodiments, the first width W1 is in a range of about 250 nm to about 1000 nm. In some embodiments, the second width W2 is in a range of about 1 μm to about 20 μm. In some embodiments, the second width W2 is in a range of about 2 μm to about 10 μm. In some embodiments, the second width W2 is about 3 to about 30 times greater than the first width W1. In certain embodiments, the second width W2 is about 5 to about 10 times greater than the first width W1.

[0023] The thickness of the edge coupler 129 changes gradually with the width. The thickness changes gradually from a first thickness T1 to a second thickness T2. In some embodiments, the first thickness T1 is in a range of about 50 nm to about 1000 nm. In some embodiments, the first thickness T1 is in a range of about 100 nm to about 600 nm. In some embodiments, the second thickness T2 is in a range of about 500 nm to about 10 μm. In some embodiments, the second thickness T2 is in a range of about 1 μm to about 5 μm. In some embodiments, the second thickness T2 is about 3 to about 30 times greater than the first thickness T1. In some embodiments, the second thickness T2 is about 5 to about 10 times greater than the first thickness T1.

[0024] In some embodiments, the top 126 of the edge coupler 129 is planar. The top 126 is vertically aligned with the top 124 of the waveguide 125. The edge coupler 129 gradually changes thickness by descending into the oxide layer 107. In some embodiments, the angle of the tilt angle θ is in the range of about 5 degrees to about 30 degrees. In some embodiments, the angle of the tilt angle θ is in the range of about 2 degrees to about 15 degrees.

[0025] Metal interconnects 103 including wires 117 and vias 119 surrounded by an interlevel dielectric 133 may be disposed above and coupled to the photonic integrated circuit 123. The metal interconnects 103 may couple the photonic integrated circuit 123 to an electronic integrated circuit (not shown) or an external device. The electronic integrated circuit may be located elsewhere on the processing substrate 109 or on a different substrate that is also part of the photonic device 100. One or more different substrates or other devices may be attached below or above the processing substrate 109. Substrates and devices below the processing substrate 109 may be coupled to the metal interconnects 103 through substrate vias 111 and the like. Substrates and devices above the processing substrate 109 may be coupled to the metal interconnects 103 through contact pads 115 and the like.

[0026] The pedestal 145 has a height such that the laser diode 139 is mounted on the pedestal 145 with the laser diode 139 aligned vertically with the wide end 137 of the edge coupler 129. In some embodiments, the pedestal 145 is closer in height to the bottom 131 of the edge coupler 129 than to the top 146 of the processing substrate 109. In some embodiments, the difference in height between the pedestal 145 and the bottom 131 of the edge coupler 129 is no more than about the thickness of the waveguide 125. In some embodiments, the difference in height is no more than about 100 nm. In some embodiments, the pedestal 145 is at about the same height as the bottom 131 of the edge coupler 129.

[0027] The base 145 is at the bottom of the base cavity 135. The base cavity 135 can have a width W3 that is limited to help achieve horizontal alignment between the laser diode 139 or other such device and the edge coupler 129. In some embodiments, the width W3 is from about 1 to about 10 times the width W2 of the wide end 137. In some embodiments, the width W3 is from about 2 to about 5 times the width W2.

[0028] Figure 2A A cross-sectional view of a photonic device 200 according to some other embodiments is shown. Figure 2B The photonic device 200 is shown in Figure 2A The photonic device 200 has many Figure 1A to Figure 1B The same components as the photonic device 100 are formed in the oxide layer 107 except that the base 145 (see Figure 1A ), the photonic device has a pedestal 245 that is lower and formed in the processing substrate 109. The pedestal 245 is in a pedestal cavity 235 having a width W3 that is only slightly larger than the diameter of the optical fiber 239, so that the pedestal cavity 235 promotes horizontal alignment between the optical fiber 239 and the edge coupler 129. The height of the pedestal 245 can be such that when the optical fiber 239 is placed on the pedestal 245, the core 241 of the optical fiber 239 is at the same height as the edge coupler 129.

[0029] Figures 3 to 14B 2 is a cross-sectional view and a plan view illustrating a method of forming a photonic device of the present disclosure according to the present disclosure. Figures 3 to 14B With reference to various embodiments of the invention, it should be understood that Figures 3 to 14B The structure shown in is not limited to the method, but can be independent of the method. Figures 3 to 14B A series of steps are described. The order of these steps may be changed in other embodiments. Figures 3 to 14B A particular set of steps is illustrated and described, but some may be omitted in other embodiments. In addition, steps not shown and / or described may be included in other embodiments. Figures 3 to 14B The method explains Figure 1A and Figure 1B The photonic device 100 is formed, but the method can be used to form other photonic devices.

[0030] like Figure 3As shown in the cross-sectional view 300 of , the method can start by providing a box substrate 303. The box substrate 303 includes a processing substrate 109, an oxide layer 107 and a top layer 301. The processing substrate 109 can be a material such as glass, ceramic, sapphire or a semiconductor substrate. The semiconductor can be silicon (Si), a III-V semiconductor or some other binary semiconductor (such as GaAs), a ternary semiconductor (such as AlGaAs), a high-order semiconductor, etc. The semiconductor can be doped or undoped. In some embodiments, the processing substrate 109 is conductive.

[0031] The oxide layer 107 may be, for example, silicon dioxide (SiO2) or the like. The oxide layer 107 may be used as a cladding layer for the optical device formed in the top layer 301. Therefore, the oxide layer 107 may be referred to as a cladding layer. In some embodiments, the oxide layer 107 has a thickness in a range of about 0.5 μm to about 4 μm.

[0032] The top layer 301 includes an optical material such as silicon (Si) or silicon nitride (Si3N4). The top layer 301 has a higher refractive index than the oxide layer 107. In some embodiments, the top layer 301 is silicon. The silicon can be doped or undoped. In some embodiments, the top layer 301 has a thickness in a range from about 100 nm to about 1.5 μm.

[0033] like Figure 4A Sectional view 400 and Figure 4B As shown in the plan view 420 of FIG. 4 , the process can continue to form a hard mask 401 above the top layer 301. The hard mask 401 has a pattern of openings 421. The openings 421 widen from a first width W1 to a second width W2 (compare FIG. Figure 1B ). The hard mask 401 includes silicon nitride (Si3N4), silicon carbide (SiC), silicon oxynitride (SiON), aluminum nitride (AlN), etc., or any other suitable material. The hard mask 401 can be patterned by photolithography, electron beam lithography, etc., or any other suitable process.

[0034] like Figure 5A Sectional view 500 and Figure 5B As shown in the plan view 520 of FIG. 5 , the process continues by etching to form trenches 501 in the top layer 301 and the oxide layer 107. In the first region 523, the trenches 501 have a depth D1 approximately equal to the thickness of the top layer 301. In the second region 521, the trenches 501 have a constant depth D2 approximately equal to the thickness T2 of the wide end 137 of the waveguide 125 (see FIG. Figure 1A). In the region 128 between the first region 523 and the second region 521, the depth of the trench 501 gradually changes from the depth D1 to the depth D2. In the region 128, the width of the trench 501 gradually changes from the width W1 to the width W2 as the depth gradually changes.

[0035] The trench 501 may be formed by one or more etching processes. The process may include dry etching, wet etching, or a combination of the two. In some embodiments, at least one of the processes is of a mass-transport rate limited type, thereby providing an etching rate that varies with the width of the trench 501. For example, the etching process may be plasma etching, and the conditions selected are to provide a high sensitivity of the etching rate to the trench width. In this way, the change in the depth of the trench 501 will naturally change gradually with the change in the width of the trench 501. It should be understood that the width and depth of the trench 501 change gradually, more gradually than shown in the figure. The gradual change in the width and depth of the trench 501 is conducive to achieving such process control.

[0036] like Figure 6 As shown in the cross-sectional view 600 of FIG. 5 , an optical material 601 can be deposited to fill the trench 501. The optical material is transparent and has a higher refractive index than the oxide layer 107. Examples of possible suitable optical materials include silicon nitride (Si3N4), silicon, and the like. In some embodiments, the optical material 601 is silicon. The silicon can be polycrystalline silicon or amorphous silicon. The silicon can be doped or undoped. In some embodiments, the optical material 601 has the same composition as the top layer 301. The optical material 601 can be deposited by any suitable process. Examples of possible suitable processes include chemical vapor deposition (CVD), physical vapor deposition (PVD), and the like.

[0037] like Figure 7 As shown in the cross-sectional view 700, Figure 6 A planarization process is performed on the structure shown in the cross-sectional view 600 of FIG. 5 to remove portions of the optical material 601 deposited outside the trench 501. The planarization process defines the edge coupler 129 from the optical material 601. In some embodiments, the planarization process removes the hard mask 401. The planarization process can also reduce the thickness of the top layer 301. The planarization process can be chemical mechanical polishing (CMP), etc., or any other suitable process.

[0038] like Figure 8As shown in the cross-sectional view 800 of FIG. 1 , the top layer 301 may be doped and patterned to form components of the photonic integrated circuit 123. These components may include, for example, the waveguide 125, the modulator 121, and the photodetector 113. The patterning and doping processes may include the formation of masks, dry etching, wet etching, ion implantation, and other similar processing steps. In some embodiments, the photonic circuit components are in a single layer above the oxide layer 107.

[0039] like Fig. 9 As shown in the cross-sectional view 900 of FIG. 1 , additional processes related to the formation of the photonic integrated circuit 123 may be performed. The additional processing includes depositing the cladding layer 105. The cladding layer 105 may be, for example, silicon dioxide (SiO2) or the like. The cladding layer 105 may be deposited by CVD, PVD, or the like, or any other suitable process. The additional processing may also include forming an opening in the cladding layer 105 and epitaxially growing a semiconductor material 901, which may be, for example, germanium (Ge), or the like, in the opening. The semiconductor material 901 constitutes a portion of the light detector 113.

[0040] like Fig.10 As shown in the cross-sectional view 1000 of , a first metallization layer 1001 can be formed above the cladding layer 105. The first metallization layer 1001 includes a wire 117 in an interlayer dielectric 133. The interlayer dielectric 133 can be silicon dioxide (SiO2), a low-k dielectric, etc., or any other suitable material. The interlayer dielectric 133 can be deposited by CVD, PVD, etc., or any other suitable process. The metal plug 1003 can couple the wire 117 to the electrical interface component of the photonic integrated circuit 123. The substrate through-hole 111 can also be formed at this processing stage. The metal plug 1003 and the wire 117 are formed of a conductive material such as a metal. The metal can be copper (Cu), silver (Si), gold (Au), tungsten (W), cobalt (Co), aluminum (Al), etc., their alloys, or any other suitable metal. The conductive material can be deposited by CVD, PVD, electroplating, electroless plating, etc., or any other suitable process. The process can be a damascene process, a dual damascene process, etc. The through-substrate via 111 is also formed by etching an opening (not shown) and filling the opening with a conductive material. The conductive material may be polysilicon, metal, etc. or any other suitable material and may be deposited by CVD, PVD, electroplating, electroless plating, etc. or any other suitable process.

[0041] like Fig.11 As shown in the cross-sectional view 1100 of FIG. 1 , additional metallization layers and interlayer dielectric 133 may be deposited to complete the formation of metal interconnect 103. Metal interconnect 103 may include more or fewer metallization layers than shown.

[0042] like Fig.12 As shown in the cross-sectional view 1200 of , a contact pad 115 can be formed on the metal interconnect 103, followed by the deposition of a passivation layer 101. The contact pad 115 can be used to couple other devices or chips to the processing substrate 109. Although the contact pad 115 is shown, other contact structures, such as bonding pads, can be used. These structures can be on the bottom of the processing substrate 109 and interface with the metal interconnect 103 through substrate through-holes 111, etc. Additional devices or chips may include photonic circuits, circuits, etc., or any other suitable device. The passivation layer 101 can be silicon nitride (Si3N4), etc., or any other suitable material, and can be deposited by CVD, PVD, etc., or any other suitable process. In some embodiments, the passivation layer 101 has a thickness in the range of about 1 μm to about 3 μm.

[0043] like Fig.13A The cross-sectional view 1300 and Fig. 13B As shown in the plan view 1320 of , a mask 1301 can be formed and used to etch a base cavity 135. Etching to form the base cavity 135 includes etching the passivation layer 101, the interlayer dielectric 133, the cladding layer 105 and an end portion of the edge coupler 129. The base cavity 135 passes through the edge coupler 129 at a position where the edge coupler 129 has a constant thickness in the second region 521. A portion 1303 of the edge coupler 129 with a constant thickness can be retained. The portion 1303 is between the wide end 137 and the region 128, where the thickness of the region 128 gradually changes. The etching process can be terminated after passing through the edge coupler 129 to expose the oxide layer 107 located underneath. The exposed portion of the oxide layer 107 provides a base 145.

[0044] The etching process may include wet etching, dry etching, or a combination thereof. In some embodiments, the composition of the edge coupler 129 is used to determine the endpoint of the etching process. As shown by way of example, byproducts of etching of the optical material that makes up the edge coupler 129 can be monitored during the etching process. A decrease in the concentration of the byproducts can be used to mark the endpoint. In some embodiments, the final stage of the etching process includes etching that selectively removes the optical material of the edge coupler 129 at a much higher rate than the material of the oxide layer 107. Trench 501 (see FIG. 5 ) Figure 5B ) can be widened to the size of the pedestal cavity 135 to facilitate this process. After etching, the mask 1301 can be stripped off.

[0045] like Fig.14A Sectional view 1400 and Fig. 14BAs shown in the plan view 1420 of FIG. 1 , a mask 1401 can be formed and used to etch trenches 1403 in the base 145. The trenches 1403 extend into the processing substrate 109. The etching process can be plasma etching, etc., or any other suitable process. After etching, the mask 1401 is stripped.

[0046] The trench 1403 may be filled and a laser diode 139 or other photonic device may be placed in the base cavity 135 to form a photonic device, e.g. Figure 1A The cross-sectional view and Figure 1B 14. The photonic device 100 is shown in a plan view of FIG. 14. In some embodiments, the material filling the trenches 1403 is a metal or some other conductive material, whereby the metal plug 143 formed by filling the trenches 1403 can provide an electrical connection between the laser diode 139 and the substrate 109. In certain embodiments, the material filling the trenches 1403 bonds the laser diode 139 or other such device to the base 145. For example, the laser diode 139 can be bonded to the base 145 by under bump metallization laser bonding. In such a case, the material filling the trenches 1403 can be carried by the laser diode 139 or other such photonic device placed on the base 145 in the base cavity 135.

[0047] Fig.15A Sectional view 1500 and Fig. 15B The floor plan of 1520 illustrates Figures 3 to 14B A variation of the process can be used to form Figure 2A and Figure 2B The photonic device 200. Fig.15A and Fig. 15B As shown, the main difference is the etching of the base cavity 235. The base cavity 235 is deeper than the base cavity 135 (see Fig.14A ). The base cavity 235 extends into the processing substrate 109 so that the base 245 is formed outside the processing substrate 109. Optical fibers or other photonic devices can be placed in the cavity on the base 245 to form Figure 2A and Figure 2B The photonic device 200 or other such device.

[0048] Fig.16 A flow chart of a process 1600 is presented that can be used to form a photonic device according to the present disclosure. Fig.16The process 1600 is illustrated and described herein as a series of steps or events, but it should be understood that the illustrated order of such steps or events should not be interpreted as having a limiting meaning. For example, some steps may appear in a different order and / or occur simultaneously with other steps or events other than those shown and / or described herein. In addition, not all illustrated steps of one or more aspects or embodiments described herein need to be implemented, and one or more steps described herein may be implemented in one or more separate steps and / or stages.

[0049] Process 1600 may begin with step 1601, providing a box substrate. The box substrate includes a handle substrate, an oxide layer, and a top layer. The top layer has a thickness and a material suitable for waveguides and other photonic devices. Figure 3 An example of this type of substrate is illustrated in cross-sectional view 300 .

[0050] Step 1603 is to etch a trench having an edge coupler shape. The trench may be formed in a hard mask formed on the box substrate. Figure 4A Sectional view 400 and Figure 4B A plan view 420 of is provided as an example. Optionally, the trench extends into the top layer. The trench of the edge coupler shape has a gradually changing width. The width gradually changes from a narrow end having the width of the waveguide to a wide end having a larger width, which corresponds to the size of an external device such as a laser diode or an optical fiber.

[0051] Step 1605 is an etch that extends the trench into the oxide layer with a gradual change in depth from a smaller depth at the narrow end to a larger depth at the wide end. Figure 5A Sectional view 500 and Figure 5B 520 is taken as an example. The smaller depth can only extend down to the top of the oxide layer. In some embodiments, the depth variation spans a range of about 50% to about 100% of the width variation. The depth can vary gradually over the length of the trench, and the width can also vary gradually over the length. In some embodiments, the process that gradually varies the trench depth has an etch rate that varies relative to the trench width.

[0052] Step 1607 fills the trench with optical material. The filling process may include optical material deposition and planarization to remove optical material deposited outside the trench. The optical material filling the trench provides an edge coupler. Figure 6 and Figure 7 Take the cross-sectional view 600 and the cross-sectional view 700 as examples.

[0053] Step 1609 forms a photonic circuit. The photonic circuit is formed in part by patterning the top layer. The patterned top layer forms a waveguide coupled to the narrow end of the edge coupler. In some embodiments, forming the photonic circuit includes doping some portion of the top layer. In some embodiments, forming the photonic circuit includes epitaxially growing a semiconductor on the top layer. Figure 8 and Fig. 9 The cross-sectional view 800 and the cross-sectional view 900 are provided as examples.

[0054] Step 1611 is an optional step of forming metal interconnects on the photonic circuit. Coupling the photonic circuit to the circuit through metal interconnects can increase functionality. For this purpose, bonding pads, substrate through-holes, etc. can also be formed. Figures 10 to 12 Cross-sectional views 1000 to 1200 are provided as examples.

[0055] Step 1613 is etching to form a pedestal. In some embodiments, the pedestal is at or below the height of the bottom of the edge coupler. In some embodiments, the pedestal is formed in the oxide layer and has an upper surface at a height near the bottom of the edge coupler. Fig.13A Sectional view 1300 and Fig. 13B 1320 is provided as an example. In some embodiments, the pedestal is lower and provided by the processing substrate. Fig.15A Sectional view 1500 and Fig. 15B The floor plan 1520 is provided as an example.

[0056] Step 1615 is to install an optical transmitter or an optical receiver on the base. In some embodiments, the device is an optical transmitter, such as a laser diode, an optical fiber, etc. Figures 1A to 1B Photonic devices 100 and Figures 2A to 2B The provided photonic device 200 is provided as an example structure.

[0057] In an embodiment of the present disclosure, a photonic device including a photonic integrated circuit and an edge coupler is provided. The edge coupler has a narrow end and a wide end. The narrow end is coupled to a waveguide in the photonic integrated circuit. The edge coupler has a thickness that gradually changes in a first region between the wide end and the narrow end. In some embodiments, the upper surface of the edge coupler is planar. In some embodiments, the width gradually changes with the thickness. In some embodiments, the photonic device includes an oxide layer, the waveguide is directly above the oxide layer, and the edge coupler gradually changes thickness into the oxide layer. In some embodiments, an optical transmitter or an optical receiver is mounted to a base formed by the oxide layer. In some embodiments, the base has an upper surface that is vertically aligned with the bottom of the edge coupler within a distance less than the thickness of the waveguide. In some embodiments, the edge coupler has a constant thickness in a second region, wherein the second region extends between the first region and the wide end. In some embodiments, the base is composed of a substrate below the oxide layer.

[0058] In an embodiment of the present disclosure, a photonic device is provided, comprising: an oxide layer; a photonic integrated circuit comprising a waveguide disposed on the oxide layer; and an optical transmitter or an optical receiver mounted on a base. The top of the base is lower than the bottom of the waveguide. An edge coupler is disposed on the oxide layer, gradually changes thickness downward into the oxide layer, and couples the optical transmitter or the optical receiver to the waveguide. In some embodiments, the top of the base is vertically aligned with the bottom of the edge coupler within a distance less than the thickness of the waveguide. In some embodiments, the oxide layer is between a substrate and the photonic integrated circuit, and the base is provided by the substrate. In some other embodiments, the base is provided by the oxide layer. In some embodiments, the top of the edge coupler is vertically aligned with the top of the waveguide.

[0059] In an embodiment of the present disclosure, a method for manufacturing a photonic device is provided. The method includes etching a trench in a top layer of a box substrate and a buried oxide layer. The trench includes a first region and a second region, wherein the trench has a gradually changing depth, and wherein the depth of the trench in the second region is greater than or equal to the maximum depth of the gradually changing depths. The trench is filled with an optical material having a refractive index greater than that of the buried oxide layer. A photonic integrated circuit is formed on the top layer, and a base is formed in the second region. An optical transmitter or an optical receiver is mounted on the base. A portion of the optical material filling the trench forms an edge coupler between the optical transmitter or the optical receiver and the photonic integrated circuit. In some embodiments, the top of the base is closer in height to the bottom of the edge coupler than to the processing substrate. In certain embodiments, a metal interconnect is formed above the photonic integrated circuit, and forming the base in the second region includes etching an interlayer dielectric passing through the metal interconnect. In certain embodiments, forming the base includes a first etching process for etching the optical material. In certain embodiments, the first etching process has a higher etching rate for the optical material than for the buried oxide layer. In some embodiments, the process includes a second etching process that forms a trench in the base. In some embodiments, a mask is formed over the top layer, wherein the mask has an opening of a gradually varying width. In these embodiments, etching trenches in the top layer and the buried oxide layer includes an etching process in which the etching rate depends on the width of the trench.

[0060] The features of several embodiments are summarized above so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications to them without departing from the spirit and scope of the present disclosure.

Claims

1. A photonic device, characterized in that: include: Photonic integrated circuits, including waveguides; and an edge coupler having a narrow end, a wide end, a narrow end thickness, and a wide end thickness; wherein the edge coupler is coupled to the waveguide at the narrow end; The edge coupler has a width that narrows between the wide end to the narrow end; and The edge coupler has a thickness that gradually changes from a thickness at the wide end to a thickness at the narrow end in a first region between the wide end and the narrow end.

2. The photonic device according to claim 1, characterized in that: The upper surface of the edge coupler is planar.

3. The photonic device according to claim 1, characterized in that: The width gradually changes with the thickness.

4. The photonic device according to claim 1, characterized in that: Also included is an oxide layer, wherein the waveguide is directly above the oxide layer and the edge coupler tapers in thickness into the oxide layer.

5. The photonic device according to claim 4, characterized in that: Also included is an optical transmitter or an optical receiver mounted to a base formed by the oxide layer.

6. The photonic device according to claim 5, characterized in that: The base has an upper surface vertically aligned with a bottom of the edge coupler within a distance less than a thickness of the waveguide.

7. A photonic device, characterized in that: include: Oxide layer; a photonic integrated circuit comprising a waveguide disposed on the oxide layer; an optical transmitter or an optical receiver mounted on a base, wherein a top of the base is lower than a bottom of the waveguide; and An edge coupler is disposed on the oxide layer and couples the optical transmitter or the optical receiver to the waveguide, wherein the edge coupler gradually changes thickness downward into the oxide layer.

8. The photonic device according to claim 7, characterized in that: The top of the pedestal is vertically aligned with the bottom of the edge coupler within a distance less than the thickness of the waveguide.

9. The photonic device according to claim 7, characterized in that: A substrate is also included, wherein the oxide layer is interposed between the substrate and the photonic integrated circuit, and the base is provided by the substrate.

10. The photonic device according to claim 7, characterized in that: The top of the edge coupler is vertically aligned with the top of the waveguide.

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