Integrated chip

Abstract

Various embodiments of the utility model aim at an integrated chip comprising a resistor structure arranged on a semiconductor substrate. A dielectric structure is disposed over the semiconductor substrate. The resistive structure is disposed within the dielectric structure. The resistive structure includes a thin film resistive (TFR) layer and a first capping structure disposed on the thin film resistive layer. The first cavity is disposed within the dielectric structure and adjoins a first sidewall of the first cover structure.

Description

Technical Field

[0001] The embodiment of the utility model relates to an integrated chip. Background Art

[0002] Modern integrated chips use a wide range of components to implement different functions. Generally speaking, integrated chips include active components and passive components. Active components include transistors (e.g., metal oxide semiconductor field effect transistors (MOSFETs)), while passive components include inductors, capacitors, and resistors. Resistors are widely used in many applications such as resistor-capacitor (RC) circuits, power drivers, power amplifiers, radio frequency (RF) applications, etc. Utility Model Content

[0003] In some embodiments of the present invention, the integrated chip includes: a semiconductor substrate; a dielectric structure disposed above the semiconductor substrate; a resistor structure disposed within the dielectric structure, wherein the resistor structure includes a thin film resistor (TFR) layer and a first covering structure disposed on the thin film resistor layer; and a first hole disposed within the dielectric structure and adjacent to a first side wall of the first covering structure.

[0004] In other embodiments of the present invention, the integrated chip includes: a semiconductor substrate; a dielectric structure arranged above the semiconductor substrate; a resistor structure arranged in the dielectric structure, wherein the resistor structure includes a thin film resistor (TFR) layer, a first covering structure and a second covering structure, wherein the first covering structure and the second covering structure are respectively arranged on opposite sides of the thin film resistor layer; a plurality of vias arranged in the dielectric structure and above the first covering structure and the second covering structure; a first air gap arranged in the dielectric structure and adjacent to the first covering structure; and a second air gap arranged in the dielectric structure and adjacent to the second covering structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The aspects of the present invention will be best understood when the following detailed description is read in conjunction with the accompanying drawings. It is worth noting that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0006] Figure 1 A cross-sectional view of some embodiments of an integrated chip is shown, the integrated chip including a plurality of holes in a cover structure laterally adjacent to a resistive structure;

[0007] Figure 2 Shows Figure 1 A top view of some embodiments of the integrated chip taken along line AA';

[0008] Figure 3A and Figure 3Bshowing cross-sectional views of some alternative embodiments of an integrated chip including a plurality of holes in a cover structure laterally adjacent to a resistive structure;

[0009] Figure 4A and Figure 4B Shows Figure 3A Cross-sectional views of some other embodiments of the integrated chip;

[0010] Figure 5A and Figure 5B Shows Figure 3A Cross-sectional views of some other embodiments of the integrated chip;

[0011] FIG. 6A to FIG. 6D Shows Figure 3A Cross-sectional views of some other embodiments of the integrated chip;

[0012] Fig. 7A Shows Figure 3A Cross-sectional views of some other embodiments of the integrated chip;

[0013] Figure 7B and Figure 7C Shows Fig. 7A Cross-sectional views of some other embodiments of regions of an integrated chip;

[0014] Fig. 8A Shows Figure 3A Cross-sectional views of some other embodiments of the integrated chip;

[0015] Figure 8B and Figure 8C Shows Fig. 8A Cross-sectional views of some other embodiments of regions of an integrated chip;

[0016] Fig.9A Shows Figure 3A Cross-sectional views of some other embodiments of the integrated chip;

[0017] Fig. 9B and Fig. 9C Shows Fig.9A Cross-sectional views of some other embodiments of regions of an integrated chip;

[0018] Fig.10 shows a cross-sectional view of some embodiments of an integrated chip having a resistor structure disposed within an interconnect structure;

[0019] Figures 11 to 16 A cross-sectional view of some embodiments of a method for forming an integrated chip including a resistive structure including a cavity adjacent to a capping structure is shown;

[0020] Figures 17 to 23Cross-sectional views of some other embodiments of methods for forming an integrated chip including a resistive structure including a cavity adjacent to a capping structure are shown;

[0021] Figure 24 to Figure 29 A cross-sectional view of some embodiments of a method for forming an integrated chip including a resistive structure including a cavity adjacent to a capping structure is shown;

[0022] Figure 30 to Figure 33 Cross-sectional views of some other embodiments of methods for forming an integrated chip including a resistive structure including a cavity adjacent to a capping structure are shown;

[0023] Fig.34 A flow chart illustrating some embodiments of a method for forming an integrated chip including a resistive structure including a cavity adjacent to a capping structure. DETAILED DESCRIPTION

[0024] The utility model provides many different embodiments or examples for realizing different features of the utility model. Specific examples of components and arrangements are described below to simplify the utility model. Of course, these are merely examples and are not restrictive. For example, forming a first feature above or on a second feature in the following description may include an embodiment in which the first and second features are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first and second features so that the first and second features may not be in direct contact. In addition, the utility model may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself specify the relationship between the various embodiments and / or configurations discussed.

[0025] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "beneath," "above," and the like may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. Spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientations depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0026] Some integrated chips have passive components disposed on / inside a substrate. For example, the passive components may include an inductor, a resistor, a capacitor, a diode, etc. One type of resistor used in an integrated chip is a thin film resistor (TFR). The thin film resistor includes a thin film resistor layer (e.g., a resistor layer) extending between two conductive covering structures. The dielectric structure is disposed above the thin film resistor layer and the two conductive covering structures and laterally surrounds the thin film resistor layer and the two conductive covering structures. Typically, the thin film resistor layer includes a first material (e.g., silicon chromium (SiCr)) having a first coefficient of thermal expansion (CTE), and the conductive covering structure includes a second material (e.g., titanium nitride, tantalum nitride, titanium tungsten, etc.), the second material having a second coefficient of thermal expansion different from the first coefficient of thermal expansion.

[0027] During the manufacture and / or operation of the thin film resistor, the thin film resistor layer and the conductive cover structure may be exposed to high temperatures. For example, one or more tests (e.g., high temperature working life (HTOL) test, high temperature storage life (HTSL) test, etc.) may be performed on the thin film resistor to determine the quality and / or reliability of the thin film resistor. During one or more tests, the thin film resistor is exposed to high temperatures (e.g., 175 degrees Celsius or higher). Due to the mismatch between the first thermal expansion coefficient and the second thermal expansion coefficient of the thin film resistor layer and the conductive cover structure, the thin film resistor layer may be exposed to high stress (e.g., high pressure stress, high tensile stress, etc.) at high temperatures. High stress may damage the thin film resistor layer, thereby reducing the safe operating area of ​​the thin film resistor (e.g., the voltage and / or current range that can be applied to the thin film resistor without damaging or reducing performance) and reducing the reliability of the thin film resistor. For example, high stress may cause a change in the sheet resistance across different regions of the thin film resistor layer (e.g., a region near the conductive cover structure of the thin film resistor layer). As a result, the overall performance of the thin film resistor is reduced and the thin film resistor may not meet the design specifications (e.g., due to changes in the sheet resistance of the entire thin film resistor layer).

[0028] Therefore, the utility model relates to an integrated chip having a resistor structure (e.g., a TFR structure), the resistor structure comprising a covering structure disposed on a thin film resistor layer and one or more holes adjacent to the covering structure. The thin film resistor layer and the covering structure are disposed in a dielectric structure. The thin film resistor layer has a first coefficient of thermal expansion (CTE), and the covering structure has a second CTE that is different from (e.g., greater than) the first CTE. One or more holes are disposed in the dielectric structure and are adjacent to corresponding side walls in the covering structure. One or more holes have a third CTE greater than the second CTE. Because the resistor structure includes one or more holes having a third CTE greater than the second CTE, the high stress caused by the covering structure on the thin film resistor layer at high temperatures (e.g., 175 degrees Celsius or higher) is reduced. In this way, the overall sheet resistance of the thin film resistor layer is more uniform, the reliability of the resistor structure is increased, and the safe operating area of ​​the resistor layer can be maintained or increased. Therefore, the overall performance of the resistor structure is improved.

[0029] Figure 1 A cross-sectional view 100 is shown in some embodiments of an integrated chip including a plurality of holes 110 laterally adjacent to a capping structure 108 of a resistive structure 104 .

[0030] The integrated chip includes a dielectric structure 112 disposed over a semiconductor substrate 102. A resistor structure 104 is disposed within the dielectric structure 112. A plurality of vias 114 are disposed within the dielectric structure 112 and disposed over the resistor structure 104. A plurality of conductive lines 116 are disposed within the dielectric structure 112 and disposed over the vias 114. The vias 114 and the conductive lines 116 are electrically coupled to the resistor structure 104.

[0031] The resistive structure 104 includes a thin film resistor (TFR) layer 106 and a pair of capping structures 108 disposed on opposite sides of the thin film resistor layer 106. In various embodiments, the capping structure 108 directly contacts the top surface of the thin film resistor layer 106. The thin film resistor layer 106 includes a first material (e.g., silicon chromium (SiCr)) having a first coefficient of thermal expansion (CTE). In addition, the capping structure 108 includes a second material (e.g., titanium nitride) having a second CTE different from (e.g., greater than) the first CTE. In some embodiments, the capping structure 108 is conductive and is configured to electrically couple the thin film resistor layer 106 to a plurality of vias 114. The resistive structure 104 is configured to resist (e.g., reduce) the flow of current between the capping structures 108. In some embodiments, the resistive structure 104 can be used, for example, in a resistor-capacitor (RC) circuit, a power driver, a power amplifier, an RF application, an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), other suitable electronic components, or any combination of the foregoing.

[0032] A plurality of holes 110 are disposed within the dielectric structure 112 and adjacent to the corresponding cover structures 108. In some embodiments, the hole 110 laterally covers a corresponding one of the cover structures 108. For example, the plurality of holes 110 include a first hole 110a, and the plurality of cover structures 108 include a first cover structure 108a. In various embodiments, the first hole 110a continuously covers the outer periphery of the first cover structure 108a. The hole 110 may be defined by one or more surfaces of the dielectric structure 112 and / or one or more surfaces of the cover structure 108. In yet other embodiments, the hole 110 is further defined by one or more surfaces of the thin film resistive layer 106. The hole 110 has a third CTE different from the first CTE and the second CTE. In some embodiments, the hole 110 includes air and may be configured as or referred to as an air gap. In various embodiments, the third CTE is greater than the first CTE and the second CTE.

[0033] Because the plurality of holes 110 are adjacent to the corresponding capping structures 108, stress on the thin film resistor layer 106 at high temperatures (e.g., caused by the capping structures 108) is reduced. For example, during the manufacture, operation and / or testing (e.g., high temperature operating life (HTOL) testing, high temperature storage life (HTSL) testing, etc.) of the resistor structure 104, the resistor structure 104 is exposed to high temperatures (e.g., 175 degrees Celsius or higher). Since the second CTE of the capping structure 108 is greater than the first CTE of the thin film resistor layer 106, the capping structure 108 may expand more than the thin film resistor layer 106 at high temperatures. Since the third CTE of the holes 110 is greater than the second CTE of the capping structure 108, the holes 110 may expand more than the capping structure 108 at high temperatures, thereby balancing and / or mitigating the expansion of the capping structure 108. This balances and / or mitigates the stress (e.g., compressive stress, tensile stress, etc.) applied to the thin film resistor layer 106 by the capping structure 108 to some extent, thereby mitigating the adverse effects on the thin film resistor layer 106. For example, the balanced and / or relieved stress on the thin film resistor layer 106 may increase the sheet resistance uniformity on the thin film resistor layer 106, increase the reliability of the thin film resistor layer 106, and / or increase the safe operating area of ​​the thin film resistor layer 106. Thus, the overall performance of the resistor structure 104 is increased.

[0034] Figure 2 Shown is a view taken along line A-A' Figure 1 The cross-sectional view 100 is a top view 200 of some embodiments.

[0035] like Figure 2 As shown, in some embodiments, the holes 110 laterally surround the corresponding cover structure 108. For example, the first hole 110a extends continuously around the outer periphery of the first cover structure 108a.

[0036] Figure 3A A cross-sectional view 300 a of some other embodiments of an integrated chip is shown that includes a plurality of holes 110 laterally adjacent to a capping structure 108 of a resistive structure 104 .

[0037] The integrated chip includes a dielectric structure 112 disposed above a semiconductor substrate 102. The semiconductor substrate 102 may be, for example, or include a semiconductor substrate material (e.g., silicon, silicon germanium, etc.), a silicon block substrate (e.g., silicon block), a semiconductor on insulator (SOI) substrate, one or more epitaxial layers, or other suitable substrates. In some embodiments, the dielectric structure 112 includes a first dielectric layer 302, a first etch stop layer 304, and a second dielectric layer 306. The first dielectric layer 302 and the second dielectric layer 306 may be, for example, or include silicon dioxide, a low-k dielectric material (e.g., undoped quartz glass (USG) and / or carbon-doped silicon dioxide), some other suitable dielectric, or any combination of the foregoing. In this context, a low-k dielectric material is a dielectric material having a dielectric constant less than 3.9. The first etch stop layer 304 may be, for example, or include silicon nitride, silicon carbide, etc. A plurality of vias 114 are disposed in the first dielectric layer 302. A plurality of conductive lines 116 are disposed in the second dielectric layer 306 and over the vias 114. The vias 114 and conductive lines 116 may be or include, for example, copper, aluminum, tungsten, titanium nitride, tantalum nitride, ruthenium, another conductive material, or any combination thereof.

[0038] The resistor structure 104 is disposed in the first dielectric layer 302. The resistor structure 104 includes a thin film resistor layer 106 and a pair of capping structures 108 disposed on opposite sides of the thin film resistor layer 106. The thin film resistor layer 106 includes a first material having a first CTE. In some embodiments, the first material is or includes silicon chromium, silicon chromium nickel, silicon chromium oxide, silicon chromium nitride, etc. In other embodiments, the first CTE can be about 3.5*10 -6 / K to 4.5*10 -6 / K, about 4*10 -6 In some other embodiments, the thin film resistor layer 106 has a thickness in the range of about 5 to 200 angstroms, less than about 200 angstroms, or some other value. The capping structure 108 includes a second material having a second CTE. In some embodiments, the second material is or includes titanium nitride, titanium tungsten, tantalum nitride, tungsten tantalum, etc. In other embodiments, the second CTE can be about 22.5*10 -6 / K to 24.5*10 -6 / K, about 23.4*10 -6In some embodiments, the first CTE is less than the second CTE. In various embodiments, the thickness of the thin film resistive layer 106 is less than the thickness of the capping structure 108.

[0039] A plurality of holes 110 are disposed in the first dielectric layer 302 and are respectively adjacent to corresponding capping structures 108. In some embodiments, the holes 110 are defined by one or more surfaces of the capping structure 108 (e.g., one or more sidewalls of the capping structure 108) and / or one or more surfaces of the first dielectric layer 302. The holes 110 have a third CTE that is different from the first CTE and the second CTE. For example, the third CTE is greater than the first CTE and the second CTE. In some embodiments, the holes include a third material (e.g., air) having the third CTE. In various embodiments, the third CTE may be about 1500*10 -6 / K to 3000*10 -6 / K, about 2000*10 -6 / K or some other suitable value. In other embodiments, the height 310 of the hole 110 is greater than the thickness of the thin film resistor layer 106 and / or greater than the thickness of the cover structure 108. In yet other embodiments, the height 310 of the hole 110 is less than the thickness of the cover structure 108 (not shown). In addition, the bottom of the hole 110 may be disposed above the top surface of the thin film resistor layer 106 and / or the top of the hole 110 may be disposed above the top surface of the cover structure 108. By virtue of the shape, the position relative to the cover structure 108 and / or the thin film resistor layer 106, and / or the third CTE of the hole 110, the stress (e.g., tensile stress, compressive stress) applied to the thin film resistor layer 106 at high temperature is reduced. This can increase the resistance uniformity of the entire thin film resistor layer 106, increase the reliability of the thin film resistor layer 106 (e.g., after exposure to high temperature, such as after HTOL testing, HTSL testing, etc.), and / or increase the safe operating area of ​​the thin film resistor layer 106 to some extent.

[0040] In addition, the first dielectric layer 302 includes a fourth material (eg, silicon dioxide) having a fourth CTE that is less than the second CTE and / or the third CTE. In other embodiments, the fourth CTE is greater than the first CTE. The fourth CTE may be, for example, about 6*10 -6 / K or some other suitable value.

[0041] Figure 3B Shows the corresponding Figure 3A300 b of some other embodiments of an integrated chip, wherein the cavity 110 is laterally spaced apart from the sidewalls of the cover structure 108 by a lateral distance 312. In such embodiments, the cavity 110 is completely defined by one or more surfaces of the first dielectric layer 302. In some embodiments, the lateral distance 312 is greater than zero. In other embodiments, the height of the cavity 110 is less than the thickness of the cover structure 108.

[0042] Figure 4A Shows the corresponding Figure 3A A cross-sectional view 400a of some other embodiments of an integrated chip of the present invention, wherein the cover structure 108 includes curved opposite sidewalls. In some embodiments, the hole 110 directly contacts and conforms to the shape of the curved opposite sidewalls of the cover structure 108. In addition, the height of the hole 110 can be equal to or less than the height of the cover structure 108. In various embodiments, the hole 110 can be defined by one or more surfaces of the first dielectric layer 302, one or more surfaces of the cover structure 108, and one or more surfaces of the thin film resistive layer 106.

[0043] Figure 4B Shows the corresponding Figure 4A A cross-sectional view 400 b of some other embodiments of the integrated chip, wherein the cover structures 108 respectively include inclined opposite side walls.

[0044] Figure 5A Shows the corresponding Figure 3A A cross-sectional view 500a of some other embodiments of an integrated chip of the present invention, wherein each of the holes 110 includes an inner hole 110i and an outer hole 110o. In addition, a hard mask layer 502 is disposed on the capping structure 108. In some embodiments, the inner hole 110i is disposed on a first side of the corresponding hole, and the outer hole 110o is disposed on a second side of the corresponding hole. In addition, the inner hole 110i and the outer hole 110o are respectively adjacent to corresponding curved sidewall segments of the corresponding hole. In various embodiments, the height of the outer hole 110o is greater than the height of the inner hole 110i. In other embodiments, the outer hole 110o is fluidically connected to the inner hole 110i.

[0045] Figure 5B To correspond to Figure 5A A cross-sectional view 500b of another embodiment of an integrated chip, wherein each of the covering structures 108 includes opposite sidewalls, and the opposite sidewalls have at least one slanted sidewall segment. In various embodiments, each of the covering structures 108 includes a first slanted sidewall segment having a first height and a second slanted sidewall segment having a second height greater than the first height.

[0046] Fig. 6A Shows the corresponding Figure 3A 600a of some other embodiments of an integrated chip of the present invention, wherein the sidewall spacer structure 602 is disposed along the opposite sidewalls of the capping structure 108. In various embodiments, the sidewall spacer structure 602 comprises silicon nitride, silicon carbide, etc. and / or has a thickness in the range of about 30 to 100 angstroms or some other suitable value. In still other embodiments, the cavity 110 may be disposed along the corresponding inner sidewall of each capping structure 108. In some embodiments, the inner sidewall of the capping structure 108 is curved. In various embodiments, the cavity 110 is defined by one or more surfaces of the first dielectric layer 302, one or more surfaces of the capping structure 108, one or more surfaces of the sidewall spacer structure 602, and / or one or more surfaces of the thin film resistive layer 106.

[0047] Figure 6B Shows the corresponding Fig. 6A FIG. 6 is a cross-sectional view 600 b of another embodiment of an integrated chip, wherein the inner sidewall of the cover structure 108 is inclined.

[0048] Figure 6C Shows the corresponding Fig. 6A A cross-sectional view 600c of another embodiment of an integrated chip, in which the sidewall spacer structure ( Fig. 6A sidewall spacer structure 602).

[0049] Fig.6D Shows the corresponding Figure 6B A cross-sectional view 600d of another embodiment of an integrated chip, in which the sidewall spacer structure ( Figure 6B sidewall spacer structure 602).

[0050] Fig. 7A Shows the corresponding Figure 3A In some other embodiments of the integrated chip, the capping structure 108 is spaced apart from the corresponding outer regions of the thin-film resistive layer 106 toward the center of the thin-film resistive layer 106. In such embodiments, the capping structure 108 is spaced apart laterally between the opposing outer sidewalls of the thin-film resistive layer 106.

[0051] Figure 7B Shows Fig. 7A The integrated chip region 702 (see, for example, Fig. 7A ) are cross-sectional views of some embodiments. Figure 7BAs shown, the hole 110 extends continuously from the curved sidewall of the capping structure 108 to the top surface of the thin-film resistive layer 106. In some embodiments, the first dielectric layer 302 includes a curved lower surface 302c defining at least a portion of the bottom of the hole 110, and the first dielectric layer 302 includes an inclined upper surface 302s defining at least a portion of the top of the hole 110. In various embodiments, the width of the hole 110 is greater than the height of the thin-film resistive layer 106.

[0052] Figure 7C Shows Fig. 7A The integrated chip region 702 (see, for example, Fig. 7A ) are cross-sectional views of other embodiments. Figure 7C As shown, in some embodiments, the capping structure 108 includes an inclined sidewall, and the hole 110 extends continuously from the inclined sidewall of the capping structure 108 to the top surface of the thin-film resistive layer 106 .

[0053] Fig. 8A Shows the corresponding Fig. 7A 800a of some other embodiments of an integrated chip, wherein the height of the hole 110 is less than the height of the cover structure 108. In various embodiments, the hole 110 is spaced apart from the cover structure 108 by the first dielectric layer 302. In other embodiments, the hole 110 is vertically spaced apart between the bottom surface of the cover structure 108 and the top surface of the cover structure 108.

[0054] Figure 8B Shows Fig. 8A The integrated chip region 802 (see, for example, Fig. 8A ) are cross-sectional views of some embodiments. Figure 8B As shown, the void 110 is adjacent to the curved sidewall of the cover structure 108. In various embodiments, the void 110 is laterally spaced apart from the curved sidewall of the cover structure 108 by a non-zero distance.

[0055] Figure 8C Shows Fig. 8A The integrated chip region 802 (see, for example, Fig. 8A ) are cross-sectional views of other embodiments. Figure 8C As shown, in some embodiments, the cover structure 108 includes a sloped sidewall adjacent to the cavity 110. In various embodiments, the cavity 110 is laterally spaced apart from the sloped sidewall of the cover structure 108 by a non-zero distance.

[0056] Fig.9A Shows the corresponding Fig. 7AIn some other embodiments of the integrated chip, the height of the hole 110 is less than the height of the cover structure 108. In other embodiments, the height of the hole 110 is less than the height of the thin film resistance layer 106. In addition, the hole 110 is separated from the cover structure 108 by the first dielectric layer 302.

[0057] Fig. 9B Shows Fig.9A The integrated chip region 902 (see, for example, Fig.9A ) are cross-sectional views of some embodiments. Fig. 9B As shown, the void 110 is adjacent to the curved sidewall of the cover structure 108 .

[0058] Fig. 9C Shows Fig.9A The integrated chip region 902 (see, for example, Fig.9A ) are cross-sectional views of other embodiments. Fig. 9C As shown, in some embodiments, the cover structure 108 includes a sloped sidewall adjacent to the cavity 110 .

[0059] Fig.10 A cross-sectional view 1000 of some embodiments of an integrated chip including a resistive structure 104 disposed within an interconnect structure 1003 is shown.

[0060] The interconnect structure 1003 is disposed above the semiconductor substrate 102. The semiconductor substrate 102 may be, for example, or include a semiconductor substrate material (e.g., silicon, silicon germanium, etc.), a silicon block substrate (e.g., silicon block), a semiconductor on insulator (SOI) substrate, one or more epitaxial layers, or other suitable substrates. The interconnect structure 1003 includes a plurality of dielectric layers (e.g., dielectric layer 1001, first dielectric layer 302, first etch stop layer 304, second dielectric layer 306, second etch stop layer 1012, third dielectric layer 1014), a plurality of vias 114, and a plurality of conductive lines 116. The plurality of vias 114 and the plurality of conductive lines 116 are disposed in the plurality of dielectric layers (e.g., dielectric layer 1001, first dielectric layer 302, first etch stop layer 304, second dielectric layer 306, second etch stop layer 1012, third dielectric layer 1014).

[0061] The semiconductor device 1002 is disposed in and / or on the semiconductor substrate 102. The semiconductor device 1002 may be, for example, a transistor and includes a source / drain region 1004, a gate dielectric layer 1006, a gate 1008, and a sidewall spacer structure 1010. The gate 1008 is disposed above the gate dielectric layer 1006, and the source / drain region 1004 is disposed in the semiconductor substrate 102 and is located on the opposite side of the gate 1008. Depending on the context, the source / drain region may refer to a source or a drain individually or collectively. The plurality of dielectric layers include a lower dielectric layer 1001, a first dielectric layer 302, a first etch stop layer 304, a second dielectric layer 306, a second etch stop layer 1012, and a third dielectric layer 1014. The lower dielectric layer 1001 is disposed above the semiconductor device 1002. In various embodiments, the resistor structure 104 is disposed on the lower dielectric layer 1001. The resistor structure 104 includes a thin film resistor layer 106 disposed along the top surface of the lower dielectric layer 1001 and a cover structure 108 disposed on opposite sides of the thin film resistor layer 106. In addition, the holes 110 are respectively adjacent to corresponding cover structures 108. By virtue of the CTE, size and / or position of the holes, the stress applied to the thin film resistor layer 106 by the cover structure 108 can be balanced and / or relieved. As a result, the overall performance of the resistor structure 104 is improved.

[0062] Figures 11 to 16 Cross-sectional views 1100 to 1600 of some embodiments of a method for forming an integrated chip include a resistive structure including a cavity adjacent to a cover structure. The integrated chip may correspond to Figure 4A Although the reference method describes Figures 11 to 16 1100 to 1600, but it should be understood that Figures 11 to 16 The structure shown in is not limited to the method, but can exist independently of the method. Figures 11 to 16 Described as a series of actions, it should be understood that these actions are not limited to the order in which the actions can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some drawings and / or described actions may be omitted in whole or in part.

[0063] like Fig.11As shown in the cross-sectional view 1100 of , a lower dielectric layer 1001, a thin film resistor (TFR) layer 106, a capping layer 1102, and a hard mask layer 502 are formed above the semiconductor substrate 102. The lower dielectric layer 1001 can be formed, for example, by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or some other suitable deposition or growth process. The lower dielectric layer 1001 can be or include, for example, silicon dioxide, a low-k dielectric material (e.g., undoped quartz glass (USG), carbon-doped silicon dioxide, etc.), some other suitable dielectrics, or any combination of the foregoing. The thin film resistor layer 106 can be formed, for example, by a CVD process, a PVD process, an ALD process, or some other suitable deposition or growth process. In some embodiments, thin film resistive layer 106 includes a first material having a first CTE (eg, silicon chromium, silicon chromium nickel, silicon chromium oxide, silicon chromium nitride, etc.) and / or is formed to a thickness in a range of approximately 5 to 200 angstroms, less than approximately 200 angstroms, or some other value.

[0064] The capping layer 1102 may be formed, for example, by a CVD process, a PVD process, an electroplating process, a sputtering process, or some other suitable deposition or growth process. In various embodiments, the capping layer 1102 includes a second material having a second CTE (e.g., titanium nitride, titanium tungsten, tantalum nitride, tantalum tungsten, etc.) and / or is formed to a thickness in the range of about 50 to 1000 angstroms or some other suitable value. In various embodiments, the second CTE is greater than the first CTE. The hard mask layer 502 may be formed, for example, by a CVD process, a PVD process, an ALD process, or some other suitable deposition or growth process. In some embodiments, the hard mask layer 502 is or includes silicon dioxide, silicon oxynitride, silicon nitride, another dielectric material, or any combination of the foregoing and / or is formed to a thickness in the range of about 100 to 500 angstroms or some other suitable value. In various embodiments, the thin film resistor layer 106, the capping layer 1102, and the hard mask layer 502 may be formed in separate processing chambers using a cluster tool.

[0065] like Fig.12 As shown in the cross-sectional view 1200 of FIG. 1 , the thin film resistor layer 106, the capping layer 1102, and the hard mask layer 502 are subjected to a first patterning process. In some embodiments, the first patterning process includes: forming a first upper masking layer 1202 (such as comprising photoresist, etc.) on the hard mask layer 502, and performing an etching process (such as a dry etching process, a wet etching process, etc.) on the thin film resistor layer 106, the capping layer 1102, and the hard mask layer 502 with the first upper masking layer 1202 in place. In some embodiments, the first upper masking layer 1202 is removed during or after the etching process (not shown).

[0066] like Fig.13As shown in the cross-sectional view 1300, the hard mask layer 502 and the capping layer ( Fig.12 The second patterning process is performed on the hard mask layer 502 (covering layer 1102) to define a plurality of covering structures 108 on the thin film resistor layer 106 and define the resistor structure 104. In some embodiments, the second patterning process includes: forming a second upper masking layer 1302 (such as comprising photoresist, etc.) on the hard mask layer 502 and performing a second patterning process on the hard mask layer 502 and the covering layer ( Fig.12 The second upper masking layer 1302 is subjected to an etching process (such as a dry etching process, a wet etching process, etc.) in some embodiments, the second upper masking layer 1302 is removed during or after the etching process (not shown).

[0067] like Fig.14 As shown in the cross-sectional view 1400 of FIG. 14 , an etching process is performed on the capping structure 108. In various embodiments, the etching process includes performing a wet etching process on the capping structure 108. In such embodiments, the etching process defines curved sidewalls (e.g., as in FIG. 14 ) in the capping structure 108. Figure 4A In some other embodiments, the etching process includes performing a plasma etching process with a voltage bias. In such embodiments, the etching process is performed so that the capping structure 108 includes a sloped sidewall (e.g., as shown in Figure 4B In various embodiments, the etching process may include performing a wet etching process and a plasma etching process. The hard mask layer 502 may be removed by a removal process after the etching process (not shown). During the etching process, the hard mask layer 502 has a first etching rate and the capping structure 108 has a second etching rate. In various embodiments, the second etching rate is greater than the first etching rate.

[0068] like Fig.15As shown in the cross-sectional view 1500 of FIG. 15 , a dielectric structure 112 is formed over the resistive structure 104 to seal and / or form a cavity 110 adjacent to the capping structure 108. The dielectric structure 112 includes a first dielectric layer 302, a second dielectric layer 306, and a first etch stop layer 304 disposed between the first dielectric layer 302 and the second dielectric layer 306. The cavity 110 is at least partially defined by one or more surfaces of the first dielectric layer 302. In various embodiments, the cavity 110 may be formed in the first dielectric layer 302 by selecting a suitable formation process. A suitable formation process for forming the first dielectric layer 302 having the cavity 110 may be a non-conformal deposition process, such as plasma enhanced chemical vapor deposition (PECVD). The non-conformal deposition process produces the cavity 110 in a recessed area such as around the sidewalls of the capping structure 108 (e.g., around the curved sidewalls and / or inclined sidewalls of the capping structure 108). Other suitable formation processes for the first dielectric layer 302 may include, for example, metal organic chemical vapor deposition (MOCVD), remote plasma chemical vapor deposition (RPCVD), high density plasma chemical vapor deposition (HDPCVD), electron cyclotron resonance (ECR) plasma enhanced chemical vapor deposition (ECRCVD), hot filament chemical vapor deposition (HWCVD), or other suitable growth or deposition processes. In other embodiments, the suitable formation process may include a CVD process with a suitable substrate bias to promote anisotropic deposition of the first dielectric layer 302, thereby controlling the size of the voids 110. In various embodiments, the voids 110 are formed in the first dielectric layer 302 due to the recessed area of ​​the capping structure 108 (e.g., near the sidewalls of the capping structure 108), the suitable formation process selected for the first dielectric layer 302, and / or the filling characteristics of the first dielectric layer 302.

[0069] In addition, the first etch stop layer 304 is formed on the first dielectric layer 302, for example, by a CVD process, a PVD process, an ALD process, or some other suitable growth or deposition process. The second dielectric layer 306 is formed on the first etch stop layer 304, for example, by a CVD process, a PVD process, an ALD process, or some other suitable growth or deposition process. The first dielectric layer 302 and the second dielectric layer 306 can be, for example, or include silicon dioxide, a low-k dielectric material (e.g., undoped quartz glass (USG) and / or carbon-doped silicon dioxide), some other suitable dielectric, or any combination of the foregoing. The first etch stop layer 304 can be, for example, or include silicon nitride, silicon carbide, etc.

[0070] like Fig.16As shown in the cross-sectional view 1600 in FIG. 1 , a plurality of vias 114 and a plurality of conductive lines 116 are formed above the resistor structure 104. In various embodiments, the process of forming the vias 114 and the conductive lines 116 includes: forming a masking layer (not shown) above the dielectric structure 112; performing an etching process (e.g., a dry etching process, a wet etching process, etc.) on the dielectric structure 112 to form a plurality of openings in the dielectric structure 112; depositing (e.g., by CVD, PVD, sputtering, electroplating, etc.) a conductive material (e.g., aluminum, copper, titanium nitride, tungsten, another conductive material, or any combination thereof) in the openings; and performing a planarization process (e.g., a chemical mechanical planarization (CMP) process) on the conductive material.

[0071] Figures 17 to 23 Cross-sectional views 1700 to 2300 illustrate some embodiments of a method for forming an integrated chip, the integrated chip including a resistive structure including a cavity adjacent to a cover structure. The integrated chip may correspond to, for example Figure 5A Although the reference method describes Figures 17 to 23 1700 to 2300, but it should be understood that Figures 17 to 23 The structure shown in is not limited to the method, but can be independent of the method. Figures 17 to 23 Described as a series of actions, it should be understood that these actions are not limited to the order in which the actions can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some drawings and / or described actions may be omitted in whole or in part.

[0072] like Fig.17 As shown in the cross-sectional view 1700 of FIG. 17 , the lower dielectric layer 1001, the thin film resistor layer 106, the capping layer 1102 and the hard mask layer 502 are formed on the semiconductor substrate 102. In addition, the thin film resistor layer 106, the capping layer 1102 and the hard mask layer 502 are subjected to a first patterning process. Fig.17 The structure can be, for example, Fig.11 and Fig.12 formed as shown and / or described in .

[0073] like Fig.18 As shown in the cross-sectional view 1800 of , the hard mask layer 502 is subjected to a second patterning process. In some embodiments, the second patterning process includes: forming a second upper masking layer 1302 (such as comprising photoresist, etc.) on the hard mask layer 502, and performing an etching process (such as a dry etching process, a wet etching process, etc.) on the hard mask layer 502 with the second upper masking layer 1302 in place. In various embodiments, the second upper masking layer 1302 is removed during or after the etching process (not shown).

[0074] like Fig.19 As shown in the cross-sectional view 1900 of FIG. 1 , a first etching process is performed on the cover layer 1102 to remove a portion of the middle region of the cover layer 1102, thereby defining an upper surface 1102us of the cover layer 1102. In some embodiments, the first etching process includes performing a plasma etching process, a reactive ion etching process, some other suitable etching process, or any combination of the foregoing. In other embodiments, the first etching process is performed on the cover layer 1102 using the second upper masking layer 1302. In yet other embodiments, the second upper masking layer 1302 is removed during or after the first etching process (not shown).

[0075] like Fig. 20 As shown in the cross-sectional view 2000 of FIG. 1 , a second etching process is performed on the capping layer 1102. In various embodiments, the second etching process includes performing a wet etching process on the capping layer 1102. In such an embodiment, the second etching process can define a curved sidewall (e.g., Figure 5A In other embodiments, the second etching process includes performing a plasma etching process, a plasma etching process with a voltage bias, or some other suitable dry etching process. In such embodiments, the second etching process can define a sloped sidewall in the capping layer 1102 (e.g., Figure 5B In some other embodiments, the second etching process includes performing a wet etching process and a plasma etching process.

[0076] like Fig.21 As shown in the cross-sectional view 2100, the cover layer ( Fig. 20 The third patterning process is performed on the capping layer 1102 of the hard mask layer 502 to define a plurality of capping structures 108 and a resistive structure 104. In some embodiments, the third patterning process includes: forming a third upper masking layer 2102 (for example, including photoresist, etc.) on the hard mask layer 502 and patterning the capping layer ( Fig. 20 The third upper masking layer 2102 is subjected to an etching process (eg, a dry etching process, a wet etching process, etc.) In various embodiments, the third upper masking layer 2102 is removed during or after the etching process (not shown).

[0077] like Fig. 22As shown in the cross-sectional view 2200 of , a dielectric structure 112 is formed over the resistive structure 104 to seal and / or form a cavity 110 adjacent to the capping structure 108. The dielectric structure 112 includes a first dielectric layer 302, a second dielectric layer 306, and a first etch stop layer 304 disposed between the first dielectric layer 302 and the second dielectric layer 306. The cavity 110 is at least partially defined by one or more surfaces of the first dielectric layer 302. In some embodiments, each of the cavities 110 includes an outer cavity 110o disposed on a first side of the corresponding capping structure 108 and an inner cavity 110i disposed on a second side of the corresponding capping structure 108. In other embodiments, the inner cavity 110i and the outer cavity 110o of each of the cavities 110 are fluidically connected to each other. In various embodiments, the cavity 110 can be formed in the first dielectric layer 302 by selecting a suitable formation process for the first dielectric layer 302. Suitable formation processes may include, for example, PECVD, MOCVD, RPCVD, HDPCVD, ECRCVD, HWCVD or other suitable growth or deposition processes. Fig.15 formed as shown and / or described in .

[0078] like Fig.23 As shown in the cross-sectional view 2300 of FIG. 23 , a plurality of vias 114 and a plurality of conductive lines 116 are formed above the resistor structure 104. In various embodiments, the process of forming the vias 114 and the conductive lines 116 includes: forming a masking layer (not shown) above the dielectric structure 112; performing an etching process (e.g., a dry etching process, a wet etching process, etc.) on the dielectric structure 112 to form a plurality of openings in the dielectric structure 112 and / or the hard mask layer 502; depositing (e.g., by CVD, PVD, sputtering, electroplating, etc.) a conductive material (e.g., aluminum, copper, titanium nitride, tungsten, another conductive material, or any combination thereof) in the openings; and performing a planarization process (e.g., a CMP process, etc.) on the conductive material.

[0079] Figure 24 to Figure 29 Cross-sectional views 2400 to 2900 of some embodiments of a method for forming an integrated chip include a resistive structure including a cavity adjacent to a cover structure. The integrated chip corresponds to, for example, Fig. 6A Although the reference method describes Figure 24 to Figure 29 2400 to 2900, but it should be understood that Figure 24 to Figure 29 The structure shown in is not limited to the method, but can be independent of the method. Figure 24 to Figure 29Described as a series of actions, it should be understood that these actions are not limited to the order in which the actions can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some drawings and / or described actions may be omitted in whole or in part.

[0080] like Fig.24 As shown in the cross-sectional view 2400 of FIG. 1 , the lower dielectric layer 1001, the thin film resistor layer 106, the capping layer 1102 and the hard mask layer 502 are formed over the semiconductor substrate 102. In addition, the thin film resistor layer 106, the capping layer 1102 and / or the hard mask layer 502 are subjected to one or more patterning processes. Fig.24 The structure can be, for example, Figures 17 to 19 formed as shown and / or described in .

[0081] like Fig.25 As shown in the cross-sectional view 2500 of FIG. 25, a sidewall spacer 2502 is formed over the hard mask layer 502, the cap layer 1102, and the lower dielectric layer 1001. In some embodiments, the sidewall spacer 2502 is formed over the hard mask layer 502, the cap layer 1102, and the lower dielectric layer 1001 by a CVD process, a PVD process, an ALD process, or some other suitable formation or growth process. The sidewall spacer 2502 can be or include, for example, silicon nitride, silicon carbide, silicon oxynitride, some other suitable dielectric material, or any combination of the foregoing. In various embodiments, the sidewall spacer 2502 is formed to a thickness in the range of about 30 to 100 angstroms or some other suitable value.

[0082] like Fig.26 As shown in the cross-sectional view 2600, the side wall spacer ( Fig.25 The first etching process is performed to define and / or form the sidewall spacer structure 602 along the sidewalls of the hard mask layer 502, the sidewalls of the cap layer 1102, and the sidewalls of the thin film resistor layer 106. In various embodiments, the first etching process is configured to remove the sidewall spacer layer ( 502 ) from horizontal surfaces such as the upper surface 1102 us of the cap layer 1102, the top surface of the hard mask layer 502, and / or the top surface of the lower dielectric layer 1001. Fig.25 In various embodiments, the first etching process includes performing a dry etching process, a plasma etching process, a blanket etching process, another suitable etching process, or any combination thereof.

[0083] like Fig. 27 As shown in the cross-sectional view 2700, the cover layer ( Fig.26The second etching process is performed on the capping layer 1102 to define and / or form the capping structure 108 above the thin film resistor layer 106. In some embodiments, the second etching process includes performing a plasma etching process, a reactive ion etching process, a wet etching process, some other suitable etching process, or any combination thereof. In other embodiments, the second etching process includes performing a wet etching process on the capping layer 1102, so that the second etching process can define at least one curved inner sidewall (e.g., as shown in FIG. 1 ) in each of the capping structures 108. Fig. 6A In some other embodiments, the second etching process includes performing a plasma etching process, a plasma etching process with a voltage bias, or some other suitable dry etching process, so that the second etching process can define at least one inclined sidewall in each of the capping structures 108 (e.g., as shown in Figure 6B In some embodiments, after the second etching process, a removal process is performed to remove the sidewall spacer structure 602 (not shown) (e.g., as shown in Figure 6C and / or Fig.6D ) as shown and / or described in .

[0084] like Fig.28 As shown in the cross-sectional view 2800 of , a dielectric structure 112 is formed above the resistive structure 104 to seal and / or form a hole 110 adjacent to the capping structure 108. The dielectric structure 112 includes a first dielectric layer 302, a second dielectric layer 306, and a first etch stop layer 304 disposed between the first dielectric layer 302 and the second dielectric layer 306. The hole 110 is at least partially defined by one or more surfaces of the first dielectric layer 302. In various embodiments, the hole 110 is formed in the first dielectric layer 302 by selecting a suitable formation process for the first dielectric layer 302. A suitable formation process may be, for example, or include PECVD, MOCVD, RPCVD, HDPCVD, ECRCVD, HWCVD, or other suitable growth or deposition processes. In yet other embodiments, the dielectric structure 112 and / or the hole 110 are as Fig.15 formed as shown and / or described in .

[0085] like Fig.29As shown in the cross-sectional view 2900 of FIG. 29 , a plurality of vias 114 and a plurality of conductive lines 116 are formed above the resistor structure 104. In various embodiments, the process of forming the vias 114 and the conductive lines 116 includes: forming a masking layer (not shown) above the dielectric structure 112; performing an etching process (e.g., a dry etching process, a wet etching process, etc.) on the dielectric structure 112 to form a plurality of openings in the dielectric structure 112 and / or the hard mask layer 502; depositing (e.g., by CVD, PVD, sputtering, electroplating, etc.) a conductive material (e.g., aluminum, copper, titanium nitride, tungsten, another conductive material, or any combination thereof) in the openings; and performing a planarization process (e.g., a CMP process, etc.) on the conductive material.

[0086] Figure 30 to Figure 33 Cross-sectional views 3000 to 3300 of some embodiments of a method for forming an integrated chip include a resistive structure including a cavity adjacent to a capping structure. The integrated chip corresponds to, for example, Fig. 7A Although the reference method describes Figure 30 to Figure 33 3000 to 3300 shown in FIG. 3000 , but it should be understood that Figure 30 to Figure 33 The structure shown in is not limited to the method, but can be independent of the method. Figure 30 to Figure 33 Described as a series of actions, it should be understood that these actions are not limited to the order in which the actions can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some drawings and / or described actions may be omitted in whole or in part.

[0087] like Fig.30 As shown in the cross-sectional view 3000 of FIG. 1 , the lower dielectric layer 1001, the thin film resistor layer 106, the capping structure 108, and the hard mask layer 502 are formed above the semiconductor substrate 102. In addition, one or more patterning processes are performed on the thin film resistor layer 106, the capping structure 108, and / or the hard mask layer 502, so as to define and / or form the resistor structure 104 above the semiconductor substrate 102. Fig.30 The structure can be, for example, Figures 11 to 13 formed as shown and / or described in .

[0088] like Fig.31As shown in the cross-sectional view 3100 of , an etching process is performed on the capping structure 108. In various embodiments, the etching process includes performing a wet etching process on the capping structure 108. In such an embodiment, the etching process defines a curved sidewall in the capping structure 108. In other embodiments, the etching process includes performing a plasma etching process with a voltage bias, some other suitable dry etching process, etc. In such an embodiment, the etching process is performed so that the capping structure 108 includes an inclined sidewall (not shown). In other embodiments, the size and / or shape of the sidewall of the capping structure 108 can be controlled and / or defined based on the etching time of the etching process, the concentration of the etchant used during the etching process (for example, the concentration of the wet etchant used during the etching process), the voltage bias value applied during the dry etching process, etc.

[0089] like Fig.32 As shown in the cross-sectional view 3200 of , a dielectric structure 112 is formed above the resistive structure 104 to seal and / or form a hole 110 adjacent to the capping structure 108. The dielectric structure 112 includes a first dielectric layer 302, a second dielectric layer 306, and a first etch stop layer 304 disposed between the first dielectric layer 302 and the second dielectric layer 306. The hole 110 is at least partially defined by one or more surfaces of the first dielectric layer 302. In various embodiments, the hole 110 is formed in the first dielectric layer 302 by selecting a suitable formation process for the first dielectric layer 302. A suitable formation process may be, for example, or include PECVD, MOCVD, RPCVD, HDPCVD, ECRCVD, HWCVD, ALD, some other suitable growth or deposition process, or any combination of the foregoing. In yet other embodiments, the dielectric structure 112 and / or the hole 110 is as Fig.15 formed as shown and / or described in .

[0090] In other embodiments, the size and / or shape of the voids 110 can be controlled by adjusting the formation process of the first dielectric layer 302. For example, the first dielectric layer 302 can be formed by a CVD process with a suitable substrate bias to set the size and / or shape of each void 110. In some embodiments, the first dielectric layer 302 can be formed by an ALD process and a CVD process to control the size of the voids 110. In various embodiments, the size of the voids 110 is at least partially determined or controlled by the shape of the sidewalls of the capping structure 108, wherein the shape of the sidewalls of the capping structure 108 can be adjusted. Fig.31 The etching process period is controlled by etching time, etchant solution concentration (eg, wet etchant concentration), appropriate voltage bias, etc.

[0091] like Fig.33As shown in the cross-sectional view 3300 of FIG. 3300 , a plurality of vias 114 and a plurality of conductive lines 116 are formed above the resistor structure 104. In various embodiments, the process of forming the vias 114 and the conductive lines 116 includes: forming a masking layer (not shown) above the dielectric structure 112; performing an etching process (e.g., a dry etching process, a wet etching process, etc.) on the dielectric structure 112 to form a plurality of openings in the dielectric structure 112 and / or the hard mask layer 502; depositing (e.g., by CVD, PVD, sputtering, electroplating, etc.) a conductive material (e.g., aluminum, copper, titanium nitride, tungsten, another conductive material, or any combination thereof) in the openings; and performing a planarization process (e.g., a CMP process, etc.) on the conductive material.

[0092] Fig.34 A flow chart of some embodiments of a method 3400 for forming an integrated chip is shown, the integrated chip including a resistive structure, the resistive structure including a hole adjacent to a covering structure. Although method 3400 is shown and / or described as a series of actions of an event, it should be understood that the method is not limited to the order or actions of the accompanying drawings. Therefore, in some embodiments, these actions may be performed in an order different from the order shown, and / or these actions may be performed simultaneously. In addition, in some embodiments, the actions or events shown may be subdivided into multiple actions or events, which may be performed at different times or simultaneously with other actions or sub-actions. In some embodiments, the actions or events of some drawings may be omitted, while other actions or events not shown may be included.

[0093] At act 3402, a lower dielectric layer is formed over a semiconductor substrate. Fig.11 Cross-sectional view 1100 corresponding to some embodiments of act 3402 is shown.

[0094] At activity 3404, a thin film resistor (TFR) layer, a capping layer, and a hard mask layer are formed over the lower dielectric layer. Fig.11 Cross-sectional view 1100 corresponding to some embodiments of act 3404 is shown.

[0095] At act 3406, the thin film resistor layer, the capping layer, and the hard mask layer are patterned. Fig.12 Cross-sectional view 1200 is shown corresponding to some embodiments of act 3406 .

[0096] At act 3408 , the hard mask layer and the capping layer are patterned to form a capping structure and a resistive structure, wherein the capping structure is disposed over the thin film resistive layer. Fig.13 Cross-sectional view 1300 is shown corresponding to some embodiments of act 3408 . Figures 18 to 21 Cross-sectional views 1800 - 2100 are shown corresponding to various embodiments of act 3408 . Figure 24 to Figure 27Cross-sectional views 2400 to 2700 are shown corresponding to other embodiments of action 3408 . Fig.30 Cross-sectional view 3000 corresponding to yet further embodiments of action 3408 is shown.

[0097] At act 3410, the capping structure is etched to remove an outer portion of the capping structure, thereby forming or defining sloped and / or curved sidewalls in the capping structure. Fig.14 Cross-sectional view 1400 corresponding to some embodiments of act 3410 is shown. Fig. 20 and Fig.21 Cross-sectional view 2000 and cross-sectional view 2100 corresponding to various embodiments of act 3410 are shown. Fig. 27 Cross-sectional view 2700 corresponding to further embodiments of act 3410 is shown. Fig.31 Cross-sectional view 3100 corresponding to yet further embodiments of action 3410 is shown.

[0098] At activity 3412, a dielectric structure is formed over and around the capping structure, thereby forming and / or sealing a cavity adjacent to the capping structure. Fig.15 Cross-sectional view 1500 is shown corresponding to some embodiments of act 3412 . Fig. 22 Cross-sectional view 2200 corresponding to various embodiments of act 3412 is shown. Fig.28 Cross-sectional view 2800 is shown corresponding to further embodiments of act 3412 . Fig.32 Cross-sectional view 3200 is shown corresponding to further embodiments of action 3412 .

[0099] At activity 3414, a plurality of vias and a plurality of conductive lines are formed in the dielectric structure and over the resistive structure. Fig.16 Cross-sectional view 1600 is shown corresponding to some embodiments of act 3414 . Fig.23 Cross-sectional view 2300 corresponding to various embodiments of act 3414 is shown. Fig.29 Cross-sectional view 2900 is shown corresponding to further embodiments of action 3414 . Fig.33 Cross-sectional view 3300 is shown corresponding to further embodiments of action 3414 .

[0100] Therefore, in some embodiments, the present invention is directed to a resistor structure including a thin film resistor (TFR) layer, a cover structure on the thin film resistor layer, and a cavity adjacent to the cover structure.

[0101] In some embodiments, the utility model provides an integrated chip, comprising: a semiconductor substrate; a dielectric structure disposed above the semiconductor substrate; a resistor structure disposed in the dielectric structure, wherein the resistor structure comprises a thin film resistor (TFR) layer and a first covering structure disposed on the thin film resistor layer; and a first hole disposed in the dielectric structure and adjacent to the first sidewall of the first covering structure. In some embodiments, the first thermal expansion coefficient of the thin film resistor layer is less than the second thermal expansion coefficient of the first covering structure. In some embodiments, the third thermal expansion coefficient of the first hole is greater than the second thermal expansion coefficient. In some embodiments, the first hole extends laterally beyond the upper surface of the thin film resistor layer. In some embodiments, the resistor structure further comprises: a second covering structure disposed on the thin film resistor layer and laterally spaced apart from the first covering structure, wherein the second hole is disposed in the dielectric structure and adjacent to the sidewall of the second covering structure. In some embodiments, the first sidewall comprises a first curved section, wherein the shape of the first hole conforms to the first curved section. In some embodiments, the first covering structure comprises a second sidewall opposite to the first sidewall, wherein the second sidewall comprises a second curved section, wherein the second hole is disposed in the dielectric structure and conforms to the second curved section, wherein the height of the first hole is greater than the height of the second hole. In some embodiments, the integrated chip further includes: a first hard mask layer disposed on a top surface of the first capping structure, wherein a top of the first hole is disposed below a top surface of the first hard mask layer.

[0102] In some embodiments, the utility model provides an integrated chip, comprising: a semiconductor substrate; a dielectric structure, arranged above the semiconductor substrate; a resistor structure, arranged in the dielectric structure, wherein the resistor structure comprises a thin film resistor (TFR) layer, a first covering structure and a second covering structure, wherein the first covering structure and the second covering structure are respectively arranged on opposite sides of the thin film resistor layer; a plurality of vias, arranged in the dielectric structure and arranged above the first covering structure and the second covering structure; a first air gap, arranged in the dielectric structure and adjacent to the first covering structure; and a second air gap, arranged in the dielectric structure and adjacent to the second covering structure. In some embodiments, the first covering structure and the second covering structure include a conductive material. In some embodiments, the first air gap laterally covers the outer periphery of the first covering structure. In some embodiments, the integrated chip further comprises: a first sidewall spacer structure, arranged along the sidewall of the first covering structure, wherein the first air gap is arranged between the lower surface of a section of the first sidewall spacer structure and the top surface of the thin film resistor layer. In some embodiments, the thermal expansion coefficients of the first covering structure and the second covering structure are different from the thermal expansion coefficient of the thin film resistor layer, and wherein the thermal expansion coefficients of the first air gap and the second air gap are greater than the thermal expansion coefficients of the first covering structure and the second covering structure. In some embodiments, the first air gap is laterally spaced a non-zero distance from adjacent sidewalls of the first capping structure, wherein the dielectric structure extends continuously laterally along the non-zero distance. In some embodiments, a bottom of the first air gap and a bottom of the second air gap are vertically above a top surface of the thin film resistive layer.

[0103] In some embodiments, the utility model provides a method for forming an integrated chip, comprising: depositing a thin film resistor (TFR) layer on a semiconductor substrate; depositing a capping layer on the thin film resistor layer; performing a first patterning process on the thin film resistor layer and the capping layer to remove the peripheral areas of the thin film resistor layer and the capping layer; performing a second patterning process on the capping layer to form a first capping structure on the thin film resistor layer; etching the first capping structure to remove the outside of the first capping structure; and forming a dielectric structure on and around the first capping structure, so that at least one or more surfaces of the dielectric structure define a first hole adjacent to the first capping structure. In some embodiments, the method for forming an integrated chip also includes: forming a hard mask layer on the capping layer; and wherein, when etching the first capping structure, the hard mask layer has a first etching rate, and the first etching rate is lower than the second etching rate of the first capping structure. In some embodiments, etching the first capping structure includes performing a wet etching process, wherein the first capping structure includes a curved sidewall, and wherein the first hole is adjacent to the curved sidewall. In some embodiments, etching the first covering structure comprises performing a dry etching process, wherein the first covering structure comprises an inclined straight sidewall, wherein the first hole is adjacent to the inclined straight sidewall. In some embodiments, the thickness of the first covering structure is greater than the thickness of the thin film resistor layer, and wherein the height of the first hole is less than the thickness of the first covering structure.

[0104] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present invention, and they can make various changes, substitutions and modifications to them without departing from the spirit and scope of the present invention.

Claims

1. An integrated chip, characterized in that: include: Semiconductor substrate; a dielectric structure disposed above the semiconductor substrate; a resistor structure disposed in the dielectric structure, wherein the resistor structure comprises a thin film resistor layer and a first covering structure disposed on the thin film resistor layer; as well as The first cavity is disposed in the dielectric structure and is adjacent to the first sidewall of the first covering structure.

2. The integrated chip according to claim 1, characterized in that: A first thermal expansion coefficient of the thin film resistance layer is smaller than a second thermal expansion coefficient of the first covering structure.

3. The integrated chip according to claim 2, characterized in that: The third coefficient of thermal expansion of the first cavity is greater than the second coefficient of thermal expansion.

4. The integrated chip according to claim 1, characterized in that: The first hole extends laterally beyond the upper surface of the thin film resistor layer.

5. The integrated chip according to claim 1, characterized in that: The resistor structure further includes: A second capping structure is disposed on the thin film resistive layer and is laterally spaced apart from the first capping structure, wherein a second cavity is disposed within the dielectric structure and abuts a sidewall of the second capping structure.

6. An integrated chip, characterized in that: include: Semiconductor substrate; a dielectric structure disposed above the semiconductor substrate; a resistor structure disposed in the dielectric structure, wherein the resistor structure comprises a thin film resistor layer, a first covering structure and a second covering structure, wherein the first covering structure and the second covering structure are disposed on opposite sides of the thin film resistor layer; A plurality of vias are disposed in the dielectric structure and above the first covering structure and the second covering structure; a first air gap disposed in the dielectric structure and adjacent to the first cover structure; as well as A second air gap is disposed in the dielectric structure and is adjacent to the second covering structure.

7. The integrated chip according to claim 6, characterized in that: The first covering structure and the second covering structure include conductive material.

8. The integrated chip according to claim 6, characterized in that: The first air gap laterally covers an outer periphery of the first covering structure.

9. The integrated chip according to claim 6, characterized in that: Also includes: A first sidewall spacer structure is disposed along a sidewall of the first covering structure, wherein the first air gap is disposed between a lower surface of a section of the first sidewall spacer structure and a top surface of the thin film resistor layer.

10. The integrated chip according to claim 6, characterized in that: The thermal expansion coefficients of the first covering structure and the second covering structure are different from the thermal expansion coefficient of the thin film resistance layer, and the thermal expansion coefficients of the first air gap and the second air gap are greater than the thermal expansion coefficients of the first covering structure and the second covering structure.

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