Operational amplifier with input offset voltage, band-gap reference circuit and control chip

Abstract

The utility model provides an operational amplifier with an input offset voltage, a band-gap reference circuit and a control chip. The operational amplifier comprises a positive temperature coefficient current source, a first differential input geminate transistor, a second differential input geminate transistor, a first resistor, a first current mirror, a second current mirror and a third current mirror. The first end of the first differential input pair transistor is connected with the first end of the first resistor, the second end of the first resistor is connected with the first end of the second differential input pair transistor, the first end of the positive temperature coefficient current source is connected with power supply voltage, and the second end is connected with a first common node of the first differential input pair transistor and the first resistor; the second end of the first differential input geminate transistor is connected with the input end of the first current mirror; the second end of the second differential input geminate transistor is connected with the input end of the second current mirror; the input end of the third current mirror is connected with the output end of the first current mirror, and the output end is connected with the output end of the second current mirror. By means of the band-gap reference circuit, the precision of the output reference voltage of the band-gap reference circuit with only one bipolar transistor in a branch can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of reference power supply, and in particular to an operational amplifier with input offset voltage, a bandgap reference circuit and a control chip. Background Art

[0002] In order to reduce the power consumption of the bandgap reference circuit, the related art proposes a bandgap reference circuit in which only one bipolar transistor is used in the branch circuit. However, compared with the traditional bandgap reference circuit, the accuracy of the output reference voltage of this bandgap reference circuit is poor. Utility Model Content

[0003] The present application provides an operational amplifier with input offset voltage, a bandgap reference circuit and a control chip, which can improve the accuracy of the output reference voltage of a bandgap reference circuit with only one bipolar transistor in a branch.

[0004] In a first aspect, the present application provides an operational amplifier with input offset voltage, comprising a positive temperature coefficient current source, a first differential input pair of tubes, a second differential input pair of tubes, a first resistor, a first current mirror, a second current mirror, and a third current mirror;

[0005] The first differential input pair tubes and the second differential input pair tubes have the same size, the controlled end of the first differential input pair tubes is the first input end of the operational amplifier, and the controlled end of the second differential input pair tubes is the second input end of the operational amplifier;

[0006] The first end of the first differential input pair is connected to the first end of the first resistor, the second end of the first resistor is connected to the first end of the second differential input pair, the first end of the positive temperature coefficient current source is connected to the power supply voltage, and the second end of the positive temperature coefficient current source is connected to the first common node, wherein the first common node is a common node connected between the first end of the first differential input pair and the first end of the first resistor;

[0007] The second end of the first differential input pair tube is connected to the input end of the first current mirror; the second end of the second differential input pair tube is connected to the input end of the second current mirror; the input end of the third current mirror is connected to the output end of the first current mirror, the output end of the third current mirror is connected to the output end of the second current mirror, and the second common node connected between the output end of the third current mirror and the output end of the second current mirror serves as the output end of the operational amplifier.

[0008] The operational amplifier provided by the present application can provide a first resistor with a precise resistance value between the first common node and the first end of the second differential input pair tube, and its input voltage has the characteristic of an offset voltage, and can provide a positive temperature coefficient offset voltage proportional to the negative temperature coefficient voltage at both ends of the third resistor, effectively offset the negative temperature coefficient, achieve temperature compensation, and finally provide an output reference voltage with a precise voltage value, thereby improving the accuracy of the output reference voltage of the bandgap reference circuit. It can be seen that the accuracy of the output reference voltage of the bandgap reference circuit with only one bipolar transistor in the branch can be improved through this solution.

[0009] In combination with the first aspect, in some possible implementations, the positive temperature coefficient current source includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first bipolar transistor, a second bipolar transistor and a second resistor;

[0010] The gate and drain of the first PMOS tube are connected and connected to the gate of the second PMOS tube and the gate of the third PMOS tube; the source of the first PMOS tube, the source of the second PMOS tube, and the source of the third PMOS tube serve as the first end of the positive temperature coefficient current source, and are used to connect to the power supply voltage; the drain of the third PMOS tube serves as the second end of the positive temperature coefficient current source, and is used to output current;

[0011] The drain and gate of the first NMOS tube are connected and connected to the drain of the second PMOS tube and the gate of the second NMOS tube; the drain of the second NMOS tube is connected to the drain of the first PMOS tube;

[0012] The base and collector of the first bipolar transistor are connected and connected to the source of the first NMOS transistor, the emitter of the first bipolar transistor is connected to the first end of the second resistor, and the second end of the second resistor is grounded;

[0013] The base and collector of the second bipolar transistor are connected and connected to the source of the second NMOS transistor, and the emitter of the second bipolar transistor is grounded;

[0014] The ratio of the emitter junction area of ​​the first bipolar transistor to that of the second bipolar transistor is K:1, where K>1.

[0015] In combination with the first aspect and the above implementations, in some possible implementations, the present invention further includes:

[0016] A capacitor, wherein a first plate of the capacitor is connected to the output end of the operational amplifier, and a second plate of the capacitor is grounded.

[0017] In combination with the first aspect and the above implementations, in some possible implementations, the source voltage of the first NMOS transistor is equal to the source voltage of the second NMOS transistor.

[0018] In combination with the first aspect and the above implementations, in some possible implementations, the first bipolar transistor and the second bipolar transistor are NPN transistors.

[0019] In a second aspect, the present application further provides a bandgap reference circuit, comprising a switch tube, a third bipolar transistor, a third resistor, a fourth resistor, and an operational amplifier with an input offset voltage as claimed in any one of claims 1 to 5;

[0020] The base and collector of the third bipolar transistor are connected and connected to the first end of the third resistor and the first input end of the operational amplifier, and the emitter of the third bipolar transistor is grounded;

[0021] The second end of the third resistor is connected to the first end of the fourth resistor and connected to the second input end of the operational amplifier;

[0022] The controlled end of the switch tube is connected to the output end of the operational amplifier, the first end of the switch tube is connected to the power supply voltage, and the second end of the switch tube is connected to the second end of the fourth resistor and serves as the output end of the bandgap reference circuit.

[0023] In combination with the second aspect, in some possible implementations, the switch tube is a PMOS tube; the gate of the switch tube is connected to the output end of the operational amplifier, the source of the switch tube is connected to the power supply voltage, and the drain of the switch tube is connected to the second end of the fourth resistor;

[0024] The first input terminal of the operational amplifier is an inverting input terminal, and the second input terminal of the operational amplifier is a non-inverting input terminal.

[0025] In combination with the second aspect and the above implementation manner, in some possible implementation manners, the switch tube is an NMOS tube; the gate of the switch tube is connected to the output end of the operational amplifier, the drain of the switch tube is connected to the power supply voltage, and the source of the switch tube is connected to the second end of the fourth resistor;

[0026] The first input terminal of the operational amplifier is a non-inverting input terminal, and the second input terminal of the operational amplifier is an inverting input terminal.

[0027] In combination with the second aspect and the above implementations, in some possible implementations, the third bipolar transistor is an NPN transistor.

[0028] In a third aspect, the present application further provides a control chip, which includes the bandgap reference circuit described in any one of the second aspects above. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a circuit diagram of an operational amplifier with input offset voltage provided in an embodiment of the present application;

[0030] Figure 2 yes Figure 1 Circuit diagram of positive temperature coefficient current source in operational amplifier;

[0031] Figure 3 is a circuit diagram of a bandgap reference circuit provided in an embodiment of the present application;

[0032] Figure 4 It is a circuit diagram of another bandgap reference circuit provided in an embodiment of the present application.

[0033] The description of the reference numerals in the figures is as follows:

[0034] OP—operational amplifier;

[0035] 100—first current mirror; 200—second current mirror; 300—third current mirror;

[0036] T1—first differential input pair of transistors; T2—second differential input pair of transistors;

[0037] R1—first resistor;

[0038] P1—first public node; P2—second public node;

[0039] I1—positive temperature coefficient current source;

[0040] MP1—first PMOS tube; MP2—second PMOS tube; MP3—third PMOS tube;

[0041] MN1—first NMOS tube; MN2—second NMOS tube,

[0042] Q1—a first bipolar transistor; Q2—a second bipolar transistor;

[0043] R2—second resistor;

[0044] Io—the second terminal of the positive temperature coefficient current source;

[0045] C—capacitance;

[0046] J1—non-inverting input terminal; J2—inverting input terminal; J3—output terminal of operational amplifier;

[0047] 400—switch tube, Q3—third bipolar transistor, R3—third resistor, R4—fourth resistor;

[0048] VBG—output terminal of bandgap reference circuit;

[0049] VDD—power supply voltage. DETAILED DESCRIPTION

[0050] The technical solution in the present application will be described clearly and in detail below in conjunction with the accompanying drawings. In the description of the embodiments of the present application, unless otherwise specified, " / " means or, for example, A / B can mean A or B: "and / or" in the text is only a description of the association relationship of associated objects, indicating that there can be three relationships, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present application, "multiple" means two or more than two.

[0051] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as suggesting or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features.

[0052] In order to reduce the power consumption of the bandgap reference circuit, the related art proposes a bandgap reference circuit in which only one bipolar transistor is used in the branch circuit. However, compared with the traditional bandgap reference circuit, the accuracy of the output reference voltage of this bandgap reference circuit is poor.

[0053] In order to solve the above technical problems, embodiments of the present application provide an operational amplifier with input offset voltage, a bandgap reference circuit, and a control chip.

[0054] The following first introduces a bandgap reference circuit provided by an embodiment of the present application in detail with reference to the accompanying drawings of the specification. In the accompanying drawings of the specification, Figure 3 and Figure 4 is a circuit diagram of two bandgap reference circuits provided in an embodiment of the present application, Figure 1 Is applied to Figure 3 and Figure 4 A schematic diagram of an operational amplifier with input offset voltage in a bandgap reference circuit. Figure 2 yes Figure 1 Circuit diagram of a positive temperature coefficient current source in an operational amplifier.

[0055] Please refer to Figure 3 and Figure 4A bandgap reference circuit provided by the present application includes a switch tube 400, a third bipolar transistor Q3, a third resistor R3, a fourth resistor R4, and an operational amplifier OP with an input offset voltage; the base and collector of the third bipolar transistor Q3 are connected and connected to the first end of the third resistor R3 and the first input end of the operational amplifier OP, and the emitter of the third bipolar transistor Q3 is grounded; the second end of the third resistor R3 is connected to the first end of the fourth resistor R4 and connected to the second input end of the operational amplifier OP; the controlled end of the switch tube 400 is connected to the output end J3 of the operational amplifier OP, the first end of the switch tube 400 is connected to the power supply voltage VDD, and the second end of the switch tube 400 is connected to the second end of the fourth resistor R4 and serves as the output end VBG of the bandgap reference circuit.

[0056] Depend on Figure 3 and Figure 4 It can be seen that the bandgap reference circuit provided in the present application is a bandgap reference circuit having only one branch with a third bipolar transistor Q3. The voltage at the output terminal VBG of the bandgap reference circuit is the output reference voltage to be obtained.

[0057] Since the base-emitter voltage of the third bipolar transistor Q3 has a negative temperature coefficient, wherein the third bipolar transistor Q3 can be an NPN transistor, that is, a voltage with a negative temperature coefficient is provided between the base and the emitter of the third bipolar transistor Q3, the present application applies a voltage with a positive temperature coefficient across the third resistor R3 to offset the negative temperature coefficient voltage of the base-emitter of the third bipolar transistor Q3, thereby obtaining an output reference voltage with high temperature stability at the output terminal VBG of the bandgap reference circuit.

[0058] In the bandgap reference circuit, the output terminal J3 of the operational amplifier OP is connected to the controlled terminal of the switch tube 400 to form a negative feedback loop, which can make the output of the bandgap reference circuit more stable. Figure 3 and Figure 4 The switch tube 400 may be a PMOS tube or an NMOS tube. Figure 3 As shown, when the switch tube 400 is a PMOS tube, the gate of the switch tube 400 is connected to the output terminal J3 of the operational amplifier OP, the source of the switch tube 400 is connected to the power supply voltage VDD, and the drain of the switch tube 400 is connected to the second end of the fourth resistor R4; the first input terminal of the operational amplifier OP is the inverting input terminal J2, and the second input terminal of the operational amplifier OP is the non-inverting input terminal J1. The inverting input terminal J2 of the operational amplifier OP is connected to the first end of the third resistor R3, and the non-inverting input terminal J1 of the operational amplifier OP is connected to the second end of the third resistor R3. Figure 4As shown, when the switch tube 400 is an NMOS tube, the gate of the switch tube 400 is connected to the output terminal J3 of the operational amplifier OP, the drain of the switch tube 400 is connected to the power supply voltage VDD, and the source of the switch tube 400 is connected to the second end of the fourth resistor R4; the first input terminal of the operational amplifier OP is the in-phase input terminal J1, and the second input terminal of the operational amplifier OP is the inverting input terminal J2. The in-phase input terminal J1 of the operational amplifier OP is connected to the first end of the third resistor R3, and the inverting input terminal J2 of the operational amplifier OP is connected to the second end of the third resistor R3. For different types of switch tubes 400, it is only necessary to connect the in-phase input terminal J1 and the inverting input terminal J2 of the operational amplifier OP accordingly, which does not affect the voltage with a positive temperature coefficient applied to both ends of the third resistor R3, that is, it does not affect the offset of the negative temperature coefficient voltage of the base-emitter of the third bipolar transistor Q3. Therefore, the designer can select a suitable type of switch tube 400 according to actual needs.

[0059] See also Figure 3 and Figure 4 , the base-emitter voltage of the third bipolar transistor Q3 is V be , the voltage across the third resistor R3 is V OS , we can get the output voltage V at the output terminal VBG of the bandgap reference circuit OUT The expression (1) is:

[0060] V OUT =V be +V OS ×(R3+R4) / R3 (1)

[0061] In formula (1), R3 is the resistance value of the third resistor, and R4 is the resistance value of the fourth resistor.

[0062] It can be seen from formula (1) that the key to obtaining an output reference voltage with high temperature stability lies in the voltage V across the third resistor R3. OS .

[0063] In order to obtain an accurate voltage V across the third resistor R3 OS In an embodiment of the present application, an operational amplifier OP with an input offset voltage is provided. The operational amplifier OP is composed of a current source, two differential input pairs of tubes and three current mirrors, and a resistor is added above a differential input pair of tubes to achieve accurate compensation of the input offset voltage.

[0064] See also Figure 1The operational amplifier OP includes a positive temperature coefficient current source I1, a first differential input pair of tubes T1, a second differential input pair of tubes T2, a first resistor R1, a first current mirror 100, a second current mirror 200 and a third current mirror 300; the first differential input pair of tubes T1 and the second differential input pair of tubes T2 have the same size, the controlled end of the first differential input pair of tubes T1 is the first input end of the operational amplifier OP, and the controlled end of the second differential input pair of tubes T2 is the second input end of the operational amplifier OP; the first end of the first differential input pair of tubes T1 is connected to the first end of the first resistor R1, the second end of the first resistor R1 is connected to the first end of the second differential input pair of tubes T2, the first end of the positive temperature coefficient current source I1 is connected to the power supply voltage VDD, and the positive The second end Io of the temperature coefficient current source I1 is connected to the first common node P1, wherein the first common node P1 is a common node connected between the first end of the first differential input pair tube T1 and the first end of the first resistor R1; the second end of the first differential input pair tube T1 is connected to the input end of the first current mirror 100; the second end of the second differential input pair tube T2 is connected to the input end of the second current mirror 200; the input end of the third current mirror 300 is connected to the output end of the first current mirror 100, the output end of the third current mirror 300 is connected to the output end of the second current mirror 200, and the second common node P2 connected between the output end of the third current mirror 300 and the output end of the second current mirror 200 serves as the output end J3 of the operational amplifier OP.

[0065] In the operational amplifier OP, two NMOS tubes are used to form the first current mirror 100 and the second current mirror 200, and two PMOS tubes are used to form the third current mirror 300. The first differential input pair tube T1 and the second differential input pair tube T2 have the same size, that is, the channel length and channel width of the first differential input pair tube T1 and the second differential input pair tube T2 are the same. The first differential input pair tube T1 and the second differential input pair tube T2 can use the same type of PMOS tube, and a matching design is used in the layout design to ensure accuracy. Since the input pair tubes of the operational amplifier OP in the present application use PMOS tubes, there is no need to add additional resistors on the branches of the bandgap reference circuit, so that the bandgap reference circuit has a smaller chip area.

[0066] It should be noted that the operational amplifier OP can be provided with a first resistor R1 having a precise resistance value between the first common node P1 and the first end of the second differential input pair transistor T2, and its input voltage has the characteristic of an offset voltage, that is, it can provide a voltage proportional to the negative temperature coefficient voltage V at both ends of the third resistor R3. be The positive temperature coefficient offset voltage V OS , effectively offsetting the negative temperature coefficient voltage V beThe negative temperature coefficient of the bandgap reference circuit is used to achieve temperature compensation. Finally, an output reference voltage V with a precise voltage value and high temperature stability is provided at the output terminal VBG of the bandgap reference circuit. OUT , thereby increasing the output reference voltage V of the bandgap reference circuit OUT accuracy.

[0067] In addition, considering that the phase margin of the current in the bandgap reference circuit of the present application may be insufficient, in order to stabilize the loop and improve the circuit stability, the operational amplifier OP of the present application is further provided with a capacitor C, the first plate of the capacitor C is connected to the output terminal J3 of the operational amplifier OP, and the second plate of the capacitor C is grounded, that is, the capacitor C is connected in parallel between the output terminal J3 of the operational amplifier OP and the ground. For example, see Figure 1 The capacitor C can be realized by connecting the gate of the MOS tube to the output terminal J3 of the operational amplifier OP, and grounding the source and drain.

[0068] Figure 1 In the operational amplifier OP shown in FIG. 1 , the positive temperature coefficient current source I1 can be generated by using two bipolar transistors. Figure 2 In some embodiments of the present application, the positive temperature coefficient current source I1 may include a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a first NMOS tube MN1, a second NMOS tube MN2, a first bipolar transistor Q1, a second bipolar transistor Q2, and a second resistor R2; the gate and drain of the first PMOS tube MP1 are connected and connected to the gate of the second PMOS tube MP2 and the gate of the third PMOS tube MP3; the source of the first PMOS tube MP1, the source of the second PMOS tube MP2, and the source of the third PMOS tube MP3 serve as the first end of the positive temperature coefficient current source I1 and are used to access the power supply voltage VDD; the drain of the third PMOS tube MP3 serves as the second end of the positive temperature coefficient current source I1. The terminal Io is used for outputting current; the drain and gate of the first NMOS tube MN1 are connected and connected to the drain of the second PMOS tube MP2 and the gate of the second NMOS tube MN2; the drain of the second NMOS tube MN2 is connected to the drain of the first PMOS tube MP1; the base and collector of the first bipolar transistor Q1 are connected and connected to the source of the first NMOS tube MN1, the emitter of the first bipolar transistor Q1 is connected to the first end of the second resistor R2, and the second end of the second resistor R2 is grounded; the base and collector of the second bipolar transistor Q2 are connected and connected to the source of the second NMOS tube MN2, and the emitter of the second bipolar transistor Q2 is grounded; wherein the ratio of the emitter junction area of ​​the first bipolar transistor Q1 to that of the second bipolar transistor Q2 is K:1, K>1.

[0069] In the embodiment of the present application, the positive temperature coefficient current source I1 utilizes the positive temperature coefficient property of the difference ΔVbe between the base and emitter voltage difference of two bipolar transistors to realize a stable positive temperature coefficient current source. The first bipolar transistor Q1 and the second bipolar transistor Q2 can both be NPN transistors. Figure 2 It can be seen that the first PMOS transistor MP1, the second PMOS transistor MP2, and the third PMOS transistor MP3 form a current mirror. By setting the first NMOS transistor MN1 and the second NMOS transistor MN2, the source voltage of the second NMOS transistor MN2 can be equal to the source voltage of the first NMOS transistor MN1, and the ratio of the emitter junction area of ​​the first bipolar transistor Q1 to the second bipolar transistor Q2 is K:1, K>1, so the voltage across the second resistor R2 is the difference between the base-emitter voltage difference of the first bipolar transistor Q1 and the second bipolar transistor Q2 ΔVbe=Vbe2-Vbe1, and has a positive temperature coefficient, wherein Vbe2 is the base-emitter voltage of the second bipolar transistor Q2, and Vbe1 is the base-emitter voltage of the first bipolar transistor Q1. Therefore, the current (Vbe2-Vbe1) / R2 flowing through the second resistor R2 is a current with a positive temperature coefficient, which can be mirrored to the drain of the third PMOS transistor MP3 through a current mirror, that is, the drain of the third PMOS transistor MP3 can serve as the second end Io of the positive temperature coefficient current source I1 to output the current of the positive temperature coefficient current source I1.

[0070] Secondly, the second aspect of the present application further proposes a control chip, which includes the bandgap reference circuit described in any one of the above locking embodiments.

[0071] The control chip provided in the embodiment of the present application has the bandgap reference circuit of the above embodiment, and thus has all the beneficial effects of the above bandgap reference circuit. The bandgap reference circuit has been described in detail above, so it will not be described again here.

[0072] The same or similar numbers in the drawings of this embodiment correspond to the same or similar parts; in the description of this application, it should be understood that if the terms "upper", "lower", "left", "right", etc. indicate an orientation or position relationship based on the orientation or position relationship shown in the drawings, it is only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, the terms describing the position relationship in the drawings are only used for illustrative purposes and cannot be understood as a limitation on this patent. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0073] The above contents are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. An operational amplifier with input offset voltage, characterized in that: It comprises a positive temperature coefficient current source (I1), a first differential input pair of transistors (T1), a second differential input pair of transistors (T2), a first resistor (R1), a first current mirror (100), a second current mirror (200) and a third current mirror (300); The first differential input pair of tubes (T1) and the second differential input pair of tubes (T2) have the same size, the controlled end of the first differential input pair of tubes (T1) is the first input end of the operational amplifier, and the controlled end of the second differential input pair of tubes (T2) is the second input end of the operational amplifier; The first end of the first differential input pair transistor (T1) is connected to the first end of the first resistor (R1), the second end of the first resistor (R1) is connected to the first end of the second differential input pair transistor (T2), the first end of the positive temperature coefficient current source (I1) is connected to the power supply voltage, and the second end (Io) of the positive temperature coefficient current source (I1) is connected to the first common node (P1), wherein the first common node (P1) is a common node connected between the first end of the first differential input pair transistor (T1) and the first end of the first resistor (R1); The second end of the first differential input pair tube (T1) is connected to the input end of the first current mirror (100); the second end of the second differential input pair tube (T2) is connected to the input end of the second current mirror (200); the input end of the third current mirror (300) is connected to the output end of the first current mirror (100), the output end of the third current mirror (300) is connected to the output end of the second current mirror (200), and the second common node (P2) connected between the output end of the third current mirror (300) and the output end of the second current mirror (200) serves as the output end (J3) of the operational amplifier.

2. The operational amplifier with input offset voltage as claimed in claim 1, characterized in that: The positive temperature coefficient current source (I1) comprises a first PMOS tube (MP1), a second PMOS tube (MP2), a third PMOS tube (MP3), a first NMOS tube (MN1), a second NMOS tube (MN2), a first bipolar transistor (Q1), a second bipolar transistor (Q2) and a second resistor (R2); The gate and drain of the first PMOS tube (MP1) are connected and connected to the gate of the second PMOS tube (MP2) and the gate of the third PMOS tube (MP3); the source of the first PMOS tube (MP1), the source of the second PMOS tube (MP2) and the source of the third PMOS tube (MP3) serve as the first end of the positive temperature coefficient current source (I1) for connecting to the power supply voltage; the drain of the third PMOS tube (MP3) serves as the second end (Io) of the positive temperature coefficient current source (I1) for outputting current; The drain and gate of the first NMOS tube (MN1) are connected and connected to the drain of the second PMOS tube (MP2) and the gate of the second NMOS tube (MN2); the drain of the second NMOS tube (MN2) is connected to the drain of the first PMOS tube (MP1); The base and collector of the first bipolar transistor (Q1) are connected and connected to the source of the first NMOS transistor (MN1); the emitter of the first bipolar transistor (Q1) is connected to the first end of the second resistor (R2); and the second end of the second resistor (R2) is grounded; The base and collector of the second bipolar transistor (Q2) are connected and connected to the source of the second NMOS transistor (MN2), and the emitter of the second bipolar transistor (Q2) is grounded; The ratio of the emitter junction area of ​​the first bipolar transistor (Q1) to that of the second bipolar transistor (Q2) is K:1, where K>1.

3. The operational amplifier with input offset voltage as claimed in claim 1, wherein: Also includes: A capacitor (C), wherein a first plate of the capacitor (C) is connected to an output terminal (J3) of the operational amplifier, and a second plate of the capacitor (C) is grounded.

4. The operational amplifier with input offset voltage as claimed in claim 2, characterized in that: The source voltage of the first NMOS transistor (MN1) is equal to the source voltage of the second NMOS transistor (MN2).

5. The operational amplifier with input offset voltage as claimed in claim 2, characterized in that: The first bipolar transistor (Q1) and the second bipolar transistor (Q2) are NPN transistors.

6. A bandgap reference circuit, characterized in that: It comprises a switch tube (400), a third bipolar transistor (Q3), a third resistor (R3), a fourth resistor (R4), and an operational amplifier with input offset voltage as claimed in any one of claims 1 to 5; The base and collector of the third bipolar transistor (Q3) are connected and connected to the first end of the third resistor (R3) and the first input end of the operational amplifier, and the emitter of the third bipolar transistor (Q3) is grounded; The second end of the third resistor (R3) is connected to the first end of the fourth resistor (R4) and connected to the second input end of the operational amplifier; The controlled end of the switch tube (400) is connected to the output end (J3) of the operational amplifier, the first end of the switch tube (400) is connected to the power supply voltage, and the second end of the switch tube (400) is connected to the second end of the fourth resistor (R4) and serves as the output end of the bandgap reference circuit.

7. The bandgap reference circuit according to claim 6, wherein: The switch tube (400) is a PMOS tube; the gate of the switch tube (400) is connected to the output end (J3) of the operational amplifier, the source of the switch tube (400) is connected to the power supply voltage, and the drain of the switch tube (400) is connected to the second end of the fourth resistor (R4); The first input terminal of the operational amplifier is an inverting input terminal (J2), and the second input terminal of the operational amplifier is a non-inverting input terminal (J1).

8. The bandgap reference circuit according to claim 6, wherein: The switch tube (400) is an NMOS tube; the gate of the switch tube (400) is connected to the output end (J3) of the operational amplifier, the drain of the switch tube (400) is connected to the power supply voltage, and the source of the switch tube (400) is connected to the second end of the fourth resistor (R4); The first input terminal of the operational amplifier is a non-inverting input terminal (J1), and the second input terminal of the operational amplifier is an inverting input terminal (J2).

9. The bandgap reference circuit according to claim 6, wherein: The third bipolar transistor (Q3) is an NPN transistor.

10. A control chip, characterized in that: Comprising the bandgap reference circuit as claimed in any one of claims 6 to 9.

Images