PV input reverse connection prevention circuit of photovoltaic inverter

Abstract

The utility model belongs to the technical field of electronic circuits, and provides a PV input reverse connection prevention circuit of a photovoltaic inverter, and when the PV input reverse connection prevention circuit of the photovoltaic inverter is in reverse connection, PV-voltage is higher than PV +, the reverse connection prevention circuit automatically starts to take power, the extremely low input voltage (about 2V) is boosted to Vout (output voltage), then the output voltage is sent to a grid electrode of a SiC MOS tube, and the reverse connection prevention circuit is connected with the grid electrode of the SiC MOS tube. At the moment, Vgs (driving voltage) is equal to Vout-Vce1, and according to the characteristics of the SiC MOS tube, only proper driving voltage needs to be set, and the SiC MOS tube is reversely conducted, so that the loss of the SiC MOS tube is reduced, the main power tube, namely the SiC MOS tube, is prevented from being overheated and damaged when PV input is reversely connected, and the reliability of the circuit is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of electronic circuits, in particular to a photovoltaic inverter PV input reverse connection prevention circuit. Background Art

[0002] The third-generation power semiconductor SiC MOS has excellent characteristics such as wide bandgap and high thermal conductivity. It is gradually replacing Si MOS in the field of power semiconductors. Due to the wide bandgap, SiC MOS tubes have a higher conduction voltage drop. In the photovoltaic inverter scenario, if SiC MOS is used as a front-end power device, it is necessary to consider the problem of continuous heating and failure of the power tube when the PV input terminal is reversed. The conduction voltage drop of SiC MOS tubes is higher. When the PV input is reversed, the power tube loses more and generates more heat, causing overheating and damage to the inverter. Utility Model Content

[0003] The utility model aims to provide a photovoltaic inverter PV input anti-reverse connection circuit to solve the problem.

[0004] The utility model provides a photovoltaic inverter PV input reverse connection protection circuit, comprising a first diode, a first capacitor, a first inductor, a first switch, a second diode and a second capacitor;

[0005] The cathode of the first diode is connected to the photovoltaic positive input terminal, the anode of the first capacitor is connected to the photovoltaic negative input terminal, the SiC MOS tube is located between the photovoltaic positive input terminal and the photovoltaic negative input terminal, and the anode of the first diode is respectively connected to the cathode of the first capacitor, the current outflow terminal of the first switch, the cathode of the second capacitor and the grounding electrode;

[0006] The positive electrode of the first capacitor is connected to the first end of the first inductor and the source electrode and the photovoltaic negative input end of the SiC MOS tube;

[0007] The second end of the first inductor is connected to the current inflow end of the first switch and the anode of the second diode;

[0008] The driving end of the first switch is connected to the boost pulse width modulator;

[0009] The cathode of the second diode is connected to the anode of the second capacitor and the gate of the SiC MOS tube.

[0010] In the above-mentioned photovoltaic inverter PV input reverse connection protection circuit, when reverse connection occurs, the voltage of PV- (photovoltaic negative input terminal) is higher than PV+ (photovoltaic positive input terminal), the first diode is turned on, the first capacitor is charged, and the reverse connection protection circuit automatically starts to draw power: from an extremely low input voltage (about 2V) to Vout (output voltage), and then the output voltage is sent to the gate of the SiC MOS tube. At this time, Vgs (driving voltage) = Vout-Vce1. According to the characteristics of the SiC MOS tube, as long as a suitable driving voltage is set, the SiC MOS tube is reversely conducted, and the SiC MOS tube works in a saturated conduction state to avoid high losses caused by excessive conduction voltage drop when its body diode is turned on, thereby preventing the main power tube, i.e., the SiC MOS tube, from overheating and damage when the PV input is reversed, thereby increasing the reliability of the circuit.

[0011] Furthermore, the first switch is any one of a MOS tube, an IGBT, and a triode.

[0012] Furthermore, both the first capacitor and the second capacitor are electrolytic capacitors.

[0013] Furthermore, the SiC MOS tube is connected in series with the second inductor and is located between the photovoltaic positive input terminal and the photovoltaic negative input terminal.

[0014] Further, a third diode is included;

[0015] The cathode of the third diode is connected to the gate of the SiC MOS tube, and the anode of the third diode is connected to the cathode of the second diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 The circuit diagram of the photovoltaic inverter PV input anti-reverse connection circuit in the first embodiment of the utility model;

[0017] Figure 2 for Figure 1 The anti-reverse connection circuit test waveform of the photovoltaic inverter PV input anti-reverse connection circuit.

[0018] Description of main component symbols:

[0019] Boost Pulse Width Modulator 10 First capacitor CE1 First Inductor L1 The first diode D1 Second capacitor CE2 Second Inductor L2 The second diode D2 SiC MOS tube Q1 Grounding electrode GND The third diode D3 First switch Q2

[0020] The following specific implementation manner will further illustrate the present utility model in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0021] In order to facilitate the understanding of the utility model, the utility model will be described more comprehensively with reference to the relevant drawings. Several embodiments of the utility model are given in the drawings. However, the utility model can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the utility model more thorough and comprehensive.

[0022] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the technical field of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0024] See also Figure 1 , a photovoltaic inverter PV input anti-reverse connection circuit provided by an embodiment of the utility model includes a first diode D1, a first capacitor CE1, a first inductor L1, a first switch Q2, a second diode D2 and a second capacitor CE2;

[0025] It should be noted that PV+, the second inductor L2, the SiC MOS tube Q1, and PV- are components of the main power circuit, the second inductor L2 is the main power inductor in the main power circuit, the SiC MOS tube Q1 is the main power tube, and the second inductor L2 and the SiC MOS tube Q1 are connected in series to form a main power branch.

[0026] The two ends of the left side of the photovoltaic inverter PV input anti-reverse connection circuit are connected to PV+ and PV- respectively. Specifically, the cathode of the first diode D1 is connected to PV+ (photovoltaic positive input terminal), and the anode of the first capacitor CE1 is connected to PV- (photovoltaic negative input terminal). In addition, the cathode of the first diode D1 is connected to the first end of the second inductor L2, the second end of the second inductor L2 is connected to the drain of the SiCMOS tube Q1, and the anode of the first diode D1 is connected to the cathode of the first capacitor CE1, the current outflow end of the first switch Q2, the cathode of the second capacitor CE2 and the grounding electrode GND respectively;

[0027] The first switch Q2 may be a SiC MOS, or other types of MOS, or may be other switches such as an IGBT, a triode, etc. The positive electrode of the first capacitor CE1 is connected to the first end of the first inductor L1 and the source of the SiC MOS tube;

[0028] The second end of the first inductor L1 is connected to the current inflow end of the first switch Q2 and the anode of the second diode D2;

[0029] The driving end of the first switch Q2 is connected to the boost pulse width modulator 10;

[0030] The cathode of the second diode D2 (where the output signal Vout of the photovoltaic inverter PV input reverse connection protection circuit is output) is connected to the anode of the second capacitor CE2 and the gate of the SiC MOS tube Q1.

[0031] Working principle:

[0032] When the photovoltaic panel is correctly connected, the current flows from PV+ to PV-, the photovoltaic inverter works normally to generate electricity, and the main power tube SiC MOS tube Q1 works in the switching state. When the SiC MOS tube Q1 is driven normally, the on-resistance is very small and the loss is low; at this time, the PV+ voltage is higher than the PV- voltage. Due to the reverse cutoff effect of the first diode D1, the Boost power circuit (i.e., the input reverse connection protection circuit) cannot draw power from the main power circuit, and the main power circuit and the Boost power circuit are isolated by D1;

[0033] When the photovoltaic panel is reversely connected, the PV- voltage is higher than PV+, and the voltage between PV- and PV+ is clamped by the body diode of the main power tube SiCMOS tube Q1. If the aforementioned PV input anti-reverse connection circuit is not added, the voltage between PV- and PV+ is equal to the forward voltage drop of the body diode of SiC MOS tube Q1 (about 5V), which cannot reach the inverter startup voltage. The main power tube SiCMOS tube Q1 cannot be turned off, and the short-circuit current is always loaded on the main power tube, that is, SiC MOS tube Q1. This short-circuit loss is much greater than the normal working loss, which will cause Q1 to heat up and fail in a short time;

[0034] After adding the aforementioned anti-reverse connection circuit, when the photovoltaic panel is reversely connected, the PV- voltage is higher than PV+, the first diode D1 is turned on, and the first capacitor CE1 is charged. At this time, the forward voltage drop of the body diode of Q1 is about 5V, and the voltage of the first capacitor CE1 is slightly higher than the forward voltage drop of the body diode of Q1. The anti-reverse connection circuit automatically starts to draw power (the voltage of the first capacitor CE1 is the input terminal voltage of the anti-reverse connection circuit), and the output voltage Vout is obtained by boosting, and the output voltage Vout is sent to the gate of the SiC MOS tube Q1. At this time, Vgs (driving voltage) of the SiC MOS tube Q1 = Vout-Vce1, Vce1 is the voltage of the first capacitor CE1, and according to the characteristics of the SiCMOS tube Q1, a suitable driving voltage is set for Q1 (for example, for an N-channel SiC MOS tube, Vgs>M, that is, Vout-Vce1>M, M is a threshold, and M of different SiC MOS tubes may be different. For example, in one embodiment, the range of M is 15V-20V), so that the SiC The MOS tube Q1 is reversely conducted (current flows from the source of Q1 to the drain), and the SiC MOS tube Q1 works in a saturated conduction state. The saturated conduction voltage drop of the SiC MOS tube Q1 is about 2V. At this time, the first capacitor CE1 is slightly higher than the saturated conduction voltage drop of the SiC MOS tube Q1, and the anti-reverse connection circuit continues to work. The output voltage Vout that meets the conditions can be obtained by controlling the duty cycle of the driving signal of the first switch Q2 in the anti-reverse connection circuit to continuously drive the SiC MOS tube Q1 to be in a saturated conduction state; since the saturated conduction voltage drop of the SiC MOS tube Q1 is lower than the conduction voltage drop of the SiC MOS tube Q1 body diode, the high loss caused by the excessively high conduction voltage drop when the body diode is turned on is reduced; such as Figure 2 As shown in the figure, the actual test loss can be reduced to about 48.5% ( Figure 2 Left figure relative to Figure 2 Right picture), to avoid overheating and damage of the main power tube, i.e. SiC MOS tube Q1, when the PV input is reversely connected, thus increasing the reliability of the circuit.

[0035] See also Figure 2 , is the anti-reverse connection circuit test waveform of the photovoltaic inverter PV input anti-reverse connection circuit, where the waveforms have the following meanings: C1 yellow waveform: voltage Vce across the first capacitor CE1; C2 green waveform: anti-reverse connection circuit output voltage Vout; C3 purple waveform: current flowing through the main power tube, i.e. SiC MOS tube Q1, i.e. reverse connection current or short-circuit current Iin; C4 blue waveform: voltage drop Vds across the main power tube, i.e. SiC MOS tube Q1; M1 orange waveform: loss of SiC MOS tube Q1. In addition, it should be noted that, Figure 2 Left picture, Figure 2 The horizontal lines in the lower half of the right image are enlarged views of the white frames in their respective upper halves.

[0036] from Figure 2 It can be seen that the loss of SiC MOS tube Q1 can be reduced from 178W ( Figure 2 In the right figure, when PV+ and PV- are reversely connected and there is no Vout to drive the main power tube Q1, the voltage drop across the SiC MOS tube Q1 is the voltage drop of its body diode, which is about 4.45V. The current flowing through the SiC MOS tube Q1 is 40A. According to the loss = voltage drop * current, the loss of the SiC MOS tube Q1 at this time is 178W = 4.45 V * 40 A) down to about 85W ( Figure 2 In the left figure, PV+ and PV- are reversed, and Vout drives the main power tube Q1 to saturate and conduct. At this time, the voltage drop across the SiC MOS tube Q1 is about 2.12V, and the current flowing through the SiC MOS tube Q1 is 40A. At this time, the loss of the SiC MOS tube Q1 is about 85W=2.12V*40A), which drops to about 48.5%, thereby avoiding overheating and damage of the main power tube when the PV input is reversed.

[0037] In one embodiment of the present invention, both the first capacitor CE1 and the second capacitor CE2 are electrolytic capacitors.

[0038] In one embodiment of the present utility model, a third diode D3 is also included;

[0039] The cathode of the third diode D3 is connected to the gate of the SiC MOS transistor Q1 to protect the SiC MOS transistor Q1 , and the anode of the third diode D3 is connected to the cathode of the second diode D2 .

[0040] The above-mentioned embodiments only express several implementation methods of the utility model, and the description is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the utility model. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the utility model, which all belong to the protection scope of the utility model.

Claims

1. A photovoltaic inverter PV input anti-reverse connection circuit, characterized in that: It includes a first diode, a first capacitor, a first inductor, a first switch, a second diode and a second capacitor; The cathode of the first diode is connected to the photovoltaic positive input terminal, the anode of the first capacitor is connected to the photovoltaic negative input terminal, the SiCMOS tube is located between the photovoltaic positive input terminal and the photovoltaic negative input terminal, and the anode of the first diode is respectively connected to the cathode of the first capacitor, the current outflow terminal of the first switch, the cathode of the second capacitor and the grounding electrode; The positive electrode of the first capacitor is connected to the first end of the first inductor and the source electrode and the photovoltaic negative input end of the SiC MOS tube; The second end of the first inductor is connected to the current inflow end of the first switch and the anode of the second diode; The driving end of the first switch is connected to the boost pulse width modulator; The cathode of the second diode is connected to the anode of the second capacitor and the gate of the SiC MOS tube.

2. The photovoltaic inverter PV input anti-reverse connection circuit according to claim 1, characterized in that: The first switch is any one of a MOS tube, an IGBT, and a triode.

3. The photovoltaic inverter PV input anti-reverse connection circuit according to claim 1, characterized in that: The first capacitor and the second capacitor are both electrolytic capacitors.

4. The photovoltaic inverter PV input anti-reverse connection circuit according to claim 1, characterized in that: The SiC MOS tube is connected in series with the second inductor and is located between the photovoltaic positive input terminal and the photovoltaic negative input terminal.

5. The photovoltaic inverter PV input anti-reverse connection circuit according to claim 1, characterized in that: Also including a third diode; The cathode of the third diode is connected to the gate of the SiC MOS tube, and the anode of the third diode is connected to the cathode of the second diode.

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