Layout structure of band-gap reference circuit

Abstract

The utility model discloses a layout structure of a band-gap reference circuit, the band-gap reference circuit comprises a first transistor and a second transistor, the ratio of the first transistor to the second transistor is 1: 10, the first transistor is arranged at the central position, and the second transistor is arranged around the first transistor, the second transistors located on the upper side and the lower side of the first transistor are symmetrically distributed about a first reference line, the second transistors located on the left side and the right side of the first transistor are symmetrically distributed about a second reference line, the first reference line and the second reference line are vertically arranged, and the first transistor is connected with all the second transistors through metal wires. The base of the first transistor and the bases of all the second transistors are at the same potential, the emitters of all the second transistors are at the same potential, and the collectors of all the second transistors are at the same potential. The problem that in the prior art, a band-gap reference circuit is low in precision is solved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor devices, and more specifically, to a layout structure of a bandgap reference circuit. Background Art

[0002] Bandgap circuits are widely used in integrated circuits. For bandgap reference circuits, the power supply needs to output a precise voltage, which requires a precise reference point, which is the reference voltage. In commonly used reference voltage circuits, the bandgap reference source is a common and accurate reference source. How to layout the layout structure of the bandgap reference source so that it can achieve an accurate reference source is an urgent problem to be solved at this stage. Utility Model Content

[0003] The utility model provides a layout structure of a bandgap reference circuit to solve the problem of low precision of the bandgap reference circuit in the prior art.

[0004] The utility model provides a layout structure of a bandgap reference circuit, the bandgap reference circuit comprises a first transistor and a second transistor whose ratio is 1:10, the first transistor is arranged at a central position, the second transistor is arranged around the first transistor, the second transistors located on the upper side and the lower side of the first transistor are symmetrically distributed about a first reference line, the second transistors located on the left side and the right side of the first transistor are symmetrically distributed about the second reference line, the first reference line and the second reference line are vertically arranged, the first transistor is connected to all the second transistors through metal wiring, so that the base of the first transistor and the base of all the second transistors are at the same potential, and the emitters of all the second transistors are at the same potential, so that the collectors of all the second transistors are at the same potential.

[0005] Preferably, the first transistor and eight of the second transistors are arranged in a nine-square grid, the first transistor is located at the center of the nine-square grid, and the second transistors are located at other positions of the nine-square grid.

[0006] Preferably, each of the transistors comprises a collector region, an emitter region, and a base region, wherein the collector region surrounds the emitter region and the base region, and the base region is located between the emitter region and the collector region and on one side of the emitter region.

[0007] Preferably, the remaining two second transistors are respectively located on the opposite first side and second side of the first transistor, and are arranged side by side with the second transistor of the second row of the nine-square grid, wherein the first side and the second side are set to be two sides adjacent to the side of the base region located on the emitter region.

[0008] Preferably, the first transistor is connected to all the second transistors via two-layer metal layer wiring.

[0009] Preferably, the metal layer wiring includes a first metal connection structure, a second metal connection structure, a third metal connection structure, a fourth metal connection structure and a fifth metal connection structure; wherein the first metal connection structure is used to connect the collectors of all the second transistors together, the second metal connection structure is used to connect the bases of all the transistors together and serve as a first lead-out terminal, the third metal connection structure is used to connect the emitters of all the second transistors together, the fourth metal connection structure is used to lead out the emitter of the first transistor and serve as a second lead-out terminal, and the fifth metal connection structure is used to lead out the collector of the first transistor and serve as a third lead-out terminal.

[0010] Preferably, the first metal connection structure includes a plurality of sections of first metal wiring, which are interconnected, wherein the plurality of sections of the first metal wiring are all located in the second metal layer.

[0011] Preferably, the second metal connection structure includes multiple segments of second metal wiring located in the second metal layer and multiple segments of third metal wiring located in the first metal layer, wherein the multiple segments of the second metal wiring are used to connect the bases of the transistors located in the same row together; the multiple segments of the third metal wiring are used to connect the multiple segments of the second metal wiring located in different rows together and serve as the first lead-out terminal.

[0012] Preferably, the third metal connection structure includes multiple segments of fourth metal wiring located in the second metal layer and multiple segments of fifth metal wiring located in the first metal layer, wherein the multiple segments of the fourth metal wiring are used to connect the emitters of the second transistors located in the same row together, and the multiple segments of the fifth metal wiring are used to connect the multiple segments of the fourth metal wiring located in different rows together.

[0013] Preferably, the fourth metal connection structure includes a section of sixth metal wiring located in the second metal layer and a section of seventh metal wiring located in the first metal layer, wherein the sixth metal wiring is connected to the emitter of the first transistor, the seventh metal wiring is connected to the sixth metal wiring through a through hole, and the seventh metal wiring also serves as a second lead-out terminal.

[0014] Preferably, the fifth metal connection structure includes a section of an eighth metal wiring located in the second metal layer and a ninth metal wiring located in the first metal layer, wherein the ninth metal wiring is connected to the collector of the first transistor, the ninth metal wiring is connected to the eighth metal wiring through a through hole, and the ninth metal wiring also serves as a third lead-out terminal.

[0015] Preferably, the layout structure also includes: a plurality of virtual transistors, which are arranged around the outer end of the layout structure of the bandgap reference circuit, and the collectors, bases and emitters of the plurality of virtual transistors are at the same potential, and the plurality of virtual transistors are used to counteract the influence of the process manufacturing process on the fully matched transistor.

[0016] Preferably, the plurality of dummy transistors are connected via a sixth metal connection structure, so that the bases, emitters and collectors of all the dummy transistors are at the same potential.

[0017] Preferably, the sixth metal connection structure includes a plurality of segments of the tenth metal wiring, the plurality of segments of the tenth metal wiring are interconnected, and the plurality of segments of the tenth metal wiring are all located in the first metal layer.

[0018] The layout structure of the bandgap reference circuit provided by the utility model, firstly, can ensure that all devices are in the same direction, and can achieve lateral matching, longitudinal matching, and center matching of transistors. Secondly, such a layout can keep the first transistor Q0 in the middle. Thirdly, during the chip manufacturing process, since each transistor will be affected by stress from all directions, temperature gradient, and the influence of the chip during the etching process, such a layout can make the differences between the above-mentioned stress influence, temperature gradient influence, and the influence of the chip during the etching process close. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and other purposes, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0020] Figure 1 The schematic diagram of the bandgap reference circuit of the utility model is shown;

[0021] Figure 2 A schematic diagram showing the layout structure of a bandgap reference circuit according to a first embodiment of the present invention;

[0022] Figure 3 A schematic diagram showing the layout structure of a bandgap reference circuit according to a second embodiment of the present invention;

[0023] Figure 4 A schematic diagram showing the layout structure of the transistor in the utility model;

[0024] Figure 5 A schematic diagram showing the cross-sectional structure of the transistor in the present invention. DETAILED DESCRIPTION

[0025] The present invention will be described in more detail below with reference to the accompanying drawings. In each of the drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, the layout structure of the bandgap reference circuit obtained after several steps can be described in one figure.

[0026] It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Furthermore, if the device is turned over, the layer or a region will be "below" or "beneath" another layer or another region.

[0027] If it is to describe the situation of being directly located on another layer or another region, the expression "A is directly on B" or "A is on B and adjacent to it" will be used in this article. In this application, "A is directly located in B" means that A is located in B and A is directly adjacent to B, rather than A being located in a doped region formed in B.

[0028] In the present application, the term "punching" refers to a phenomenon in which adjacent leads come into contact with each other and cause a short circuit due to the impact of the packaging material during the process of injecting the packaging material after the chip is fixed on the lead frame and wire bonding is performed.

[0029] Many specific details of the present invention are described below, such as device structure, materials, dimensions, processing technology and techniques, so as to more clearly understand the present invention. However, as those skilled in the art will appreciate, the present invention may be implemented without following these specific details.

[0030] Embodiment 1:

[0031] Figure 1 The schematic diagram of the bandgap reference circuit of the utility model is shown as follows: Figure 1 As shown, in the bandgap reference circuit of the embodiment of the present application, the ratio of the first transistor to the second transistor is 1:10, that is, the bandgap reference circuit includes one first transistor Q0 and all second transistors Q1, wherein the base of the first transistor Q0 and the bases of all second transistors Q1 are connected together and led out, and the lead-out terminal is named VBG; the emitter of the first transistor Q0 is led out, and the lead-out terminal is named F; the collector of the first transistor Q0 is led out, and the lead-out terminal is named A. In addition, the collectors of all second transistors Q1 are connected together and led out, and the lead-out terminal is named G; the emitters of all second transistors Q1 are connected together and led out, and the lead-out terminal is named H.

[0032] Figure 2 A schematic diagram showing the layout structure of a bandgap reference circuit according to a first embodiment of the present invention is shown; Figure 2 As shown, in the layout structure of the bandgap reference circuit, the first transistor Q0 is set at the center position; the second transistor Q1 is set around the first transistor Q0, wherein the second transistors Q1 located on the upper and lower sides of the first transistor Q0 are symmetrically distributed about the first reference line, and the second transistors Q1 located on the left and right sides of the first transistor Q0 are symmetrically distributed about the second reference line, and the first reference line and the second reference line are vertically arranged.

[0033] The first transistor Q0 is connected to all the second transistors Q1 through metal wiring, so that the base of the first transistor Q0 and the bases of all the second transistors Q1 are at the same potential, and the emitters of all the second transistors Q1 are at the same potential. In addition, the collectors of all the second transistors Q1 are at the same potential.

[0034] In this embodiment, eight of the second transistors Q1 are arranged around the first transistor Q0, that is, the first transistor Q0 and the eight of the second transistors Q1 are arranged in a nine-square grid, with the first transistor Q0 located at the center of the nine-square grid and the eight of the second transistors Q1 located at other positions of the nine-square grid.

[0035] In this embodiment, each of the transistors includes a collector region C, an emitter region E and a base region B, wherein the collector region C surrounds the emitter region E and the base region B, and the base region B is located between the emitter region E and the collector region C and on one side of the emitter region E.

[0036] In this embodiment, the remaining two second transistors Q1 are respectively located on the first side and the second side opposite to the first transistor Q0, and are arranged side by side with the second transistor Q1 of the second row of the nine-square grid, wherein the first side and the second side are set to be two sides adjacent to the side of the base region B located on the emitter region E.

[0037] Specifically, in this embodiment, Figure 2As shown, two second transistors Q1 are respectively arranged on the left and right sides of the first transistor Q0; and three second transistors Q1 are respectively arranged on the upper and lower sides of the first transistor Q0; wherein the four second transistors Q1 located on the left and right sides of the first transistor Q0 are symmetrically distributed about the second reference line; and the six second transistors Q1 located on the upper and lower sides of the first transistor Q0 are symmetrically distributed about the first reference line. That is to say, in this embodiment, the first transistor Q0 is arranged at the center, and all the second transistors Q1 are arranged around the first transistor Q0, wherein the eight second transistors Q1 and the first transistor Q0 form a nine-square grid arrangement, and the remaining two second transistors Q1 are respectively located on the first side and the second side opposite to the first transistor Q0, and are arranged side by side with the second transistors Q1 in the second row of the nine-square grid.

[0038] In other embodiments, the first transistor and all the second transistors may also be arranged in other styles, as long as the second transistor Q1 is arranged around the first transistor Q0, and the second transistors Q1 located on the upper and lower sides of the first transistor Q0 are symmetrically distributed about the first reference line, and the second transistors Q1 located on the left and right sides of the first transistor Q0 are symmetrically distributed about the second reference line, the first reference line and the second reference line are vertically arranged and may also be subjected to several deformations and improvements, which all fall within the scope of protection of the present application and will not be elaborated here.

[0039] In an embodiment of the present application, the first transistor Q0 is connected to all the second transistors Q1 through two layers of metal wiring, so that the bases of the first transistor Q0 and all the second transistors Q1 are at the same potential, and the emitters of all the second transistors Q1 are at the same potential, so that the collectors of all the second transistors Q1 are at the same potential.

[0040] like Figure 2 As shown, in other embodiments, the metal layer includes a first metal connection structure 11, a second metal connection structure 21, a third metal connection structure 31, a fourth metal connection structure 41 and a fifth metal connection structure 51; wherein the first metal connection structure 11 is used to connect the collectors of all the second transistors Q1 together, the second metal connection structure 21 is used to connect the bases of all transistors together and serve as the first lead-out terminal VBG, the third metal connection structure 31 is used to connect the emitters of all the second transistors Q1 together, the fourth metal connection structure 41 is used to lead out the emitter of the first transistor Q0 and serve as the second lead-out terminal F, and the fifth metal connection structure 51 is used to lead out the collector of the first transistor Q0 and serve as the third lead-out terminal A.

[0041] In this embodiment, the first metal connection structure 11 includes a plurality of first metal wiring segments, the plurality of first metal wiring segments are interconnected, and the plurality of first metal wiring segments are all located in the second metal layer.

[0042] Specifically, Figure 2 As shown, the first metal connection structure 11 includes a first-segment first metal wiring 111, a second-segment first metal wiring 112, a third-segment first metal wiring 113, and a fourth-segment first metal wiring 114. In this embodiment, the collectors of the three second transistors Q1 located in the first row of the nine-square grid are connected to the first-segment first metal wiring 111 through three through holes Via1, the collectors of the two second transistors Q1 located in the second row and on the left side of the first transistor Q0 are connected to the second-segment first metal wiring 112 through two through holes Via1, and the collectors of the two second transistors Q1 located in the second row and on the right side of the first transistor Q0 are connected to the third-segment first metal wiring 113 through two through holes Via1. The collectors of the three second transistors Q1 in the third row of the grid are connected to the fourth-segment first metal wiring 114 through three through holes Via1 respectively; wherein, one end of the first-segment first metal wiring 111 is connected to the second-segment first metal wiring 112, the other end of the first-segment first metal wiring 111 is connected to the third-segment first metal wiring 113, one end of the fourth-segment first metal wiring 114 is connected to the second-segment first metal wiring 112, and the other end of the fourth-segment first metal wiring 114 is connected to the third-segment first metal wiring 113.

[0043] For details, please continue to refer to Figure 2 As shown, the second metal connection structure 12 includes multiple segments of second metal wiring located in the second metal layer and multiple segments of third metal wiring located in the first metal layer, wherein the multiple segments of the second metal wiring are used to connect the bases of the transistors located in the same row together, and the multiple segments of the third metal wiring are used to connect the multiple segments of the second metal wiring located in different rows together and lead out as the first lead-out terminal VBG. Specifically, the second metal connection structure 12 includes a first segment of second metal wiring 211, a second segment of second metal wiring 212, a third segment of second metal wiring 213, a fourth segment of second metal wiring 214, a fifth segment of second metal wiring 215, a first segment of third metal wiring 216, and a second segment of third metal wiring 217.

[0044] like Figure 2As shown, in this embodiment, the bases of the three second transistors Q1 located in the first row of the nine-square grid are connected to the first-segment second metal wiring 211 through three through holes Via1, the bases of the first transistor Q0 located at the center of the second row and the four second transistors Q1 located on the left and right sides of the first transistor Q0 are connected to the second-segment second metal wiring 212 through five through holes Via1; the bases of the three second transistors Q1 located in the third row of the nine-square grid are connected to the third-segment second metal wiring 213 through three through holes Via1. The fourth-segment second metal wiring 214 is used to connect the second-segment second metal wiring 212 with the third-segment second metal wiring 213, wherein the fourth-segment second metal wiring 214 includes two, and the two fourth-segment second metal wirings 214 are respectively arranged on the left and right sides of the first transistor Q0, and are symmetrically distributed with respect to the second reference line, and the fourth-segment second metal wiring 214 is located in the second metal layer; one end of the fifth-segment second metal wiring 215 is connected to the second-segment second metal wiring 212, and the other end of the fifth-segment second metal wiring 215 is connected to the first-segment third metal wiring 216. One end of the first segment third metal wiring 216 is connected together through the through hole Via2, and the other end of the first segment third metal wiring 216 is connected to the first segment second metal wiring 211 through the through hole Via2, wherein the fifth segment second metal wiring 215 includes two, and the two fifth segment second metal wirings 215 are respectively arranged on the left and right sides of the first transistor Q0, and are symmetrically distributed with respect to the second reference line, and the two fifth segment second metal wirings 215 are located in the second metal layer; the first segment third metal wiring 216 includes two, and the two first segment third metal wirings 216 are respectively arranged on the left and right sides of the first transistor Q0, and are symmetrically distributed with respect to the second reference line. The two first-segment third metal wirings 216 are symmetrically distributed along the second reference line, and are located on the first metal layer; one end of the second-segment third metal wiring 217 is connected to the third-segment second metal wiring 213 through a through hole Via2, and the other end of the second-segment third metal wiring 217 is led out as a first lead-out terminal VBG, wherein the second-segment third metal wiring 217 includes two, and the two second-segment third metal wirings 217 are respectively arranged on the left and right sides of the first transistor Q0, and are symmetrically distributed along the second reference line, and the two second-segment third metal wirings 217 are located on the first metal layer.

[0045] Continue to refer to Figure 2As shown, the third metal connection structure 31 includes multiple segments of fourth metal wiring located in the second metal layer and multiple segments of fifth metal wiring located in the first metal layer, wherein the multiple segments of the fourth metal wiring are used to connect the emitters of the second transistors located in the same row together, and the multiple segments of the fifth metal wiring are used to connect the multiple segments of the fourth metal wiring located in different rows together. Specifically, the third metal connection structure 31 includes a first segment of fourth metal wiring 311, a second segment of fourth metal wiring 312, a third segment of fourth metal wiring 313, a fourth segment of fourth metal wiring 314, and a first segment of fifth metal wiring 315.

[0046] like Figure 2 As shown, in this embodiment, the emitters of the three second transistors Q1 located in the first row of the nine-square grid are connected to the first-segment fourth metal wiring 311 through three through holes Via1 respectively; the emitters of the two second transistors Q1 located in the second row and on the left side of the first transistor Q0 are connected to the second-segment fourth metal wiring 312 through two through holes Via1 respectively; the emitters of the two second transistors Q1 located in the second row and on the right side of the first transistor Q0 are connected to the third-segment fourth metal wiring 313 through two through holes Via1 respectively; the three second transistors Q1 located in the third row of the nine-square grid are connected to the third-segment fourth metal wiring 314 through two through holes Via1 respectively. Transistor Q1, the emitters of the three second transistors Q1 are respectively connected to the fourth-segment fourth metal wiring 314 through three through holes Via1; the first-segment fifth metal wiring 315 is used to connect the first-segment fourth metal wiring 311, the second-segment fourth metal wiring 312, the third-segment fourth metal wiring 313 and the fourth-segment fourth metal wiring 314 together, wherein the first-segment fifth metal wiring 315 includes two, and the two first-segment fifth metal wirings 315 are respectively arranged on the left and right sides of the first transistor Q0, and are symmetrically distributed on the left and right sides of the second reference line, and the first-segment fifth metal wiring 315 is located on the first metal layer. One end of the first-segment fifth metal wiring 315 is connected to the first-segment fourth metal wiring 311 through the through-hole Via2, and the other end of the first-segment fifth metal wiring 315 is connected to the fourth-segment fourth metal wiring 314 through the through-hole Via2, and the middle part of one of the first-segment fifth metal wirings 315 is connected to the second-segment fourth metal wiring 312 through the through-hole Via2, and the middle part of another first-segment fifth metal wiring 315 is connected to the third-segment fourth metal wiring 313 through the through-hole Via2.

[0047] Continue to refer to Figure 2As shown, the fourth metal connection structure 41 includes a sixth metal wiring located in the second metal layer and a seventh metal wiring located in the first metal layer, wherein the sixth metal wiring is connected to the emitter of the first transistor through a via Via1, the seventh metal wiring is connected to the sixth metal wiring through a via, and the seventh metal wiring serves as a second lead terminal. Specifically, the fourth metal connection structure 41 includes a sixth metal wiring 411 and a seventh metal wiring 511.

[0048] like Figure 2 As shown, in this embodiment, the emitter of the first transistor is connected to the sixth metal wiring 411 through the via Via1, wherein the sixth metal wiring 411 is arranged on the second metal layer, the sixth metal wiring 411 is connected to the seventh metal wiring 511 through the via Via2, and the seventh metal wiring 511 is arranged on the first metal layer. The seventh metal wiring 511 is also led out as a second lead terminal F.

[0049] Continue to refer to Figure 2 As shown, the fifth metal connection structure 51 includes a section of an eighth metal wiring located in the second metal layer and a ninth metal wiring located in the first metal layer, wherein the ninth metal wiring is connected to the eighth metal wiring through a through hole, and the ninth metal wiring serves as a third lead-out terminal. Specifically, the fifth metal connection structure 51 includes an eighth metal wiring 611 and a ninth metal wiring 711.

[0050] like Figure 2 As shown, in this embodiment, the collector of the first transistor is connected to the eighth metal wiring 611 through the via Via1, wherein the eighth metal wiring 611 is arranged in the second metal layer, and the eighth metal wiring 611 is connected to the ninth metal wiring 711 through the via Via2, and the ninth metal wiring 711 is arranged in the first metal layer. The ninth metal wiring 711 is also led out as the third lead terminal A.

[0051] The through hole is an opening in the insulating layer between metal layers. In this embodiment, the metal layers refer to the first metal layer and the second metal layer. The through hole is used for connection between the first metal layer and the second metal layer.

[0052] The contact hole is an opening of the insulating layer between the first metal layer and the active region or polysilicon. In this embodiment, the contact hole is used for connection between the first metal layer and the active region or polysilicon.

[0053] According to the above layout, the bandgap reference circuit can first ensure that all transistors are in the same direction, and can achieve lateral matching, vertical matching, and center matching of the transistors. Secondly, such a layout can keep the first transistor Q0 in the middle. Thirdly, during the chip manufacturing process, since each transistor will be affected by stress from all directions, temperature gradient, and the impact of the chip during the etching process, such a layout makes the layout structure of the bandgap reference circuit close to a rectangle, thereby minimizing the stress impact of each transistor; since all second transistors are basically the same distance from the first transistor, the temperature gradient impact is minimized; due to such a layout, the layout structure of the bandgap reference circuit is close to a rectangle, thereby minimizing the impact of the chip during the etching process.

[0054] Embodiment 2:

[0055] In other embodiments, Figure 3 As shown, based on the first embodiment, the layout structure of the bandgap reference circuit also includes a plurality of virtual transistors, which are arranged around the outer end of the layout structure of the bandgap reference circuit, and the collectors, bases and emitters of the plurality of virtual transistors are at the same potential, and the plurality of virtual transistors are used to counteract the influence of the process manufacturing process on the fully matched transistor. In this embodiment, the layout structure of the first embodiment is omitted, and only the layout between the plurality of virtual transistors and the virtual transistors is shown.

[0056] In other embodiments, the plurality of virtual transistors are connected via a sixth metal connection structure, so that the bases, emitters and collectors of all the virtual transistors are at the same potential. Specifically, the sixth metal connection structure includes a plurality of segments of the tenth metal wiring, the plurality of segments of the tenth metal wiring are interconnected, and the plurality of segments of the tenth metal wiring are all located in the first metal layer.

[0057] In other embodiments, Figure 4 As shown, the layout structure substrate 7 of the transistor also includes a first well region 5, which is arranged in the substrate 7, and the first well region 5 is of the second doping type; it also includes a second well region 4, which is arranged in the first well region 5, and the second well region 4 is of the first doping type; it also includes an emitter region 3, which is arranged in the second well region 4, and the emitter region 3 is of the second doping type; it also includes a base region 2, which is arranged in the second well region 4, and the base region 2 is arranged on one side of the emitter region 3, and the base region 2 is of the first doping type; it also includes a collector region 1, which is arranged in the first well region 5, and the collector region 1 is arranged around the emitter region 3 and the base region 2, and the collector region 1 is of the second doping type. In the embodiment of the present application, the first doping type is P-type doping, and the second doping type is N-type doping.

[0058] In other embodiments, Figure 5As shown, the layout structure of the transistor further includes a low-concentration doping region 8 . In this embodiment, the low-concentration doping region 8 is disposed in the second well region 4 , and the emitter region 3 is disposed in the low-concentration doping region 8 .

[0059] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0060] According to the embodiments of the utility model described above, these embodiments do not describe all the details in detail, nor do they limit the utility model to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the utility model, so that technicians in the relevant technical field can make good use of the utility model and the modified use based on the utility model. The utility model is only limited by the claims and their full scope and equivalents.

Claims

1. A layout structure of a bandgap reference circuit, the bandgap reference circuit comprising a first transistor and a second transistor with a ratio relationship of 1:10, characterized in that: The first transistor is arranged at the center position, The second transistors are arranged around the first transistor, wherein the second transistors located on the upper side and the lower side of the first transistor are symmetrically distributed about a first reference line, and the second transistors located on the left side and the right side of the first transistor are symmetrically distributed about a second reference line, and the first reference line and the second reference line are vertically arranged. The first transistor is connected to all the second transistors through metal wiring, so that the base of the first transistor and the bases of all the second transistors are at the same potential, and the emitters of all the second transistors are at the same potential, and the collectors of all the second transistors are at the same potential.

2. The layout structure of the bandgap reference circuit according to claim 1, characterized in that: The first transistor and eight of the second transistors are arranged in a nine-square grid, The first transistor is located at the center of the nine-square grid, and the second transistor is located at other positions of the nine-square grid.

3. The layout structure of the bandgap reference circuit according to claim 2, characterized in that: Each of the transistors comprises a collector region, an emitter region and a base region, The collector region surrounds the emitter region and the base region, and the base region is located between the emitter region and the collector region and is located on one side of the emitter region.

4. The layout structure of the bandgap reference circuit according to claim 3, characterized in that: The remaining two second transistors are respectively located on the first side and the second side opposite to the first transistor, and are arranged side by side with the second transistors in the second row of the nine-square grid. The first side and the second side are arranged to be two sides adjacent to a side of the base region located at the emitter region.

5. The layout structure of the bandgap reference circuit according to claim 1, characterized in that: The first transistor is connected to all the second transistors via two-layer metal layer wiring.

6. The layout structure of the bandgap reference circuit according to claim 5, characterized in that: The metal layer wiring includes a first metal connection structure, a second metal connection structure, a third metal connection structure, a fourth metal connection structure and a fifth metal connection structure; wherein the first metal connection structure is used to connect the collectors of all the second transistors together, the second metal connection structure is used to connect the bases of all the transistors together and serve as a first lead-out terminal, the third metal connection structure is used to connect the emitters of all the second transistors together, the fourth metal connection structure is used to lead out the emitter of the first transistor and serve as a second lead-out terminal, and the fifth metal connection structure is used to lead out the collector of the first transistor and serve as a third lead-out terminal.

7. The layout structure of the bandgap reference circuit according to claim 6, characterized in that: The first metal connection structure includes a plurality of sections of first metal wiring, which are interconnected, wherein the plurality of sections of the first metal wiring are all located in the second metal layer.

8. The layout structure of the bandgap reference circuit according to claim 6, characterized in that: The second metal connection structure includes multiple segments of second metal wiring located in the second metal layer and multiple segments of third metal wiring located in the first metal layer, wherein the multiple segments of the second metal wiring are used to connect the bases of the transistors located in the same row together; the multiple segments of the third metal wiring are used to connect the multiple segments of the second metal wiring located in different rows together and serve as the first lead-out terminal.

9. The layout structure of the bandgap reference circuit according to claim 6, characterized in that: The third metal connection structure includes multiple segments of fourth metal wiring located in the second metal layer and multiple segments of fifth metal wiring located in the first metal layer, wherein the multiple segments of the fourth metal wiring are used to connect the emitters of the second transistors located in the same row together, and the multiple segments of the fifth metal wiring are used to connect the multiple segments of the fourth metal wiring located in different rows together.

10. The layout structure of the bandgap reference circuit according to claim 6, characterized in that: The fourth metal connection structure includes a section of the sixth metal wiring located in the second metal layer and a section of the seventh metal wiring located in the first metal layer, wherein the sixth metal wiring is connected to the emitter of the first transistor, the seventh metal wiring is connected to the sixth metal wiring through a through hole, and the seventh metal wiring also serves as a second lead-out terminal.

11. The layout structure of the bandgap reference circuit according to claim 6, characterized in that: The fifth metal connection structure includes a section of an eighth metal wiring located in the second metal layer and a ninth metal wiring located in the first metal layer, wherein the ninth metal wiring is connected to the collector of the first transistor, the ninth metal wiring is connected to the eighth metal wiring through a through hole, and the ninth metal wiring also serves as a third lead-out terminal.

12. The layout structure of the bandgap reference circuit according to claim 1, characterized in that: The layout structure also includes: multiple virtual transistors, which are arranged around the outer end of the layout structure of the bandgap reference circuit, and the collectors, bases and emitters of the multiple virtual transistors are all at the same potential. The multiple virtual transistors are used to counteract the impact of the process manufacturing process on the fully matched transistor.

13. The layout structure of the bandgap reference circuit according to claim 12, characterized in that: The plurality of dummy transistors are connected to each other via a sixth metal connection structure, so that the bases, emitters and collectors of all the dummy transistors are at the same potential.

14. The layout structure of the bandgap reference circuit according to claim 13, characterized in that: The sixth metal connection structure includes a plurality of segments of the tenth metal wiring, the plurality of segments of the tenth metal wiring are interconnected, and the plurality of segments of the tenth metal wiring are all located in the first metal layer.

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