Short circuit detection circuit and inverter
By designing a comparison circuit that directly determines short-circuit faults in the inverter, the damage problem of high-voltage devices such as IGBT in the case of short-circuit faults is solved, and faster and more accurate protection is achieved, avoiding device damage.
Patent Information
- Application Number
- CN202420529514.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-18
- Publication Date
- 2025-01-14
- Estimated Expiration
- 2034-03-18
AI Technical Summary
In the prior art, high-voltage power devices such as IGBT in photovoltaic/photostor inverters lack effective protection when short-circuit failure, resulting in device damage. The short-circuit protection scheme for Hall current sampling has a long delay, resulting in actual protection points. Higher than the protection point of theoretical calculation.
Design a short-circuit detection circuit, use the first comparison circuit and the second comparison circuit to generate signals in the three-level topology structure, directly determine whether the inverter circuit has a short-circuit fault, reduce the delay in the signal conversion path, and avoid multi-level operations Use of discharge circuit.
By directly judging the short circuit fault of the inverter circuit, reducing delay, improving protection speed, avoiding device damage, and achieving faster and more accurate short circuit detection.
Smart Images
Figure CN222354042U_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the technical field of short-circuit detection, and in particular, relates to a short-circuit detection circuit and an inverter. Background Art
[0002] High-voltage power devices such as IGBTs are commonly used in photovoltaic / solar storage inverters. Since the devices themselves do not have short-circuit protection functions, they are easily damaged when a short-circuit fault occurs in the circuit in which the devices are used.
[0003] In the related art, a Hall current sampling scheme is usually adopted to implement short-circuit protection. This scheme converts the sampled current into a voltage signal, and uses a multi-stage operational amplifier circuit and a comparison circuit to determine the circuit short-circuit fault based on the voltage signal. However, each stage of the operational amplifier circuit and the comparison circuit in the above scheme has a device response delay. Therefore, there is a long delay in determining whether a short-circuit fault occurs in the circuit, which makes the actual current protection point higher than the theoretically calculated protection point, causing device damage. Utility Model Content
[0004] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a short-circuit detection circuit and an inverter, which can determine whether a short-circuit fault occurs in an inverter circuit including a three-level topology structure according to the signals generated by a first comparison circuit and a second comparison circuit, without the need to use a multi-stage operational amplifier circuit for signal conversion, thereby reducing the delay on the short-circuit detection path, speeding up the protection speed, and avoiding device damage.
[0005] In a first aspect, the present application provides a short circuit detection circuit, which is applied to a three-level topology structure. The three-level topology structure includes an upper bridge arm and a lower bridge arm. The short circuit detection circuit includes:
[0006] A step-down circuit, wherein the input end of the step-down circuit is electrically connected to the input end of the upper bridge arm, and the voltage reduction amplitude of the input end of the step-down circuit is greater than the turn-on voltage drop of the upper bridge arm in a non-overcurrent state;
[0007] A first comparison circuit is electrically connected to the output end of the step-down circuit and the output end of the upper bridge arm, respectively, the potential of the input end is higher than the potential of the output end, and the first comparison circuit is configured to generate a first short-circuit signal when the upper bridge arm is turned on and the voltage at the output end of the step-down circuit is greater than the voltage at the output end;
[0008] The second comparison circuit is connected to the voltage difference across the lower bridge arm and is configured to generate a second short-circuit signal when the lower bridge arm is turned on and the voltage difference across the lower bridge arm is greater than a first reference voltage, and the first reference voltage is greater than the turn-on voltage drop of the lower bridge arm in a non-overcurrent state.
[0009] According to the short-circuit detection circuit of the present application, when a short-circuit fault occurs in the inverter circuit, overcurrent in the upper and lower bridge arms causes the conduction voltage drop to increase, and the output signal levels of the first comparison circuit and the second comparison circuit are reversed. Therefore, based on the signals generated by the first comparison circuit and the second comparison circuit, it is possible to determine whether a short-circuit fault occurs in the inverter circuit including a three-level topology structure. There is no need to use a multi-stage operational amplifier circuit to convert the signal, which reduces the delay on the short-circuit detection path, speeds up the protection speed, and avoids device damage.
[0010] According to one embodiment of the present application, the three-level topology is a T-type three-level topology, the T-type three-level topology has a positive bus, a negative bus, a neutral node and an AC output terminal, the upper bridge arm is electrically connected between the positive bus and the AC output terminal, the lower bridge arm is electrically connected between the AC output terminal and the neutral node, the step-down circuit is electrically connected to the positive bus, the first comparison circuit is electrically connected to the AC output terminal, and the second comparison circuit is electrically connected to the neutral node and the AC output terminal respectively; or,
[0011] The upper bridge arm is electrically connected between the neutral node and the AC output terminal, the lower bridge arm is electrically connected between the AC output terminal and the negative bus, the step-down circuit is electrically connected to the neutral node, the first comparison circuit is electrically connected to the AC output terminal, and the second comparison circuit is electrically connected to the AC output terminal and the negative bus respectively.
[0012] According to one embodiment of the present application, the step-down circuit includes a Zener diode, a cathode of the Zener diode is electrically connected to the first comparison circuit, and an anode of the Zener diode is electrically connected to the input end of the upper bridge arm.
[0013] According to one embodiment of the present application, the first comparison circuit includes:
[0014] A first comparator, wherein a positive phase input terminal of the first comparator is electrically connected to the step-down circuit, and a negative phase input terminal of the first comparator is electrically connected to an output terminal of an upper bridge arm;
[0015] The first pull-up circuit is electrically connected to the output terminal of the first comparator and is configured to pull up the output voltage of the first comparator to generate a first signal to be tested when the upper bridge arm is turned on.
[0016] According to one embodiment of the present application, the first pull-up circuit includes:
[0017] A first pull-up resistor, wherein a first end of the first pull-up resistor is connected to a PWM signal driving an upper bridge arm, and a second end of the first pull-up resistor is electrically connected to an output end of the first comparator;
[0018] A first diode, wherein an anode of the first diode is electrically connected to a first end of the first pull-up resistor, and a cathode of the first diode is electrically connected to a second end of the first pull-up resistor.
[0019] According to one embodiment of the present application, the first comparison circuit also includes a third comparator, which is electrically connected to the output end of the first comparator and is configured to generate a first short-circuit signal when the first measured voltage of the first measured signal is greater than the second reference voltage, and the second reference voltage is less than the first measured voltage.
[0020] According to one embodiment of the present application, the short circuit detection circuit further includes a reference circuit, the reference circuit is configured to generate a first reference voltage, and the second comparison circuit includes:
[0021] A second comparator, wherein a positive phase input terminal of the second comparator is electrically connected to the lower bridge arm, and a negative phase input terminal of the second comparator is electrically connected to the reference circuit;
[0022] The second pull-up circuit is electrically connected to the output terminal of the second comparator and is configured to pull up the output voltage of the second comparator to generate a second signal to be tested when the upper bridge arm is turned on.
[0023] According to one embodiment of the present application, the second pull-up circuit includes:
[0024] A second pull-up resistor, wherein a first end of the second pull-up resistor is connected to the PWM signal driving the lower bridge arm, and a second end of the second pull-up resistor is electrically connected to the output end of the second comparator;
[0025] A second diode, an anode of the second diode is electrically connected to the first end of the second pull-up resistor, and a cathode of the second diode is electrically connected to the second end of the second pull-up resistor.
[0026] According to one embodiment of the present application, the second comparison circuit also includes a fourth comparator, which is electrically connected to the output end of the second comparator and is configured to generate a second short-circuit signal when the second measured voltage of the second measured signal is greater than the third reference voltage, and the third reference voltage is less than the second measured voltage.
[0027] In a second aspect, the present application provides an inverter, which includes the above-mentioned short-circuit detection circuit.
[0028] According to the inverter of the present application, when a short-circuit fault occurs in the inverter, overcurrent in the upper and lower bridge arms causes the conduction voltage drop to increase, and the output signal levels of the first comparison circuit and the second comparison circuit are reversed. Therefore, based on the signals generated by the first comparison circuit and the second comparison circuit, it is possible to determine whether a short-circuit fault occurs in the inverter including a three-level topology structure. There is no need to use a multi-stage operational amplifier circuit to convert the signal, which reduces the delay on the short-circuit detection path, speeds up the protection speed, and avoids device damage.
[0029] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:
[0031] Figure 1 is a schematic diagram of a T-type three-level topology structure provided in an embodiment of the present application;
[0032] Figure 2 It is one of the structural schematic diagrams of the short circuit detection circuit provided in the embodiment of the present application;
[0033] Figure 3 This is the second structural schematic diagram of the short circuit detection circuit provided in the embodiment of the present application;
[0034] Figure 4 This is the third structural schematic diagram of the short-circuit detection circuit provided in the embodiment of the present application.
[0035] Reference numerals:
[0036] Buck circuit 110, first comparison circuit 120, first comparator 121, first pull-up circuit 122, third comparator 123, second comparison circuit 130, second comparator 131, second pull-up circuit 132, fourth comparator 133, third pull-up circuit 140, first voltage divider circuit 151, second voltage divider circuit 152, third voltage divider circuit 153, fourth voltage divider circuit 154, fifth voltage divider circuit 155, sixth voltage divider circuit 156, first bias circuit 161, second bias circuit 162, first to fourth switch tubes T1-T4, first to third capacitors C1-C3, first to third pull-up resistors R1-R3, first to second diodes D1-D2, first to second voltage divider resistors R4-R5, neutral node NE, AC output terminal A, voltage regulator tube ZD. DETAILED DESCRIPTION
[0037] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.
[0038] In the following description, "circuit" refers to a conductive loop composed of at least one element or subcircuit through electrical connection or electromagnetic connection. When an element or circuit is said to be "connected to" another element or an element / circuit is said to be "connected between" two nodes, it can be directly connected to another element or there can be an intermediate element. The connection between the elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly connected to" another element, it means that there is no intermediate element between the two.
[0039] In the description, the terms "first", "second", etc. are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the numerical descriptors used in this way are interchangeable where appropriate, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.
[0040] In addition, descriptions with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" etc. mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.
[0041] The three-level topology usually uses high-voltage power devices such as IGBT. Since the device itself does not have a short-circuit protection function, it is very easy to cause damage to the device when a short-circuit fault occurs in the circuit in which the device is used, such as a short circuit at the inverter circuit port.
[0042] In the related art, a Hall current sampling scheme is usually adopted to implement short-circuit protection. This scheme converts the sampled current into a voltage signal, and uses a multi-stage operational amplifier circuit and a comparison circuit to determine the circuit short-circuit fault based on the voltage signal. However, each stage of the operational amplifier circuit and the comparison circuit has a device response delay. Therefore, there is a long delay in determining whether a short-circuit fault occurs in the circuit, which makes the actual current protection point higher than the theoretically calculated protection point, causing device damage.
[0043] The present application proposes a short-circuit detection circuit and an inverter, which can determine whether a short-circuit fault occurs in an inverter circuit including a three-level topology structure according to the signal generated by the first comparison circuit 120 and the second comparison circuit 130, thereby reducing the delay on the short-circuit detection path, speeding up the protection speed, and avoiding device damage. In order to explain the solution of the present application more clearly, a T-type three-level topology structure is used as an example for explanation.
[0044] Reference Figure 1 , Figure 1A T-type three-level topology is shown. The T-type three-level topology has a positive bus and a negative bus, and a first capacitor C1 and a second capacitor C2 are arranged between the positive bus and the negative bus. The first end of the first capacitor C1 is electrically connected to the positive bus, the second end of the first capacitor C1 is electrically connected to the first end of the second capacitor C2, the first end of the second capacitor C2 is electrically connected to the second end of the first capacitor C1, the second end of the second capacitor C2 is electrically connected to the negative bus, and the node where the second end of the first capacitor C1 and the first end of the second capacitor C2 are connected is the neutral node NE.
[0045] The T-type three-level topology structure includes a first switch tube T1, a second switch tube T2, a third switch tube T3 and a fourth switch tube T4. The upper bridge arm includes the first switch tube T1 and the third switch tube T3, and the lower bridge arm includes the second switch tube T2 and the fourth switch tube T4. The input end of the first switch tube T1 is electrically connected to the positive bus, the output end of the first switch tube T1 is electrically connected to the input end of the fourth switch tube, the output end of the fourth switch tube T4 is electrically connected to the negative bus, and the node where the output end of the first switch tube T1 and the input end of the fourth switch tube T4 are connected is the AC output end A. The input end of the second switch tube T2 is electrically connected to the neutral node NE, the output end of the second switch tube T2 is electrically connected to the input end of the third switch tube T3, and the output end of the third switch tube T3 is electrically connected to the AC output end A.
[0046] The switch tube may be a MOS tube or an IGBT, the input end of the switch tube is a source or a collector, and the output end of the switch tube is a drain or an emitter.
[0047] Reference Figure 2 , Figure 2 A short circuit detection circuit is shown. An embodiment of the present application proposes a short circuit detection circuit, which is applied to a three-level topology structure. The three-level topology structure includes an upper bridge arm and a lower bridge arm. The short circuit detection circuit includes: a buck circuit 110, a first comparison circuit 120, and a second comparison circuit 130. The input end of the buck circuit 110 is electrically connected to the input end of the upper bridge arm, and the voltage reduction amplitude of the input end of the buck circuit 110 is greater than the turn-on voltage drop of the upper bridge arm in a non-overcurrent state; the first comparison circuit 120 is electrically connected to the output end of the buck circuit 110 and the output end of the upper bridge arm respectively, and the potential of the input end is higher than the potential of the output end. The first comparison circuit 120 is configured to generate a first short circuit signal when the upper bridge arm is turned on and the voltage at the output end of the buck circuit is greater than the voltage at the output end; the second comparison circuit 130 is connected to the voltage difference at both ends of the lower bridge arm, and is configured to generate a second short circuit signal when the lower bridge arm is turned on and the voltage difference at both ends of the lower bridge arm is greater than the first reference voltage, and the first reference voltage is greater than the turn-on voltage drop of the lower bridge arm in a non-overcurrent state.
[0048] It should be noted that in the aforementioned T-type three-level topology structure, the first switch tube T1 and the second switch tube T2 form a pair of complementary switch tubes, and the first switch tube T1 and the second switch tube T2 are turned on alternately, and the third switch tube T3 and the fourth switch tube T4 form a pair of complementary switch tubes, and the third switch tube T3 and the fourth switch tube T4 are turned on alternately. In the loop formed by the first switch tube T1 and the second switch tube T2, the first switch tube T1 is the upper bridge arm corresponding to the present embodiment, and the second switch tube T2 is the lower bridge arm corresponding to the present embodiment. In the loop formed by the third switch tube T3 and the fourth switch tube T4, the third switch tube T3 is the upper bridge arm corresponding to the present embodiment, and the fourth switch tube T4 is the lower bridge arm corresponding to the present embodiment.
[0049] The input end of the buck circuit 110 is electrically connected to the input end of the upper bridge arm, and the voltage at the input end of the upper bridge arm is the target voltage after being bucked by the buck circuit 110. When the upper bridge arm is not overcurrent, the difference between the voltage at the input end and the target voltage is greater than the turn-on voltage drop of the upper bridge arm. When the upper bridge arm is overcurrent, the turn-on voltage drop of the upper bridge arm increases, and the difference between the voltage at the input end and the target voltage is less than the turn-on voltage drop of the upper bridge arm when the upper bridge arm is overcurrent.
[0050] The first comparison circuit 120 is mainly used to compare the target voltage and the voltage at the output end of the upper bridge arm. When the upper bridge arm is not overcurrent, the voltage at the output end of the upper bridge arm is the difference between the voltage at the input end and the turn-on voltage drop of the upper bridge arm. Since the difference between the voltage at the input end and the target voltage is greater than the turn-on voltage drop of the upper bridge arm at this time, the voltage at the output end of the upper bridge arm is greater than the target voltage when the upper bridge arm is not overcurrent. When the upper bridge arm is in an overcurrent state, the voltage at the output end of the upper bridge arm is still the difference between the voltage at the input end and the turn-on voltage drop of the upper bridge arm, and the difference between the voltage at the input end and the target voltage is less than the turn-on voltage drop of the upper bridge arm at this time. At this time, when the upper bridge arm is overcurrent, the voltage at the output end of the upper bridge arm is less than the target voltage. Therefore, the first comparison circuit 120 compares the target voltage and the voltage at the output end of the upper bridge arm, and can determine whether a short circuit fault occurs in the inverter circuit including a three-level topology structure when the upper bridge arm is turned on.
[0051] The second comparison circuit 130 is mainly used to compare the voltage difference at both ends of the lower bridge arm with the first reference voltage. When the lower bridge arm is not overcurrent, the voltage difference at both ends of the lower bridge arm is the turn-on voltage drop of the lower bridge arm. At this time, the first reference voltage is greater than the turn-on voltage drop of the lower bridge arm. Therefore, when the lower bridge arm is not overcurrent, the voltage difference at both ends of the lower bridge arm is less than the first reference voltage. When the lower bridge arm is in an overcurrent state, the turn-on voltage drop of the lower bridge arm increases, the first reference voltage is less than the turn-on voltage drop of the lower bridge arm, and the voltage difference at both ends of the lower bridge arm is still the turn-on voltage drop of the lower bridge arm. At this time, the voltage difference at both ends of the lower bridge arm is less than the first reference voltage. Therefore, the second comparison circuit 130 compares the voltage difference at both ends of the lower bridge arm with the first reference voltage, and can determine whether a short circuit fault occurs in the inverter circuit including a three-level topology structure when the lower bridge arm is turned on.
[0052] According to the short-circuit detection circuit of the present application, when a short-circuit fault occurs in the inverter circuit, overcurrent in the upper and lower bridge arms causes the conduction voltage drop to increase, and the output signal levels of the first comparison circuit 120 and the second comparison circuit 130 are reversed. Therefore, based on the signals generated by the first comparison circuit 120 and the second comparison circuit 130, it is possible to determine whether a short-circuit fault occurs in the inverter circuit including a three-level topology structure. There is no need to use a multi-stage operational amplifier circuit to convert the signal, which reduces the delay on the short-circuit detection path, speeds up the protection speed, and avoids device damage.
[0053] Reference Figure 3 , Figure 3 A short circuit detection circuit is shown. In some embodiments, the three-level topology is a T-type three-level topology, the T-type three-level topology has a positive bus, a neutral node NE and an AC output terminal A, the upper bridge arm is electrically connected between the positive bus and the AC output terminal A, the lower bridge arm is electrically connected between the AC output terminal A and the neutral node NE, the buck circuit 110 is electrically connected to the positive bus, the first comparison circuit 120 is electrically connected to the AC output terminal A, and the second comparison circuit 130 is electrically connected to the neutral node NE and the AC output terminal A, respectively.
[0054] When the first switch tube T1 is turned on, the step-down circuit 110 is electrically connected to the positive bus, and the first comparison circuit 120 is electrically connected to the step-down circuit 110 and the AC output terminal A, respectively. At this time, the voltage of the AC output terminal A is equal to the difference between the voltage of the positive bus and the turn-on voltage drop of the first switch tube T1. When the first switch tube T1 is not overcurrent, the difference between the positive bus and the target voltage is greater than the turn-on voltage drop of the first switch tube T1. When the first switch tube T1 is overcurrent, the turn-on voltage drop of the first switch tube T1 increases, and the difference between the positive bus and the target voltage is less than the turn-on voltage drop of the first switch tube T1. If the target voltage is less than the voltage of the AC output terminal A, it indicates that the first switch tube T1 is not overcurrent; if the target voltage is greater than the voltage of the AC output terminal A, it indicates that the first switch tube T1 is overcurrent, that is, it indicates that a short circuit fault occurs in the inverter circuit including the three-level topology structure.
[0055] When the second switch tube T2 is turned on, the second comparison circuit 130 is electrically connected to the neutral node NE and the AC output terminal A respectively, the voltage between the neutral node NE and the AC output terminal A is equal to the sum of the turn-on voltage drops of the second switch tube T2 and the third switch tube T3, the first reference voltage is greater than the sum of the turn-on voltage drops of the second switch tube T2 and the third switch tube T3 when the second switch tube T2 is not overcurrent, and is less than the sum of the turn-on voltage drops of the second switch tube T2 and the third switch tube T3 when the second switch tube T2 is overcurrent. If the first reference voltage is greater than the voltage between the neutral node NE and the AC output terminal A, it indicates that the second switch tube T2 is not overcurrent; if the first reference voltage is less than the voltage between the neutral node NE and the AC output terminal A, it indicates that the second switch tube T2 is overcurrent, that is, it indicates that a short circuit fault occurs in the inverter circuit including the three-level topology structure.
[0056] Reference Figure 4 , Figure 4 A short circuit detection circuit is shown. In some embodiments, the three-level topology is a T-type three-level topology, the T-type three-level topology has a negative bus, a neutral node NE and an AC output terminal A, the upper bridge arm is electrically connected between the neutral node NE and the AC output terminal A, the lower bridge arm is electrically connected between the AC output terminal A and the negative bus, the buck circuit 110 is electrically connected to the neutral node NE, the first comparison circuit 120 is electrically connected to the AC output terminal A, and the second comparison circuit 130 is electrically connected to the AC output terminal A and the negative bus, respectively.
[0057] When the third switch tube T3 is turned on, the step-down circuit 110 is electrically connected to the neutral node NE, and the first comparison circuit 120 is electrically connected to the AC output terminal A. At this time, the voltage of the AC output terminal A is equal to the difference between the voltage of the neutral node NE and the sum of the turn-on voltage drops of the second switch tube T2 and the third switch tube T3. When the third switch tube T3 is not overcurrent, the difference between the neutral node NE and the target voltage is greater than the sum of the turn-on voltage drops of the second switch tube T2 and the third switch tube T3. When the third switch tube T3 is overcurrent, the turn-on voltage drop of the third switch tube T3 increases, and the difference between the neutral node NE and the target voltage is less than the sum of the turn-on voltage drops of the second switch tube T2 and the third switch tube T3. If the target voltage is less than the voltage of the AC output terminal A, it indicates that the third switch tube T3 is not overcurrent; if the target voltage is greater than the voltage of the AC output terminal A, it indicates that the third switch tube T3 is overcurrent, that is, it indicates that a short circuit fault occurs in the inverter circuit including the three-level topology structure.
[0058] When the fourth switch tube T4 is turned on, the second comparison circuit 130 is electrically connected to the AC output terminal A and the negative bus, respectively. The voltage between the AC output terminal A and the negative bus is equal to the turn-on voltage drop of the fourth switch tube T4. The first reference voltage is greater than the turn-on voltage drop of the fourth switch tube T4 when there is no overcurrent, and is less than the turn-on voltage drop of the fourth switch tube T4 when there is overcurrent. If the first reference voltage is greater than the voltage between the AC output terminal A and the negative bus, it indicates that the fourth switch tube T4 is not overcurrent; if the first reference voltage is less than the voltage between the AC output terminal A and the negative bus, it indicates that the fourth switch tube T4 is overcurrent, that is, it indicates that a short circuit fault occurs in the inverter circuit including the three-level topology structure.
[0059] Continue to refer to Figure 3 In some embodiments, the step-down circuit 110 includes a voltage regulator tube ZD, a cathode of the voltage regulator tube ZD is electrically connected to the first comparison circuit 120, and an anode of the voltage regulator tube ZD is electrically connected to the input end of the upper bridge arm.
[0060] When the voltage regulator tube ZD is in a breakdown state, the voltage drop across the two ends changes very little, so a fixed voltage drop can be provided to achieve the effect of reducing the voltage at the input end of the upper bridge arm.
[0061] In some embodiments, the first comparison circuit 120 includes: a first comparator 121 and a first pull-up circuit 122. The positive phase input terminal of the first comparator 121 is electrically connected to the buck circuit 110, and the negative phase input terminal of the first comparator 121 is electrically connected to the output terminal of the upper bridge arm; the first pull-up circuit 122 is electrically connected to the output terminal of the first comparator 121, and is configured to pull up the output voltage of the first comparator 121 when the upper bridge arm is turned on, so as to generate a first signal to be tested.
[0062] The first comparator 121 has a positive input terminal and a negative input terminal, the positive input terminal is electrically connected to the buck circuit 110 to access the target voltage, and the negative input terminal is electrically connected to the output terminal of the upper bridge arm to access the voltage of the output terminal of the upper bridge arm. When the target voltage is greater than the voltage of the output terminal of the upper bridge arm, the signal at the output terminal of the first comparator 121 is pulled up by the first pull-up circuit 122 to generate a high-level signal, i.e., the first signal to be tested; when the target voltage is less than the voltage of the output terminal of the upper bridge arm, the signal at the output terminal of the first comparator 121 is pulled up by the first pull-up circuit 122 to generate a low-level signal.
[0063] In some embodiments, the first pull-up circuit 122 includes a first pull-up resistor R1 and a first diode D1. The first end of the first pull-up resistor R1 is connected to the PWM signal driving the upper bridge arm, and the second end of the first pull-up resistor R1 is electrically connected to the output end of the first comparator 121; the anode of the first diode D1 is electrically connected to the first end of the first pull-up resistor R1, and the cathode of the first diode D1 is electrically connected to the second end of the first pull-up resistor R1.
[0064] When the upper bridge arm is turned on, the first pull-up resistor R1 is connected to a high-level signal to provide a sufficiently large current to the output end of the first comparator 121, so that when the target voltage is greater than the voltage at the output end of the upper bridge arm, the first pull-up signal is provided to the output end of the first comparator 121 to keep the output end of the first comparator 121 in a high-level state. The first diode D1 is mainly used to maintain the stability of the signal when the PWM signal connected to the first end of the first pull-up resistor R1 switches between a high level and a low level, so as to avoid circuit failure caused by signal pulses.
[0065] As an example, the first end of the first pull-up resistor R1 is connected to the signal that drives the third switch tube T3. The third switch tube T3 is turned on when the driving signal is at a high level. When the third switch tube T3 in the upper bridge arm is turned on, the first end of the first pull-up resistor R1 is connected to the high-level signal, and a pull-up signal is provided to the output end of the first comparator 121 through the first pull-up resistor R1. When the target voltage is greater than the voltage of the AC output terminal A, the current passing through the first pull-up resistor R1 keeps the output end of the first comparator 121 in a high-level state.
[0066] In some embodiments, the first comparison circuit 120 also includes a third comparator 123, which is electrically connected to the output end of the first comparator 121 and is configured to generate a first short-circuit signal when the first measured voltage of the first measured signal is greater than the second reference voltage, and the second reference voltage is less than the first measured voltage.
[0067] The third comparator 123 has a positive input terminal and a negative input terminal, the positive input terminal is connected to the second reference voltage, and the negative input terminal is electrically connected to the output terminal of the first comparator 121 to connect to the voltage of the output terminal of the first comparator 121. When the first voltage to be measured is greater than the second reference voltage, the third comparator 123 outputs a low level signal, that is, a first short-circuit signal.
[0068] When the output end of the first comparator 121 outputs a low-level signal, it is still a low-level signal after passing through the first pull-up circuit 122, and the second reference voltage is greater than zero voltage. At this time, the third comparator 123 outputs a high-level signal, indicating that there is no overcurrent in the switch tube in the upper bridge arm; when the output end of the first comparator 121 outputs a high-level signal, it is the first test signal after passing through the first pull-up circuit 122. Since the second reference voltage is less than the first test voltage, the third comparator 123 outputs a low-level signal at this time, indicating that there is an overcurrent in the switch tube in the upper bridge arm.
[0069] Continue to refer to Figure 4In some embodiments, the short circuit detection circuit further includes a reference circuit, and the reference circuit is configured to generate a first reference voltage. The second comparison circuit 130 includes a second comparator 131 and a second pull-up circuit 132. The positive phase input terminal of the second comparator 131 is electrically connected to the lower bridge arm, and the negative phase input terminal of the second comparator 131 is electrically connected to the reference circuit; the second pull-up circuit 132 is electrically connected to the output terminal of the second comparator 131, and is configured to pull up the output voltage of the second comparator 131 when the upper bridge arm is turned on, so as to generate a second signal to be tested.
[0070] The second comparator 131 has a positive input terminal and a negative input terminal, the positive input terminal is electrically connected to the lower bridge arm to access the voltage at both ends of the lower bridge arm, and the negative input terminal is electrically connected to the reference circuit to access the first reference voltage. When the voltage at both ends of the lower bridge arm is greater than the first reference voltage, the signal at the output end of the second comparator 131 is pulled up by the second pull-up circuit 132 to generate a high-level signal, i.e., the second signal to be tested; when the voltage at both ends of the lower bridge arm is less than the first reference voltage, the signal at the output end of the second comparator 131 is pulled up by the second pull-up circuit 132 to generate a low-level signal.
[0071] In some embodiments, the second pull-up circuit 132 includes a second pull-up resistor R2 and a second diode D2. The first end of the second pull-up resistor R2 is connected to the PWM signal driving the lower bridge arm, and the second end of the second pull-up resistor R2 is electrically connected to the output end of the second comparator 131; the second diode D2, the anode of the second diode D2 is electrically connected to the first end of the second pull-up resistor R2, and the cathode of the second diode D2 is electrically connected to the second end of the second pull-up resistor R2.
[0072] When the lower bridge arm is turned on, the second pull-up resistor R2 is connected to a high-level signal to provide a sufficiently large current to the output end of the second comparator 131, so that when the voltage across the lower bridge arm is greater than the first reference voltage, a second pull-up signal is provided to the output end of the second comparator 131 to keep the output end of the second comparator 131 in a high-level state. The second diode D2 is mainly used to maintain the stability of the signal when the PWM signal connected to the first end of the second pull-up resistor R2 switches between a high level and a low level, so as to avoid circuit failure caused by signal pulses.
[0073] As an example, the first end of the second pull-up resistor R2 is connected to the signal that drives the fourth switch tube T4. The fourth switch tube T4 is turned on when the driving signal is at a high level. When the fourth switch tube T4 in the lower bridge arm is turned on, the first end of the second pull-up resistor R2 is connected to the high-level signal, and a pull-up signal is provided to the output end of the second comparator 131 through the second pull-up resistor R2. When the voltage between the AC output terminal A and the negative bus is greater than the first reference voltage, the current passing through the second pull-up resistor R2 keeps the output end of the second comparator 131 in a high-level state.
[0074] In some embodiments, the second comparison circuit 130 also includes a fourth comparator 133, which is electrically connected to the output end of the second comparator 131 and is configured to generate a second short-circuit signal when the second measured voltage of the second measured signal is greater than the third reference voltage, and the third reference voltage is less than the second measured voltage.
[0075] The fourth comparator 133 has a positive input terminal and a negative input terminal, the positive input terminal is connected to the third reference voltage, and the negative input terminal is electrically connected to the output terminal of the second comparator 131 to connect to the voltage of the output terminal of the second comparator 131. When the second voltage to be measured is greater than the third reference voltage, the fourth comparator 133 outputs a low level signal, that is, a second short-circuit signal.
[0076] When the output end of the second comparator 131 outputs a low-level signal, it is still a low-level signal after passing through the second pull-up circuit 132, and the third reference voltage is greater than zero voltage. At this time, the fourth comparator 133 outputs a high-level signal, indicating that there is no overcurrent in the switch tube in the lower bridge arm; when the output end of the second comparator 131 outputs a low-level signal, it is the second test signal after passing through the second pull-up circuit 132. Since the third reference voltage is less than the second test voltage, the fourth comparator 133 outputs a low-level signal at this time, indicating that there is an overcurrent in the switch tube in the lower bridge arm.
[0077] In some embodiments, the short circuit detection circuit further includes a third pull-up circuit 140. The third pull-up circuit 140 includes a third pull-up resistor R3, which is electrically connected to the output terminals of the third comparator 123 and the fourth comparator 133, and is configured to provide a third pull-up signal to the output terminals of the third comparator 123 and the fourth comparator 133, so that the third comparator 123 or the fourth comparator 133 outputs a high-level signal, thereby stabilizing the signal in a high-level state.
[0078] In some embodiments, the short circuit detection circuit further includes a first voltage divider circuit 151 , a second voltage divider circuit 152 , a third voltage divider circuit 153 , a fourth voltage divider circuit 154 , a fifth voltage divider circuit 155 and a sixth voltage divider circuit 156 .
[0079] The first voltage-dividing circuit 151 includes a first voltage-dividing resistor R4, a second voltage-dividing resistor R5 and a third capacitor C3. The first end of the first voltage-dividing resistor R4 is electrically connected to the step-down circuit 110, the second end of the first voltage-dividing resistor R4 is electrically connected to the first end of the second voltage-dividing resistor R5 and the first end of the third capacitor C3 respectively, the second end of the second voltage-dividing resistor R5 and the second end of the third capacitor C3 are grounded, and the target voltage can be divided by connecting the first voltage-dividing resistor R4 and the second resistor in series to prevent the target voltage from being too large and damaging the first comparator 121.
[0080] The second voltage divider circuit 152 is electrically connected to the negative phase input terminal of the first comparator 121, the third voltage divider circuit 153 is electrically connected to the positive phase input terminal of the second comparator 131, the fourth voltage divider circuit 154 is electrically connected to the negative phase input terminal of the second comparator 131, the fifth voltage divider circuit 155 is electrically connected to the positive phase input terminal of the third comparator 123, and the sixth voltage divider circuit 156 is electrically connected to the positive phase input terminal of the fourth comparator 133.
[0081] The structures and principles of the second voltage divider circuit 152 , the third voltage divider circuit 153 , the fourth voltage divider circuit 154 , the fifth voltage divider circuit 155 and the sixth voltage divider circuit 156 may refer to the first voltage divider circuit 151 , and will not be described in detail here.
[0082] In some embodiments, the short circuit detection circuit further includes a first bias circuit 161 and a second bias circuit 162. The first bias circuit 161 is electrically connected to the negative phase input terminal of the first comparator 121, and is configured to ensure that the voltage input to the negative phase input terminal of the first comparator 121 is greater than zero voltage, so as to facilitate the first comparator 121 to make a comparison; the second bias circuit 162 is electrically connected to the positive phase input terminal of the second comparator 131, and is configured to ensure that the voltage input to the positive phase input terminal of the second comparator 131 is greater than zero voltage, so as to facilitate the second comparator 131 to make a comparison.
[0083] An embodiment of the present application provides an inverter, which includes the above-mentioned short-circuit detection circuit.
[0084] The inverter also includes the three-level topology structure in the above embodiment. The specific structure and principle of the three-level topology structure and the short-circuit detection circuit can refer to the above embodiments, and this implementation will not be repeated here.
[0085] According to the inverter of the present application, when a short-circuit fault occurs in the inverter, overcurrent in the upper and lower bridge arms causes the conduction voltage drop to increase, and the output signal levels of the first comparison circuit 120 and the second comparison circuit 130 are reversed. Therefore, based on the signals generated by the first comparison circuit 120 and the second comparison circuit 130, it is possible to determine whether a short-circuit fault occurs in the inverter including a three-level topology structure. There is no need to use a multi-stage operational amplifier circuit to convert the signal, which reduces the delay on the short-circuit detection path, speeds up the protection speed, and avoids device damage.
[0086] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.
Claims
1. A short circuit detection circuit, characterized in that: Applied to a three-level topology structure, the three-level topology structure includes an upper bridge arm and a lower bridge arm, and the short-circuit detection circuit includes: A step-down circuit, wherein the input end of the step-down circuit is electrically connected to the input end of the upper bridge arm, and the voltage reduction amplitude of the input end of the step-down circuit is greater than the turn-on voltage drop of the upper bridge arm in a non-overcurrent state; a first comparison circuit, electrically connected to the output end of the step-down circuit and the output end of the upper bridge arm, respectively, the first comparison circuit being configured to generate a first short-circuit signal when the upper bridge arm is turned on and the voltage at the output end of the step-down circuit is greater than the voltage at the output end; and / or, The second comparison circuit is connected to the voltage difference across the lower bridge arm and is configured to generate a second short-circuit signal when the lower bridge arm is turned on and the voltage difference across the lower bridge arm is greater than a first reference voltage, and the first reference voltage is greater than the turn-on voltage drop of the lower bridge arm in a non-overcurrent state.
2. The short circuit detection circuit according to claim 1, characterized in that: The three-level topology structure is a T-type three-level topology structure, and the T-type three-level topology structure has a positive bus, a negative bus, a neutral node and an AC output terminal; The upper bridge arm is electrically connected between the positive bus and the AC output end, the lower bridge arm is electrically connected between the AC output end and the neutral node, the step-down circuit is electrically connected to the positive bus, the first comparison circuit is electrically connected to the AC output end, and the second comparison circuit is electrically connected to the neutral node and the AC output end respectively; or the upper bridge arm is electrically connected between the neutral node and the AC output end, the lower bridge arm is electrically connected between the AC output end and the negative bus, the step-down circuit is electrically connected to the neutral node, the first comparison circuit is electrically connected to the AC output end, and the second comparison circuit is electrically connected to the AC output end and the negative bus respectively.
3. The short circuit detection circuit according to any one of claims 1 or 2, characterized in that: The step-down circuit includes a voltage regulator tube, a cathode of the voltage regulator tube is electrically connected to the first comparison circuit, and an anode of the voltage regulator tube is electrically connected to the input end of the upper bridge arm.
4. The short circuit detection circuit according to any one of claims 1 or 2, characterized in that: The first comparison circuit comprises: A first comparator, wherein a positive phase input terminal of the first comparator is electrically connected to the step-down circuit, and a negative phase input terminal of the first comparator is electrically connected to an output terminal of the upper bridge arm; The first pull-up circuit is electrically connected to the output end of the first comparator and is configured to pull up the output voltage of the first comparator to generate a first signal to be tested when the upper bridge arm is turned on.
5. The short circuit detection circuit according to claim 4, characterized in that: The first pull-up circuit comprises: a first pull-up resistor, wherein a first end of the first pull-up resistor is connected to a PWM signal driving the upper bridge arm, and a second end of the first pull-up resistor is electrically connected to an output end of the first comparator; A first diode, wherein an anode of the first diode is electrically connected to a first end of the first pull-up resistor, and a cathode of the first diode is electrically connected to a second end of the first pull-up resistor.
6. The short circuit detection circuit according to claim 5, characterized in that: The first comparison circuit also includes a third comparator, which is electrically connected to the output end of the first comparator and is configured to generate a first short-circuit signal when the first measured voltage of the first measured signal is greater than a second reference voltage, and the second reference voltage is less than the first measured voltage.
7. The short circuit detection circuit according to any one of claims 1 or 2, characterized in that: The short circuit detection circuit further includes a reference circuit, wherein the reference circuit is configured to generate a first reference voltage, and the second comparison circuit includes: A second comparator, wherein a positive phase input terminal of the second comparator is electrically connected to the lower bridge arm, and a negative phase input terminal of the second comparator is electrically connected to the reference circuit; The second pull-up circuit is electrically connected to the output terminal of the second comparator and is configured to pull up the output voltage of the second comparator to generate a second signal to be tested when the upper bridge arm is turned on.
8. The short circuit detection circuit according to claim 7, characterized in that: The second pull-up circuit comprises: a second pull-up resistor, wherein a first end of the second pull-up resistor is connected to the PWM signal driving the lower bridge arm, and a second end of the second pull-up resistor is electrically connected to an output end of the second comparator; A second diode, wherein an anode of the second diode is electrically connected to the first end of the second pull-up resistor, and a cathode of the second diode is electrically connected to the second end of the second pull-up resistor.
9. The short circuit detection circuit according to claim 8, characterized in that: The second comparison circuit also includes a fourth comparator, which is electrically connected to the output end of the second comparator and is configured to generate a second short-circuit signal when the second voltage to be measured of the second signal to be measured is greater than a third reference voltage, and the third reference voltage is less than the second voltage to be measured.
10. An inverter, characterized in that: The invention comprises a short circuit detection circuit according to any one of claims 1 to 9.